Michael L. Bushnell

96 papers A* 8A 11C 1Misc 39Journal 26Unranked 11

Year	Rank	Type	Title / Venue / Authors
2009	J	`jnl`	Variable Input Delay CMOS Logic for Low Power Design. IEEE Trans. Very Large Scale Integr. Syst. Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell
2008	Misc	`conf`	A Jitter Reduction Circuit Using Autocorrelation for Phase-Locked Loops and Serializer-Deserializer (SERDES) Circuits. VLSI Design Hari Vijay Venkatanarayanan, Michael L. Bushnell
2008	Misc	`conf`	Fault Nodes in Implication Graph for Equivalence/Dominance Collapsing, and Identifying Untestable and Independent Faults. VTS Rajamani Sethuram, Michael L. Bushnell, Vishwani D. Agrawal
2007	Misc	`conf`	A Neural Net Branch Predictor to Reduce Power. VLSI Design Rajamani Sethuram, Omar I. Khan, Hari Vijay Venkatanarayanan, Michael L. Bushnell
2007	Misc	`conf`	Analog Circuit Testing Using Auto Regressive Moving Average Models. VLSI Design Jeffrey Ayres, Michael L. Bushnell
2007	Misc	`conf`	Architecture for Variable-Length Combined FFT, DCT, and MWT Transform Hardware for a Multi-ModeWireless System. VLSI Design Rohit Pandey, Michael L. Bushnell
2007	Misc	`conf`	Fault Models and Device Yield of a Large Population of Room Temperature Operation Single-Electron Transistors. VLSI Design Daniel Mazor, Michael L. Bushnell, David J. Mulligan, Richard J. Blaikie
2007	J	`jnl`	Graphical I IEEE Trans. Very Large Scale Integr. Syst. Lan Rao, Michael L. Bushnell, Vishwani D. Agrawal
2007	C	`conf`	Power Grid Analysis of Dynamic Power Cutoff Technology. ISCAS Baozhen Yu, Michael L. Bushnell
2007	A	`conf`	SPARTAN: a spectral and information theoretic approach to partial-scan. ITC Omar I. Khan, Michael L. Bushnell, Suresh Kumar Devanathan, Vishwani D. Agrawal
2007	Misc	`conf`	Test Pattern Generation Using Modulation by Haar Wavelets and Correlation for Sequential BIST. VLSI Design Suresh Kumar Devanathan, Michael L. Bushnell
2007	Misc	`conf`	Zero Cost Test Point Insertion Technique for Structured ASICs. VLSI Design Rajamani Sethuram, Seongmoon Wang, Srimat T. Chakradhar, Michael L. Bushnell
2006	A	`conf`	A novel dynamic power cutoff technique (DPCT) for active leakage reduction in deep submicron CMOS circuits. ISLPED Baozhen Yu, Michael L. Bushnell
2006	Misc	`conf`	Aliasing Analysis of Spectral Statistical Response Compaction Techniques. VLSI Design Omar I. Khan, Michael L. Bushnell
2006	Misc	`conf`	An Area Efficient Mixed-Signal Test Architecture for Systems-on-a-Chip. VLSI Design Hari Vijay Venkatanarayanan, Michael L. Bushnell
2006	Misc	`conf`	Analog Macromodeling for Combined Resistive Vias, Resistive Bridges, and Capacitive Crosstalk Delay Faults. VLSI Design Shweta Chary, Michael L. Bushnell
2006	Misc	`conf`	Automatic Path-Delay Fault Test Generation for Combined Resistive Vias, Resistive Bridges, and Capacitive Crosstalk Delay Faults. VLSI Design Shweta Chary, Michael L. Bushnell
2006	Misc	`conf`	Sequential Spectral ATPG Using the Wavelet Transform and Compaction. VLSI Design Suresh Kumar Devanathan, Michael L. Bushnell
2006	J	`jnl`	Transistor Sizing of Logic Gates to Maximize Input Delay Variability. J. Low Power Electron. Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell
2006	—	`conf`	Zero Cost Test Point Insertion Technique to Reduce Test Set Size and Test Generation Time for Structured ASICs. ATS Rajamani Sethuram, Seongmoon Wang, Srimat T. Chakradhar, Michael L. Bushnell
2005	—	`conf`	Design of Variable Input Delay Gates for Low Dynamic Power Circuits. PATMOS Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell
2005	Misc	`conf`	Using Contrapositive Law in an Implication Graph to Identify Logic Redundancies. VLSI Design Kunal K. Dave, Vishwani D. Agrawal, Michael L. Bushnell
2005	Misc	`conf`	Variable Input Delay CMOS Logic for Low Power Design. VLSI Design Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell
2004	J	`jnl`	A New Classification of Path-Delay Fault Testability in Terms of Stuck-at Faults. J. Comput. Sci. Technol. Subhashis Majumder, Bhargab B. Bhattacharya, Vishwani D. Agrawal, Michael L. Bushnell
2004	Misc	`conf`	A Tuturial on the Emerging Nanotechnology Devices. VLSI Design Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell
2004	Misc	`conf`	CMOS Circuit Design for Minimum Dynamic Power and Highest Speed. VLSI Design Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell
2004	A	`conf`	On Random Pattern Generation with the Selfish Gene Algorithm for Testing Digital Sequential Circuits. ITC Junwu Zhang, Michael L. Bushnell, Vishwani D. Agrawal
2004	A	`conf`	Spectral Analysis for Statistical Response Compaction During Built-In Self-Testing. ITC Omar I. Khan, Michael L. Bushnell
2003	Misc	`conf`	A Fault-Independent Transitive Closure Algorithm for Redundancy Identification. VLSI Design Vishal J. Mehta, Kunal K. Dave, Vishwani D. Agrawal, Michael L. Bushnell
2003	Misc	`conf`	Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program. VLSI Design Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell
2003	Misc	`conf`	New Graphical IDDQ Signatures Reduce Defect Level and Yield Loss. VLSI Design Lan Rao, Michael L. Bushnell, Vishwani D. Agrawal
2002	—	`conf`	A New Transitive Closure Algorithm with Application to Redundancy Identification. DELTA Vivek Gaur, Vishwani D. Agrawal, Michael L. Bushnell
2002	A	`conf`	Analog Macromodeling of Capacitive Coupling Faults in Digital Circuit Interconnects. ITC Aditya D. Sathe, Michael L. Bushnell, Vishwani D. Agrawal
2002	—	`conf`	Electronic Testing for SOC Designers (Tutorial Abstract). ASP-DAC/VLSI Design Vishwani D. Agrawal, Michael L. Bushnell
2001	Misc	`conf`	A Code Transition Delay Model for ADC Test. VLSI Design Sanjay Mohan, Michael L. Bushnell
2000	J	`jnl`	False-Path Removal Using Delay Fault Simulation. J. Electron. Test. Marwan A. Gharaybeh, Vishwani D. Agrawal, Michael L. Bushnell, Carlos G. Parodi
2000	J	`jnl`	Improving path delay testability of sequential circuits. IEEE Trans. Very Large Scale Integr. Syst. Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell
2000	J	`jnl`	Path delay fault simulation of sequential circuits. IEEE Trans. Very Large Scale Integr. Syst. Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell
1999	Misc	`conf`	A Complete Characterization of Path Delay Faults through Stuck-at Faults. VLSI Design Subhashis Majumder, Bhargab B. Bhattacharya, Vishwani D. Agrawal, Michael L. Bushnell
1999	Misc	`conf`	Digital Circuit Design for Minimum Transient Energy and a Linear Programming Method. VLSI Design Vishwani D. Agrawal, Michael L. Bushnell, Ganapathy Parthasarathy, Rajesh Ramadoss
1999	J	`jnl`	Effect of Noise on Analog Circuit Testing. J. Electron. Test. Madhu K. Iyer, Michael L. Bushnell
1999	A	`conf`	Increasing Test Coverage in a VLSI Design Course. ITC Michael L. Bushnell
1999	J	`jnl`	Test Generation for Mixed-Signal Devices Using Signal Flow Graphs. J. Electron. Test. Rajesh Ramadoss, Michael L. Bushnell
1998	A	`conf`	A non-enumerative path delay fault simulator for sequential circuits. ITC Carlos G. Parodi, Vishwani D. Agrawal, Michael L. Bushnell, Shianling Wu
1998	J	`jnl`	A parallel-vector concurrent-fault simulator and generation of single-input-change tests for path-delay faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal
1998	Misc	`conf`	Effect of Noise on Analog Circuit Testing. VTS Madhu K. Iyer, Michael L. Bushnell
1998	—	`conf`	False-Path Removal Using Delay Fault Simulation. Asian Test Symposium Marwan A. Gharaybeh, Vishwani D. Agrawal, Michael L. Bushnell
1998	Misc	`conf`	On Delay-Untestable Paths and Stuck-Fault Redundancy. VTS Subhashis Majumder, Vishwani D. Agrawal, Michael L. Bushnell
1998	Misc	`conf`	Path Delay Testing: Variable-Clock Versus Rated-Clock. VLSI Design Subhashis Majumder, Michael L. Bushnell, Vishwani D. Agrawal
1998	J	`jnl`	Statistical Delay Fault Coverage Estimation for Synchronous Sequential Circuits. J. Electron. Test. Lakshminarayana Pappu, Michael L. Bushnell, Vishwani D. Agrawal, Mandyam-Komar Srinivas
1998	J	`jnl`	The path-status graph with application to delay fault simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal
1998	Misc	`conf`	Towards Simultaneous Delay-Fault Built-In Self-Test and Partial-Scan Insertion. VTS Ganapathy Parthasarathy, Michael L. Bushnell
1997	J	`jnl`	A Functional Decomposition Method for Redundancy Identification and Test Generation. J. Electron. Test. Michael L. Bushnell, John Giraldi
1997	J	`jnl`	Classification and Test Generation for Path-Delay Faults Using Single Struck-at Fault Tests. J. Electron. Test. Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal
1997	Misc	`conf`	Flags and Algebra for Sequential Circuit VNR Path Delay Fault Test Generation. VLSI Design Mandyam-Komar Srinivas, Michael L. Bushnell, Vishwani D. Agrawal
1997	J	`jnl`	Improving a nonenumerative method to estimate path delay fault coverage. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell, Janak H. Patel
1997	J	`jnl`	On variable clock methods for path delay testing of sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell
1996	A	`conf`	An Exact Non-Enumerative Fault Simulator for Path-Delay Faults. ITC Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal
1996	Misc	`conf`	Parallel concurrent path-delay fault simulation using single-input change patterns. VLSI Design Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal
1996	—	`conf`	Redundancy Identification Using Transitive Closure. Asian Test Symposium Vishwani D. Agrawal, Michael L. Bushnell, Qing Lin
1996	J	`jnl`	Sequential circuit test generation using dynamic justification equivalence. J. Electron. Test. Xinghao Chen, Michael L. Bushnell
1996	Misc	`conf`	Statistical path delay fault coverage estimation for synchronous sequential circuits. VLSI Design Lakshminarayana Pappu, Michael L. Bushnell, Vishwani D. Agrawal, Mandyam-Komar Srinivas
1996	Misc	`conf`	Test generation for mixed-signal devices using signal flow graphs. VLSI Design Rajesh Ramadoss, Michael L. Bushnell
1995	Misc	`conf`	A graph approach to DFT hardware placement for robust delay fault BIST. VLSI Design Imtiaz P. Shaik, Michael L. Bushnell
1995	—	`conf`	An adaptive distributed algorithm for sequential circuit test generation. EURO-DAC James Sienicki, Michael L. Bushnell, Prathima Agrawal, Vishwani D. Agrawal
1995	Misc	`conf`	An asynchronous algorithm for sequential circuit test generation on a network of workstations. VLSI Design James Sienicki, Michael L. Bushnell, Prathima Agrawal, Vishwani D. Agrawal
1995	Misc	`conf`	Circuit design for low overhead delay-fault BIST using constrained quadratic 0-1 programming . VTS Imtiaz P. Shaik, Michael L. Bushnell
1995	A	`conf`	Classification and Test Generation for Path-Delay Faults Using Single Stuck-Fault Tests. ITC Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal
1995	J	`jnl`	Fault coverage estimation by test vector sampling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell
1995	—	`conf`	Functional test generation for path delay faults. Asian Test Symposium Mandyam-Komar Srinivas, Vishwani D. Agrawal, Michael L. Bushnell
1995	Misc	`conf`	Generation of search state equivalence for automatic test pattern generation. VLSI Design Xinghao Chen, Michael L. Bushnell
1995	Misc	`conf`	Statistical methods for delay fault coverage analysis. VLSI Design Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell
1994	A*	`conf`	An Efficient Path Delay Fault Coverage Estimator. DAC Keerthi Heragu, Michael L. Bushnell, Vishwani D. Agrawal
1994	—	`conf`	Distributed Computing, Automatic Design, and Error Recovery in the ULYSSES II Framework. EDAC-ETC-EUROASIC Sandip Parikh, Michael L. Bushnell, James Sienicki, Ganesh Ramakrishnan
1994	—	`conf`	Dynamic State and Objective Learning for Sequential Circuit Automatic Test Generation Using Decomposition Equivalence. FTCS Xinghao Chen, Michael L. Bushnell
1994	J	`jnl`	Energy minimization and design for testability. J. Electron. Test. Srimat T. Chakradhar, Vishwani D. Agrawal, Michael L. Bushnell
1994	Misc	`conf`	FACTS: fault coverage estimation by test vector sampling. VTS Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell
1994	Misc	`conf`	Graphical Methodology Language for CAD Frameworks. VLSI Design James Sienicki, Michael L. Bushnell, Sandip Parikh
1994	Misc	`conf`	Neural models for transistor and mixed-level test generation. VTS Carolina L. C. Cooper, Michael L. Bushnell
1993	A*	`conf`	Design for Testability for Path Delay faults in Sequential Circuits. DAC Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell
1992	J	`jnl`	A solvable class of quadratic 0-1 programming. Discret. Appl. Math. Srimat T. Chakradhar, Michael L. Bushnell
1992	A*	`conf`	Delay Fault Models and Test Generation for Random Logic Sequential Circuits. DAC Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell
1991	A	`conf`	Search State Equivalence for Redundancy Identification and Test Generation. ITC John Giraldi, Michael L. Bushnell
1990	A*	`conf`	Automatic Test Generation Using Quadratic 0-1 Programming. DAC Srimat T. Chakradhar, Vishwani D. Agrawal, Michael L. Bushnell
1990	A*	`conf`	EST: The New Frontier in Automatic Test-Pattern Generation. DAC John Giraldi, Michael L. Bushnell
1990	A*	`conf`	MHERTZ: A New Optimization Algorithm for Floorplanning and Global Routing. DAC Daniel R. Brasen, Michael L. Bushnell
1990	J	`jnl`	Neural Net and Boolean Satisfiability Models of Logic Circuits. IEEE Des. Test Comput. Srimat T. Chakradhar, Vishwani D. Agrawal, Michael L. Bushnell, Thomas K. Truong
1990	—	`conf`	Polynomial time solvable fault detection problems. FTCS Srimat T. Chakradhar, Vishwani D. Agrawal, Michael L. Bushnell
1990	J	`jnl`	Toward massively parallel automatic test generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Srimat T. Chakradhar, Michael L. Bushnell, Vishwani D. Agrawal
1989	J	`jnl`	Automated design tool execution in the Ulysses design environment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Michael L. Bushnell, Stephen W. Director
1988	A*	`conf`	A Module Area Estimator for VLSI Layout. DAC Xinghao Chen, Michael L. Bushnell
1988	A	`conf`	Automatic test generation using neural networks. ICCAD Srimat T. Chakradhar, Michael L. Bushnell, Vishwani D. Agrawal
1987	J	`jnl`	ULYSSES - a knowledge-based VLSI design environment. Artif. Intell. Eng. Michael L. Bushnell, Stephen W. Director
1986	J	`jnl`	Guest editorial. Artif. Intell. Eng. Michael L. Bushnell, Pierre Haren
1986	A*	`conf`	VLSI CAD tool integration using the Ulysses environment. DAC Michael L. Bushnell, Stephen W. Director
1984	J	`jnl`	DIF: A framework for VLSI multi-level representation. Integr. David P. LaPotin, Sani R. Nassif, Jayanth V. Rajan, Michael L. Bushnell, John A. Nestor