Michael J. Klaiber

23 papers A 1B 2Misc 4Journal 8Unranked 7

Year	Rank	Type	Title / Venue / Authors
2022	J	`jnl`	Union-Retire for Connected Components Analysis on FPGA. J. Imaging Donald G. Bailey, Michael J. Klaiber
2021	Misc	`conf`	Automated HW/SW co-design for edge AI: state, challenges and steps ahead. CODES+ISSS Oliver Bringmann, Wolfgang Ecker, Ingo Feldner, Adrian Frischknecht, Christoph Gerum, Timo Hämäläinen, Muhammad Abdullah Hanif, Michael J. Klaiber, Daniel Mueller-Gritschneder, Paul Palomero Bernardo, Sebastian Siegfried Prebeck, Muhammad Shafique
2021	J	`jnl`	Enabling Cross-Domain Communication: How to Bridge the Gap between AI and HW Engineers. CoRR Michael J. Klaiber, Axel J. Acosta, Ingo Feldner, Falk Rehm
2021	—	`conf`	Union-Retire: A New Paradigm for Single-Pass Connected Component Analysis. ISGV Donald G. Bailey, Michael J. Klaiber
2020	J	`jnl`	Efficient AI System Design With Cross-Layer Approximate Computing. Proc. IEEE Swagath Venkataramani, Xiao Sun, Naigang Wang, Chia-Yu Chen, Jungwook Choi, Mingu Kang, Ankur Agarwal, Jinwook Oh, Shubham Jain, Tina Babinsky, Nianzheng Cao, Thomas W. Fox, Bruce M. Fleischer, George Gristede, Michael Guillorn, Howard Haynie, Hiroshi Inoue, Kazuaki Ishizaki, Michael J. Klaiber, Shih-Hsien Lo, Gary W. Maier, Silvia M. Mueller, Michael Scheuermann, Eri Ogawa, Marcel Schaal, Mauricio J. Serrano, Joel Silberman, Christos Vezyrtzis, Wei Wang, Fanchieh Yee, Jintao Zhang, Matthew M. Ziegler, Ching Zhou, Moriyoshi Ohara, Pong-Fei Lu, Brian W. Curran, Sunil Shukla, Vijayalakshmi Srinivasan, Leland Chang, Kailash Gopalakrishnan
2019	J	`jnl`	A single-cycle parallel multi-slice connected components analysis hardware architecture. J. Real Time Image Process. Michael J. Klaiber, Donald G. Bailey, Sven Simon
2019	—	`conf`	An End-to-End HW/SW Co-Design Methodology to Design Efficient Deep Neural Network Systems using Virtual Models. INTESA Michael J. Klaiber, Sebastian Vogel, Axel Acosta, Robert Korn, Leonardo Ecco, Kristine Back, Andre Guntoro, Ingo Feldner
2019	J	`jnl`	An End-to-End HW/SW Co-Design Methodology to Design Efficient Deep Neural Network Systems using Virtual Models. CoRR Michael J. Klaiber, Sebastian Vogel, Axel Acosta, Robert Korn, Leonardo Ecco, Kristine Back, Andre Guntoro, Ingo Feldner
2019	J	`jnl`	Comparative Study and Proof of Single-Pass Connected Components Algorithms. J. Math. Imaging Vis. Michael J. Klaiber, Donald G. Bailey, Sven Simon
2019	J	`jnl`	Zig-Zag Based Single-Pass Connected Components Analysis. J. Imaging Donald G. Bailey, Michael J. Klaiber
2018	—	`conf`	A Scalable Multi- TeraOPS Deep Learning Processor Core for AI Trainina and Inference. VLSI Circuits Bruce M. Fleischer, Sunil Shukla, Matthew M. Ziegler, Joel Silberman, Jinwook Oh, Vijayalakshmi Srinivasan, Jungwook Choi, Silvia M. Mueller, Ankur Agrawal, Tina Babinsky, Nianzheng Cao, Chia-Yu Chen, Pierce Chuang, Thomas W. Fox, George Gristede, Michael Guillorn, Howard Haynie, Michael J. Klaiber, Dongsoo Lee, Shih-Hsien Lo, Gary W. Maier, Michael Scheuermann, Swagath Venkataramani, Christos Vezyrtzis, Naigang Wang, Fanchieh Yee, Ching Zhou, Pong-Fei Lu, Brian W. Curran, Leland Chang, Kailash Gopalakrishnan
2018	A	`conf`	Across the Stack Opportunities for Deep Learning Acceleration. ISLPED Vijayalakshmi Srinivasan, Bruce M. Fleischer, Sunil Shukla, Matthew M. Ziegler, Joel Silberman, Jinwook Oh, Jungwook Choi, Silvia M. Mueller, Ankur Agrawal, Tina Babinsky, Nianzheng Cao, Chia-Yu Chen, Pierce Chuang, Thomas W. Fox, George Gristede, Michael Guillorn, Howard Haynie, Michael J. Klaiber, Dongsoo Lee, Shih-Hsien Lo, Gary W. Maier, Michael Scheuermann, Swagath Venkataramani, Christos Vezyrtzis, Naigang Wang, Fanchieh Yee, Ching Zhou, Pong-Fei Lu, Brian W. Curran, Leland Chang, Kailash Gopalakrishnan
2016	J	`jnl`	A Resource-Efficient Hardware Architecture for Connected Component Analysis. IEEE Trans. Circuits Syst. Video Technol. Michael J. Klaiber, Donald G. Bailey, Yousef O. Baroud, Sven Simon
2016	—	`—`	A parallel and resource-efficient single lookup connected components analysis architecture for reconfigurable hardware. Michael J. Klaiber
2014	B	`conf`	Adaptive Dynamic On-chip Memory Management for FPGA-based reconfigurable architectures. FPL Ghada Dessouky, Michael J. Klaiber, Donald G. Bailey, Sven Simon
2013	—	`conf`	A high-throughput FPGA architecture for parallel connected components analysis based on label reuse. FPT Michael J. Klaiber, Donald G. Bailey, Silvia Ahmed, Yousef Baroud, Sven Simon
2013	Misc	`conf`	Efficient hardware calculation of running statistics. IVCNZ Donald G. Bailey, Michael J. Klaiber
2013	—	`conf`	Stream Processing of Scientific Big Data on Heterogeneous Platforms - Image Analytics on Big Data in Motion. CSE Seyyed Mahdi Najmabadi, Michael J. Klaiber, Zhe Wang, Yousef Baroud, Sven Simon
2012	—	`conf`	A memory-efficient parallel single pass architecture for connected component labeling of streamed images. FPT Michael J. Klaiber, Lars Rockstroh, Zhe Wang, Yousef Baroud, Sven Simon
2012	Misc	`conf`	Correlation and convolution of image data using fermat number transform based on two's complement. ICASSP Lars Rockstroh, Michael J. Klaiber, Sven Simon
2012	—	`conf`	Fast lossless image compression with 2D Golomb parameter adaptation based on JPEG-LS. EUSIPCO Zhe Wang, Michael J. Klaiber, Yurij Gera, Sven Simon, Thomas Richter
2012	Misc	`conf`	Relaxation of particle image velocimetry based on single autocorrelation of filtered motion blurring. ICASSP T. Lefeure, Lars Rockstroh, Michael J. Klaiber, N. Fortier, Sven Simon
2012	B	`conf`	SSPQ - spatial domain perceptual image codec based on subsampling and perceptual quantization. ICIP Zhe Wang, Sven Simon, Michael J. Klaiber, Silvia Ahmed, Thomas Richter