Michael H. Perrott

35 papers A* 2C 3Journal 21Unranked 8

Year	Rank	Type	Title / Venue / Authors
2014	J	`jnl`	A 0.5 V < 4 µW CMOS Light-to-Digital Converter Based on a Nonuniform Quantizer for a Photoplethysmographic Heart-Rate Sensor. IEEE J. Solid State Circuits Mohammad Alhawari, Nadya Albelooshi, Michael H. Perrott
2014	C	`conf`	A clockless, multi-stable, CMOS analog circuit. ISCAS Mohammad Alhawari, Michael H. Perrott
2013	—	`conf`	A 0.5V <4µW CMOS photoplethysmographic heart-rate sensor IC based on a non-uniform quantizer. ISSCC Mohammad Alhawari, Nadya Albelooshi, Michael H. Perrott
2013	J	`jnl`	A Temperature-to-Digital Converter for a MEMS-Based Programmable Oscillator With < ±0.5-ppm Frequency Stability and < 1-ps Integrated Jitter. IEEE J. Solid State Circuits Michael H. Perrott, James C. Salvia, Fred S. Lee, Aaron Partridge, Shouvik Mukherjee, Carl Arft, Jin-Tae Kim, Niveditha Arumugam, Pavan Gupta, Sassan Tabatabaei, Sudhakar Pamarti, Haechang Lee, Fari Assaderaghi
2013	—	`conf`	Session 15 overview: Data converter techniques. ISSCC Michael H. Perrott, Geert Van der Plas
2012	—	`conf`	A temperature-to-digital converter for a MEMS-based programmable oscillator with better than ±0.5ppm frequency stability. ISSCC Michael H. Perrott, Jim Salvia, Fred S. Lee, Aaron Partridge, Shouvik Mukherjee, Carl Arft, Jin-Tae Kim, Niveditha Arumugam, Pavan Gupta, Sassan Tabatabaei, Sudhakar Pamarti, Haechang Lee, Fari Assaderaghi
2011	J	`jnl`	An Amplitude Resolution Improvement of an RF-DAC Employing Pulsewidth Modulation. IEEE Trans. Circuits Syst. I Regul. Pap. Min C. Park, Michael H. Perrott, Robert Bogdan Staszewski
2010	J	`jnl`	A Low Area, Switched-Resistor Based Fractional-N Synthesizer Applied to a MEMS-Based Programmable Oscillator. IEEE J. Solid State Circuits Michael H. Perrott, Sudhakar Pamarti, Eric G. Hoffman, Fred S. Lee, Shouvik Mukherjee, Cathy Lee, Vadim Tsinker, Sathi Perumal, Benjamin Soto, Niveditha Arumugam, Bruno W. Garlepp
2010	J	`jnl`	A Time-Domain Resolution Improvement of an RF-DAC. IEEE Trans. Circuits Syst. II Express Briefs Min C. Park, Michael H. Perrott, Robert Bogdan Staszewski
2010	—	`conf`	A low-area switched-resistor loop-filter technique for fractional-N synthesizers applied to a MEMS-based programmable oscillator. ISSCC Michael H. Perrott, Sudhakar Pamarti, Eric G. Hoffman, Fred S. Lee, Shouvik Mukherjee, Cathy Lee, Vadim Tsinker, Sathi Perumal, Benjamin Soto, Niveditha Arumugam, Bruno W. Garlepp
2009	—	`conf`	A 0.13µm CMOS 78dB SNDR 87mW 20MHz BW CT ΔΣ ADC with VCO-based integrator and quantizer. ISSCC Min C. Park, Michael H. Perrott
2009	J	`jnl`	A 78 dB SNDR 87 mW 20 MHz Bandwidth Continuous-Time ΔΣ ADC With VCO-Based Integrator and Quantizer Implemented in 0.13 µm CMOS. IEEE J. Solid State Circuits Matthew Park, Michael H. Perrott
2009	J	`jnl`	A Low Jitter Programmable Clock Multiplier Based on a Pulse Injection-Locked Oscillator With a Highly-Digital Tuning Loop. IEEE J. Solid State Circuits Belal Helal, Chun-Ming Hsu, Kerwin Johnson, Michael H. Perrott
2009	J	`jnl`	A Multi-Path Gated Ring Oscillator TDC With First-Order Noise Shaping. IEEE J. Solid State Circuits Matthew Z. Straayer, Michael H. Perrott
2009	C	`conf`	A Single-slope 80MS/s ADC using Two-Step Time-to-Digital Conversion. ISCAS Min C. Park, Michael H. Perrott
2009	C	`conf`	A VCO-based Analog-to-digital Converter with Second-order Sigma-Delta Noise Shaping. ISCAS Min C. Park, Michael H. Perrott
2008	J	`jnl`	A 12-Bit, 10-MHz Bandwidth, Continuous-Time ΣΔ ADC With a 5-Bit, 950-MS/s VCO-Based Quantizer. IEEE J. Solid State Circuits Matthew Z. Straayer, Michael H. Perrott
2008	J	`jnl`	A Highly Digital MDLL-Based Clock Multiplier That Leverages a Self-Scrambling Time-to-Digital Converter to Achieve Subpicosecond Jitter Performance. IEEE J. Solid State Circuits Belal Helal, Matthew Z. Straayer, Gu-Yeon Wei, Michael H. Perrott
2008	J	`jnl`	A Low-Noise Wide-BW 3.6-GHz Digital ΔΣ Fractional-N Frequency Synthesizer With a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation. IEEE J. Solid State Circuits Chun-Ming Hsu, Matthew Z. Straayer, Michael H. Perrott
2008	—	`conf`	A Low-Noise, Wide-BW 3.6GHz Digital ΔΣ Fractional-N Frequency Synthesizer with a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation. ISSCC Chun-Ming Hsu, Matthew Z. Straayer, Michael H. Perrott
2006	J	`jnl`	A 1-MHZ bandwidth 3.6-GHz 0.18-μm CMOS fractional-N synthesizer utilizing a hybrid PFD/DAC structure for reduced broadband phase noise. IEEE J. Solid State Circuits Scott E. Meninger, Michael H. Perrott
2006	J	`jnl`	A 2.5-Gb/s Multi-Rate 0.25-$\mu$m CMOS Clock and Data Recovery Circuit Utilizing a Hybrid Analog/Digital Loop Filter and All-Digital Referenceless Frequency Acquisition. IEEE J. Solid State Circuits Michael H. Perrott, Yunteng Huang, Rex T. Baird, Bruno W. Garlepp, Douglas Pastorello, Eric T. King, Qicheng Yu, Dan B. Kasha, Philip Steiner, Ligang Zhang, Jerrell P. Hein, Bruce Del Signore
2006	—	`conf`	A 2.5Gb/s Multi-Rate 0.25µm CMOS CDR Utilizing a Hybrid Analog/Digital Loop Filter. ISSCC Michael H. Perrott, Yunteng Huang, Rex T. Baird, Bruno W. Garlepp, Ligang Zhang, Jerrell P. Hein
2006	J	`jnl`	A 3.125 Gb/s limit amplifier in CMOS with 42 dB gain and 1 μs offset compensation. IEEE J. Solid State Circuits Ethan Crain, Michael H. Perrott
2004	—	`conf`	A numerical design approach for high speed, differential, resistor-loaded, CMOS amplifiers. ISCAS (5) Ethan Crain, Michael H. Perrott
2003	J	`jnl`	A fractional- N frequency synthesizer architecture utilizing a mismatch compensated PFD/DAC structure for reduced quantization-induced phase noise. IEEE Trans. Circuits Syst. II Express Briefs Scott E. Meninger, Michael H. Perrott
2003	A*	`conf`	Fractional-N frequency synthesizer design at the transfer function level using a direct closed loop realization algorithm. DAC Charlotte Y. Lau, Michael H. Perrott
2003	J	`jnl`	Guest editorial. IEEE Trans. Circuits Syst. II Express Briefs Michael H. Perrott, Gu-Yeon Wei
2002	J	`jnl`	A modeling approach for ΣΔ fractional-N frequency synthesizers allowing straightforward noise analysis. IEEE J. Solid State Circuits Michael H. Perrott, Mitchell D. Trott, Charles G. Sodini
2002	J	`jnl`	Behavioral Simulation of Fractional-N Frequency Synthesizers and Other PLL Circuits. IEEE Des. Test Comput. Michael H. Perrott
2002	A*	`conf`	Fast and accurate behavioral simulation of fractional-N frequency synthesizers and other PLL/DLL circuits. DAC Michael H. Perrott
1997	J	`jnl`	A 27-mW CMOS fractional-N synthesizer using digital compensation for 2.5-Mb/s GFSK modulation. IEEE J. Solid State Circuits Michael H. Perrott, Theodore L. Tewksbury III, Charles G. Sodini
1997	—	`—`	Techniques for high data rate modulation and low power operation of fractional-N frequency synthesizers. Michael H. Perrott
1996	J	`jnl`	An efficient approach to ARMA modeling of biological systems with multiple inputs and delays. IEEE Trans. Biomed. Eng. Michael H. Perrott, Richard J. Cohen
1993	J	`jnl`	A time domain approach for the fluctuation analysis of heart rate related to instantaneous lung volume. IEEE Trans. Biomed. Eng. Kazuo Yana, J. Philip Saul, Ronald D. Berger, Michael H. Perrott, Richard J. Cohen