| Year | Rank | Type | Title / Venue / Authors |
|---|---|---|---|
| 2021 | J | jnl |
IEEE Trans. Sustain. Comput.
|
| 2016 | C | conf |
IOLTS
|
| 2014 | J | jnl |
Microprocess. Microsystems
|
| 2013 | J | jnl |
Microelectron. J.
|
| 2013 | J | jnl |
Exact closed-form expressions for substrate resistance and capacitance extraction in nanoscale VLSI.
Microelectron. J.
|
| 2013 | C | conf |
IOLTS
|
| 2011 | J | jnl |
IEEE Trans. Instrum. Meas.
|
| 2011 | C | conf |
DDECS
|
| 2011 | J | jnl |
Simul. Model. Pract. Theory
|
| 2011 | C | conf |
ISCAS
|
| 2011 | C | conf |
VLSI-SoC
|
| 2011 | J | jnl |
IEEE Trans. Instrum. Meas.
|
| 2010 | — | conf |
ICECS
|
| 2010 | J | jnl |
IEEE Trans. Instrum. Meas.
|
| 2010 | — | conf |
ICECS
|
| 2010 | — | conf |
ISVLSI
|
| 2010 | C | conf |
ISCAS
|
| 2010 | C | conf |
IOLTS
|
| 2008 | — | conf |
ICECS
|
| 2008 | C | conf |
DDECS
|
| 2007 | — | conf |
ECCTD
|
| 2007 | — | conf |
ICECS
|
| 2004 | A | conf |
DATE
|
| 2004 | — | — |
|
| 2003 | J | jnl |
Accelerating the compaction of test sequences in sequential circuits through problem size reduction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
|
| 2002 | — | conf |
SETN
|