Michael D. Powell

18 papers A* 13A 3Journal 2

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	Intel Xeon 6 Product Family. IEEE Micro Michael D. Powell, Patrick Fleming, Venkidesh Iyer Krishna, Naveen Lakkakula, Subhiksha Ravisundar, Praveen Mosur, Arijit Biswas, Pradeep Dubey, Kapil Sood, Andrew Cunningham, Smita Kumar
2011	A*	`conf`	Achieving uniform performance and maximizing throughput in the presence of heterogeneity. HPCA Krishna K. Rangan, Michael D. Powell, Gu-Yeon Wei, David M. Brooks
2009	A*	`conf`	Architectural core salvaging in a multi-core processor for hard-error tolerance. ISCA Michael D. Powell, Arijit Biswas, Shantanu Gupta, Shubhendu S. Mukherjee
2009	A*	`conf`	CAMP: A technique to estimate per-structure power at run-time using a few simple parameters. HPCA Michael D. Powell, Arijit Biswas, Joel S. Emer, Shubhendu S. Mukherjee, Basit Riaz Sheikh, Shrirang M. Yardi
2007	A	`conf`	Resource area dilation to reduce power density in throughput servers. ISLPED Michael D. Powell, T. N. Vijaykumar
2005	A*	`conf`	Balancing Resource Utilization to Mitigate Power Density in Processor Pipelines. MICRO Michael D. Powell, Ethan Schuchman, T. N. Vijaykumar
2005	A*	`conf`	Optimizing Replication, Communication, and Capacity Allocation in CMPs. ISCA Zeshan Chishti, Michael D. Powell, T. N. Vijaykumar
2004	A*	`conf`	Exploiting Resonant Behavior to Reduce Inductive Noise. ISCA Michael D. Powell, T. N. Vijaykumar
2004	A*	`conf`	Heat-and-run: leveraging SMT and CMP to manage power density through the operating system. ASPLOS Mohamed A. Gomaa, Michael D. Powell, T. N. Vijaykumar
2003	A*	`conf`	Distance Associativity for High-Performance Energy-Efficient Non-Uniform Cache Architectures. MICRO Zeshan Chishti, Michael D. Powell, T. N. Vijaykumar
2003	A*	`conf`	Pipeline Damping: A Microarchitectural Technique to Reduce Inductive Noise in Supply Voltage. ISCA Michael D. Powell, T. N. Vijaykumar
2003	A	`conf`	Pipeline muffling and a priori current ramping: architectural techniques to reduce high-frequency inductive noise. ISLPED Michael D. Powell, T. N. Vijaykumar
2002	A*	`conf`	Exploiting Choice in Resizable Cache Design to Optimize Deep-Submicron Processor Energy-Delay. HPCA Se-Hyun Yang, Michael D. Powell, Babak Falsafi, T. N. Vijaykumar
2002	A*	`conf`	Reducing register ports for higher speed and lower energy. MICRO Il Park, Michael D. Powell, T. N. Vijaykumar
2001	A*	`conf`	An Integrated Circuit/Architecture Approach to Reducing Leakage in Deep-Submicron High-Performance I-Caches. HPCA Se-Hyun Yang, Michael D. Powell, Babak Falsafi, Kaushik Roy, T. N. Vijaykumar
2001	J	`jnl`	Reducing leakage in a high-performance deep-submicron instruction cache. IEEE Trans. Very Large Scale Integr. Syst. Michael D. Powell, Se-Hyun Yang, Babak Falsafi, Kaushik Roy, T. N. Vijaykumar
2001	A*	`conf`	Reducing set-associative cache energy via way-prediction and selective direct-mapping. MICRO Michael D. Powell, Amit Agarwal, T. N. Vijaykumar, Babak Falsafi, Kaushik Roy
2000	A	`conf`	Gated-V ISLPED Michael D. Powell, Se-Hyun Yang, Babak Falsafi, Kaushik Roy, T. N. Vijaykumar