Michael D. Hutton

16 papers A* 2A 3B 1Journal 4Unranked 6
YearRankTypeTitle / Venue / Authors
2007 J jnl
Efficient Timing Analysis With Known False Paths Using Biclique Covering.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Michael D. Hutton, Truman Collins, Sridhar Srinivasan, Nan-Chi Chou, Peter Suaris, Chung-Kuan Cheng
2006 — conf
A methodology for FPGA to structured-ASIC synthesis and verification.
DATE Designers' Forum
Michael D. Hutton, Richard Yuan, Jay Schleicher, Gregg Baeckler, Sammy Cheung, Kar Keng Chua, Hee Kong Phoo
2006 — conf
Efficient static timing analysis using a unified framework for false paths and multi-cycle paths.
ASP-DAC
Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Chung-Kuan Cheng, Michael D. Hutton
2005 A conf
Improving the efficiency of static timing analysis with false paths.
ICCAD
Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Chung-Kuan Cheng, Michael D. Hutton, Truman Collins, Sridhar Srinivasan, Nan-Chi Chou, Peter Suaris
2004 B conf
Improving FPGA Performance and Area Using an Adaptive Logic Module.
FPL
Michael D. Hutton, Jay Schleicher, David M. Lewis, Bruce Pedersen, Richard Yuan, Sinan Kaptanoglu, Gregg Baeckler, Boris Ratchev, Ketan Padalia, Mark Bourgeault, Andy Lee, Henry Kim, Rahul Saini
2002 J jnl
Automatic generation of synthetic sequential benchmark circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Michael D. Hutton, Jonathan Rose, Derek G. Corneil
2002 A conf
Interconnect enhancements for a high-speed PLD architecture.
FPGA
Michael D. Hutton, Vinson Chan, Peter Kazarian, Victor Maruri, Tony Ngai, Jim Park, Rakesh H. Patel, Bruce Pedersen, Jay Schleicher, Sergey Y. Shumarayev
2001 — conf
Interconnect prediction for programmable logic devices.
SLIP
Michael D. Hutton
1999 — conf
Applications of clone circuits to issues in physical-design.
ISCAS (6)
Michael D. Hutton, Jonathan Rose
1999 — conf
Equivalence classes of clone circuits for physical-design benchmarking.
ISCAS (6)
Michael D. Hutton, Jonathan Rose
1998 J jnl
Characterization and parameterized generation of synthetic combinational benchmark circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Michael D. Hutton, Jonathan Rose, Jerry P. Grossman, Derek G. Corneil
1997 A conf
Generation of Synthetic Sequential Benchmark Circuits.
FPGA
Michael D. Hutton, Jonathan Rose, Derek G. Corneil
1996 A* conf
Characterization and Parameterized Random Generation of Digital Circuits.
DAC
Michael D. Hutton, Jerry P. Grossman, Jonathan Rose, Derek G. Corneil
1996 J jnl
Upward Planar Drawing of Single-Source Acyclic Digraphs.
SIAM J. Comput.
Michael D. Hutton, Anna Lubiw
1991 — conf
Upward Planar Drawing of Single Source Acyclic Digraphs.
Planar Graphs
Michael D. Hutton, Anna Lubiw
1991 A* conf
Upward Planar Drawing of Single Source Acyclic Digraphs.
SODA
Michael D. Hutton, Anna Lubiw