Mengjie Mao

28 papers A* 5A 5C 3Journal 7Unranked 8
YearRankTypeTitle / Venue / Authors
2021 J jnl
Exploring Applications of STT-RAM in GPU Architectures.
IEEE Trans. Circuits Syst. I Regul. Pap.
Xiaoxiao Liu, Mengjie Mao, Xiuyuan Bi, Hai Helen Li, Yiran Chen
2019 J jnl
Thread Batching for High-performance Energy-efficient GPU Memory Design.
CoRR
Bing Li, Mengjie Mao, Xiaoxiao Liu, Tao Liu, Zihao Liu, Wujie Wen, Yiran Chen, Hai Helen Li
2019 J jnl
Thread Batching for High-performance Energy-efficient GPU Memory Design.
ACM J. Emerg. Technol. Comput. Syst.
Bing Li, Mengjie Mao, Xiaoxiao Liu, Tao Liu, Zihao Liu, Wujie Wen, Yiran Chen, Hai (Helen) Li
2018 J jnl
TriZone: A Design of MLC STT-RAM Cache for Combined Performance, Energy, and Reliability Optimizations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Zihao Liu, Mengjie Mao, Tao Liu, Xue Wang, Wujie Wen, Yiran Chen, Hai Li, Danghui Wang, Yukui Pei, Ning Ge
2017 J jnl
An Energy-Efficient GPGPU Register File Architecture Using Racetrack Memory.
IEEE Trans. Computers
Mengjie Mao, Wujie Wen, Yaojun Zhang, Yiran Chen, Hai Li
2017 J jnl
Cross-Layer Optimization for Multilevel Cell STT-RAM Caches.
IEEE Trans. Very Large Scale Integr. Syst.
Xiuyuan Bi, Mengjie Mao, Danghui Wang, Hai Helen Li
2016 A conf
A holistic tri-region MLC STT-RAM design with combined performance, energy, and reliability optimizations.
DATE
Wujie Wen, Mengjie Mao, Hai Li, Yiran Chen, Yukui Pei, Ning Ge
2016 J jnl
Harmonica: A Framework of Heterogeneous Computing Systems With Memristor-Based Neuromorphic Computing Accelerators.
IEEE Trans. Circuits Syst. I Regul. Pap.
Xiaoxiao Liu, Mengjie Mao, Beiye Liu, Boxun Li, Yu Wang, Hao Jiang, Mark Barnell, Qing Wu, Jianhua Joshua Yang, Hai Li, Yiran Chen
2016 C conf
Heterogeneous systems with reconfigurable neuromorphic computing accelerators.
ISCAS
Sicheng Li, Xiaoxiao Liu, Mengjie Mao, Hai (Helen) Li, Yiran Chen, Boxun Li, Yu Wang
2016 A conf
Sliding Basket: An adaptive ECC scheme for runtime write failure suppression of STT-RAM cache.
DATE
Xue Wang, Mengjie Mao, Enes Eken, Wujie Wen, Hai Li, Yiran Chen
2016 A* conf
TEMP: thread batch enabled memory partitioning for GPU.
DAC
Mengjie Mao, Wujie Wen, Xiaoxiao Liu, Jingtong Hu, Danghui Wang, Yiran Chen, Hai Li
2015 — conf
An efficient STT-RAM-based register file in GPU architectures.
ASP-DAC
Xiaoxiao Liu, Mengjie Mao, Xiuyuan Bi, Hai Li, Yiran Chen
2015 A* conf
RENO: a high-efficient reconfigurable neuromorphic computing accelerator design.
DAC
Xiaoxiao Liu, Mengjie Mao, Beiye Liu, Hai Li, Yiran Chen, Boxun Li, Yu Wang, Hao Jiang, Mark Barnell, Qing Wu, Jianhua Joshua Yang
2015 C conf
The applications of memristor devices in next-generation cortical processor designs.
ISCAS
Hai Li, Beiye Liu, Xiaoxiao Liu, Mengjie Mao, Yiran Chen, Qing Wu, Qinru Qiu
2015 A* conf
VWS: a versatile warp scheduler for exploring diverse cache localities of GPGPU applications.
DAC
Mengjie Mao, Jingtong Hu, Yiran Chen, Hai Li
2014 — conf
A heterogeneous computing system with memristor-based neuromorphic accelerators.
HPEC
Xiaoxiao Liu, Mengjie Mao, Hai Li, Yiran Chen, Hao Jiang, J. Joshua Yang, Qing Wu, Mark Barnell
2014 — conf
Emerging memristor technology enabled next generation cortical processor.
SoCC
Hai Li, Miao Hu, Xiaoxiao Liu, Mengjie Mao, Chuandong Li, Shukai Duan
2014 A* conf
Exploration of GPGPU Register File Architecture Using Domain-wall-shift-write based Racetrack Memory.
DAC
Mengjie Mao, Wujie Wen, Yaojun Zhang, Yiran Chen, Hai (Helen) Li
2014 — conf
Neuromorphic hardware acceleration enabled by emerging technologies (Invited paper).
ISIC
Hai Li, Xiaoxiao Liu, Mengjie Mao, Yiran Chen, Qing Wu, Mark Barnell
2014 — conf
Prefetching techniques for STT-RAM based last-level cache in CMP systems.
ASP-DAC
Mengjie Mao, Guangyu Sun, Yong Li, Alex K. Jones, Yiran Chen
2014 A* conf
State-Restrict MLC STT-RAM Designs for High-Reliable High-Performance Memory System.
DAC
Wujie Wen, Yaojun Zhang, Mengjie Mao, Yiran Chen
2013 A conf
CD-ECC: content-dependent error correction codes for combating asymmetric nonvolatile memory operation errors.
ICCAD
Wujie Wen, Mengjie Mao, Xiaochun Zhu, Seung-Hyuk Kang, Danghui Wang, Yiran Chen
2013 — conf
Coordinating prefetching and STT-RAM based last-level cache management for multicore systems.
ACM Great Lakes Symposium on VLSI
Mengjie Mao, Hai (Helen) Li, Alex K. Jones, Yiran Chen
2013 A conf
Unleashing the potential of MLC STT-RAM caches.
ICCAD
Xiuyuan Bi, Mengjie Mao, Danghui Wang, Hai Li
2012 — conf
Distributed Control Independence for Composable Multi-processors.
ACIS-ICIS
Mengjie Mao, Hong An, Tao Sun, Qi Li, Bobin Deng, Xuechao Wei, Junrui Zhou
2012 A conf
Distributed replay protocol for distributed uniprocessors.
ICS
Mengjie Mao, Hong An, Bobin Deng, Tao Sun, Xuechao Wei, Wei Zhou, Wenting Han
2012 — conf
Value Predicted LogSPoTM: Improve the Parallesim of Thread Level System by Using a Value Predictor.
ACIS-ICIS
Bobin Deng, Hong An, Qi Li, Gongming Li, Mengjie Mao
2010 C conf
FACRA: Flexible-Core Architecture Chip Resource Abstractor.
PDCAT
Tao Sun, Hong An, Yongqing Ren, Mengjie Mao, Yang Liu, Mu Xu, Qi Li