Meng Liu

11 papers A* 1A 1Misc 1Journal 5Unranked 3
YearRankTypeTitle / Venue / Authors
2025 J jnl
Clock mesh synthesis through dynamic programming with physical parameters consideration.
Integr.
Dejian Li, Jie Gan, Chongfei Shen, Qi Chen, Lixin Yang, Sihai Qiu, Xin Jin, Tiantian Wu, Zhijie Chen, Meng Liu
2025 J jnl
PttAcc: Pipeline-Based Taylor Expansion Fitting Arctangent Angle Hardware Accelerator Design for Descriptor Duty in ORB-SLAM System.
IEEE Embed. Syst. Lett.
Meng Liu, Fei Xiao, Ruijie Wang, Peiyuan Wan, Zhijie Chen, Dejian Li, Chongfei Shen
2024 A* conf
SSRESF: Sensitivity-aware Single-particle Radiation Effects Simulation Framework in SoC Platforms based on SVM Algorithm.
DAC
Meng Liu, Shuai Li, Fei Xiao, Ruijie Wang, Chunxue Liu, Liang Wang
2023 J jnl
Vector-Based Dedicated Processor Architecture for Efficient Tracking in VSLAM Systems.
IEEE Embed. Syst. Lett.
Dejian Li, Xi Feng, Chongfei Shen, Qi Chen, Lixin Yang, Sihai Qiu, Xin Jin, Meng Liu
2022 J jnl
A co-design method of customized ISA design space exploration and fixed-point library construction for RISC-V dedicated processor.
IEICE Electron. Express
Meng Liu
2021 — conf
An Approximate Symmetry Clock Tree Design with Routing Topology Prediction.
MWSCAS
Meng Liu, Zhiye Zhang, Jiabao Wen, Yunpeng Jia
2021 Misc conf
The RISC-V instruction set architecture optimization and fixed-point math library co-design: work-in-progress.
CODES+ISSS
Meng Liu
2020 A conf
HcveAcc: A High-Performance and Energy-Efficient Accelerator for Tracking Task in VSLAM System.
DATE
Renwei Li, Junning Wu, Meng Liu, Zuding Chen, Shengang Zhou, Shanggong Feng
2017 J jnl
A novel obstacle-aware multiple fan-out symmetrical clock tree synthesis.
IEICE Electron. Express
Meng Liu, Zhiwei Zhang, Wenqin Sun, Donglin Wang
2017 — conf
Obstacle-aware symmetrical clock tree construction.
MWSCAS
Meng Liu, Zhiwei Zhang, Wenqin Sun, Donglin Wang
2017 — conf
Optimization of clock mesh based on wire sizing variation.
ISOCC
Meng Liu, Zhiwei Zhang, Wenqin Sun, Donglin Wang