Meng-Hsueh Chiang

15 papers Journal 4Unranked 11
YearRankTypeTitle / Venue / Authors
2024 — conf
Fabrication of Hybrid Fin/Planar LDMOS with Modulation Gate.
DRC
Zih-Fei Chen, Ya-Chi Huang, Yu-Shen Lai, Yi-Ting Wu, Cheng-Ming Huang, Meng-Hsueh Chiang
2023 — conf
How Fault-Tolerant Quantum Computing Benefits from Cryo-CMOS Technology.
VLSI Technology and Circuits
H.-L. Chiang, Richard A. Hadi, J.-F. Wang, Hung-Chi Han, J.-J. Wu, H.-H. Hsieh, J.-J. Horng, W.-S. Chou, B.-S. Lien, C.-H. Chang, Y.-C. Chen, Yeong-Her Wang, T.-C. Chen, J.-C. Liu, Y.-C. Liu, Meng-Hsueh Chiang, K.-H. Kao, B. Pulicherla, J. Cai, C.-S. Chang, K.-W. Su, K.-L. Cheng, T.-J. Yeh, Y.-C. Peng, Christian C. Enz, Mau-Chung Frank Chang, M.-F. Chang, H.-S. Philip Wong, Iuliana P. Radu
2023 — conf
MOSFET Characterization with Reduced Supply Voltage at Low Temperatures for Power Efficiency Maximization.
ESSDERC
W.-C. Lin, H.-P. Huang, Kuo-Hsing Kao, Meng-Hsueh Chiang, Darsen D. Lu, Wei-Chou Hsu, Yeong-Her Wang, William Cheng-Yu Ma, Hann-Huei Tsai, Y.-J. Lee, H.-L. Chiang, J.-F. Wang, Iuliana P. Radu
2023 — conf
Performance Comparison of SRAM Designs Implemented with Silicon-On-Insulator Nanosheet Transistors and Bulk FinFETs.
ESSDERC
Po-Chih Chen, Yi-Ting Wu, Meng-Hsueh Chiang
2021 — conf
Back-Bias Modulated UTBB SOI for System-on-Chip I/O Cells.
ISQED
Ming-Yu Chang, Po-Yu Chao, Meng-Hsueh Chiang
2020 J jnl
Compact Device Models for FinFET and Beyond.
CoRR
Darsen D. Lu, Mohan V. Dunga, Ali M. Niknejad, Chenming Hu, Fu-Xiang Liang, Wei-Chen Hung, Jia-Wei Lee, Chun-Hsiang Hsu, Meng-Hsueh Chiang
2019 — conf
Speed Optimization of Vertically Stacked Gate-All-Around MOSFETs with Inner Spacers for Low Power and Ultra-Low Power Applications.
ISQED
Ya-Chi Huang, Meng-Hsueh Chiang, Shui-Jinn Wang
2018 — conf
An area efficient low-voltage 6-T SRAM cell using stacked silicon nanowires.
ICICDT
Ya-Chi Huang, Meng-Hsueh Chiang, Shui-Jinn Wang, Sumeet Kumar Gupta
2018 — conf
Body-biasing assisted vmin optimization for 5nm-node multi-Vt FD-SOI 6T-SRAM.
ISQED
Jheng-Yi Chen, Ming-Yu Chang, Shi-Hao Chen, Jia-Wei Lee, Meng-Hsueh Chiang
2017 J jnl
Threshold-voltage variability analysis and modeling for junctionless double-gate transistors.
Microelectron. Reliab.
Chun-Yu Chen, Jyi-Tsong Lin, Meng-Hsueh Chiang
2016 — conf
Performance evaluation of stacked gate-all-around MOSFETs at 7 and 10 nm technology nodes.
ISQED
Meng-Yen Wu, Meng-Hsueh Chiang
2015 — conf
6-T SRAM performance assessment with stacked silicon nanowire MOSFETs.
ISQED
Ya-Chi Huang, Meng-Hsueh Chiang, Wei-Chou Hsu, Shiou-Ying Cheng
2012 J jnl
Assessment of structure variation in silicon nanowire FETs and impact on SRAM.
Microelectron. J.
Yi-Bo Liao, Meng-Hsueh Chiang, Keunwoo Kim, Wei-Chou Hsu
2012 — conf
Design issues and insights of multi-fin bulk silicon FinFETs.
ISQED
Hsun Li, Meng-Hsueh Chiang
2010 J jnl
Low power design of phase-change memory based on a comprehensive model.
IET Comput. Digit. Tech.
Meng-Hsueh Chiang, Yi-Bo Liao, Jun-Tin Lin, Wei-Chou Hsu, Chu Yu, Pei-Chia Chiang, Y.-Y. Hsu, W.-H. Liu, Shyh-Shyuan Sheu, Keng-Li Su, Ming-Jer Kao, Ming-Jinn Tsai