Meng-Chiou Wu

11 papers C 1Misc 1Journal 4Unranked 5
YearRankTypeTitle / Venue / Authors
2019 J jnl
NFV deployment strategies in SDN network.
Int. J. High Perform. Comput. Netw.
Chia-Wei Tseng, Po-Hao Lai, Bo-Sheng Huang, Li-Der Chou, Meng-Chiou Wu
2008 J jnl
Chip placement in a reticle for multiple-project wafer fabrication.
ACM Trans. Design Autom. Electr. Syst.
Meng-Chiou Wu, Rung-Bin Lin, Shih-Cheng Tsai
2008 J jnl
Finding Dicing Plans for Multiple Project wafers fabricated with Shuttle Mask.
J. Circuits Syst. Comput.
Meng-Chiou Wu, Rung-Bin Lin
2007 J jnl
Reticle Design for Minimizing Multiproject Wafer Production Cost.
IEEE Trans Autom. Sci. Eng.
Rung-Bin Lin, Meng-Chiou Wu, Shih-Cheng Tsai
2007 C conf
Reticle Exposure Plans for Multi-Project Wafers.
DDECS
Rung-Bin Lin, Da-Wei Hsu, Ming-Hsine Kuo, Meng-Chiou Wu
2006 — conf
Design space exploration for minimizing multi-project wafer production cost.
ASP-DAC
Rung-Bin Lin, Meng-Chiou Wu, Wei-Chiu Tseng, Ming-Hsine Kuo, Tsai-Ying Lin, Shr-Cheng Tsai
2005 — conf
A Comparative Study on Dicing of Multiple Project Wafers.
ISVLSI
Meng-Chiou Wu, Rung-Bin Lin
2005 — conf
Multiple project wafers for medium-volume IC production.
ISCAS (5)
Meng-Chiou Wu, Rung-Bin Lin
2005 — conf
Reticle Floorplanning and Wafer Dicing for Multiple Project Wafers.
ISQED
Meng-Chiou Wu, Rung-Bin Lin
2005 — conf
Reticle floorplanning of flexible chips for multi-project wafers.
ACM Great Lakes Symposium on VLSI
Meng-Chiou Wu, Rung-Bin Lin
1998 Misc conf
A New Statistical Approach to Timing Analysis of VLSI Circuits.
VLSI Design
Rung-Bin Lin, Meng-Chiou Wu