Melvin A. Breuer

190 papers A* 23A 36C 4Misc 17Journal 72Unranked 37

Year	Rank	Type	Title / Venue / Authors
2016	J	`jnl`	Testable MUTEX Design. IEEE Trans. Circuits Syst. I Regul. Pap. Yang Zhang, Leandro S. Heck, Matheus T. Moreira, David Zar, Melvin A. Breuer, Ney Laert Vilar Calazans, Peter A. Beerel
2015	—	`conf`	Blade - A Timing Violation Resilient Asynchronous Template. ASYNC Dylan Hand, Matheus Trevisan Moreira, Hsin-Ho Huang, Danlei Chen, Frederico Butzke, Zhichao Li, Matheus Gibiluka, Melvin A. Breuer, Ney Laert Vilar Calazans, Peter A. Beerel
2015	—	`conf`	Design and Analysis of Testable Mutual Exclusion Elements. ASYNC Yang Zhang, Leandro S. Heck, Matheus T. Moreira, David Zar, Melvin A. Breuer, Ney Laert Vilar Calazans, Peter A. Beerel
2015	—	`conf`	GlYFF: A framework for global yield and floorplan aware design optimization. ISQED Shuo Wang, Yue Gao, Melvin A. Breuer
2015	—	`conf`	Performance Optimization and Analysis of Blade Designs under Delay Variability. ASYNC Dylan Hand, Hsin-Ho Huang, Benmao Cheng, Yang Zhang, Matheus Trevisan Moreira, Melvin A. Breuer, Ney Laert Vilar Calazans, Peter A. Beerel
2013	A	`conf`	A new paradigm for trading off yield, area and performance to enhance performance per wafer. DATE Yue Gao, Melvin A. Breuer, Yanzhi Wang
2013	Misc	`conf`	Trading off area, yield and performance via hybrid redundancy in multi-core architectures. VTS Yue Gao, Yang Zhang, Da Cheng, Melvin A. Breuer
2013	A	`conf`	Using explicit output comparisons for fault tolerant scheduling (FTS) on modern high-performance processors. DATE Yue Gao, Sandeep K. Gupta, Melvin A. Breuer
2012	A	`conf`	A design flow to maximize yield/area of physical devices via redundancy. ITC Mohammad Mirza-Aghatabar, Melvin A. Breuer, Sandeep K. Gupta
2012	J	`jnl`	Efficient Overdetection Elimination of Acceptable Faults for Yield Improvement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kuen-Jong Lee, Tong-Yu Hsieh, Melvin A. Breuer
2012	J	`jnl`	Error Rate Estimation for Defective Circuits via Ones Counting. ACM Trans. Design Autom. Electr. Syst. Zhaoliang Pan, Melvin A. Breuer
2012	—	`conf`	Theory of redundancy for logic circuits to maximize yield/area. ISQED Mohammad Mirza-Aghatabar, Melvin A. Breuer, Sandeep K. Gupta, Shahin Nazarian
2011	J	`jnl`	An Error-Tolerance-Based Test Methodology to Support Product Grading for Yield Enhancement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Tong-Yu Hsieh, Kuen-Jong Lee, Melvin A. Breuer
2010	A	`conf`	Algorithms to maximize yield and enhance yield/area of pipeline circuitry by insertion of switches and redundant modules. DATE Mohammad Mirza-Aghatabar, Melvin A. Breuer, Sandeep K. Gupta
2010	—	`conf`	HYPER: A Heuristic for Yield/Area imProvEment Using Redundancy in SoC. Asian Test Symposium Mohammad Mirza-Aghatabar, Melvin A. Breuer, Sandeep K. Gupta
2010	A*	`conf`	Hardware that produces bounded rather than exact results. DAC Melvin A. Breuer
2009	—	`conf`	SIRUP: Switch Insertion in RedUndant Pipeline Structures for Yield and Yield/Area Improvement. Asian Test Symposium Mohammad Mirza-Aghatabar, Melvin A. Breuer, Sandeep K. Gupta
2009	A	`conf`	Tolerance of performance degrading faults for effective yield improvement. ITC Tong-Yu Hsieh, Melvin A. Breuer, Murali Annavaram, Sandeep K. Gupta, Kuen-Jong Lee
2008	—	`conf`	A Multi-valued Algebra for Capacitance Induced Crosstalk Delay Faults. ATS Arani Sinha, Sandeep K. Gupta, Melvin A. Breuer
2008	J	`jnl`	An Error Rate Based Test Methodology to Support Error-Tolerance. IEEE Trans. Reliab. Tong-Yu Hsieh, Kuen-Jong Lee, Melvin A. Breuer
2008	J	`jnl`	An Illustrated Methodology for Analysis of Error Tolerance. IEEE Des. Test Comput. Melvin A. Breuer, Haiyang (Henry) Zhu
2008	Misc	`conf`	Basing Acceptable Error-Tolerant Performance on Significance-Based Error-rate (SBER). VTS Zhaoliang Pan, Melvin A. Breuer
2008	J	`jnl`	Clarifying the record on testability cost functions. IEEE Des. Test Comput. Melvin A. Breuer
2007	J	`jnl`	Estimating Error Rate in Defective Logic Using Signature Analysis. IEEE Trans. Computers Zhaoliang Pan, Melvin A. Breuer
2007	—	`conf`	Improving Timing-Independent Testing of Crosstalk Using Realistic Assumptions on Delay Faults. ATS Shahdad Irajpour, Sandeep K. Gupta, Melvin A. Breuer
2007	A	`conf`	Reduction of detected acceptable faults for yield improvement via error-tolerance. DATE Tong-Yu Hsieh, Kuen-Jong Lee, Melvin A. Breuer
2006	Misc	`conf`	An Error-Oriented Test Methodology to Improve Yield with Error-Tolerance. VTS Tong-Yu Hsieh, Kuen-Jong Lee, Melvin A. Breuer
2006	—	`conf`	Diagnosis of delay faults due to resistive bridges, delay variations and defects. ATS Lei Wang, Sandeep K. Gupta, Melvin A. Breuer
2006	—	`conf`	Error-Tolerance and Multi-Media. IIH-MSP Melvin A. Breuer, Haiyang (Henry) Zhu
2006	—	`conf`	STAX: statistical crosstalk target set compaction. DATE Designers' Forum Shahin Nazarian, Massoud Pedram, Sandeep K. Gupta, Melvin A. Breuer
2006	—	`conf`	Test Generation for Weak Resistive Bridges. ATS Shahdad Irajpour, Sandeep K. Gupta, Melvin A. Breuer
2005	A	`conf`	A novel test methodology based on error-rate to support error-tolerance. ITC Kuen-Jong Lee, Tong-Yu Hsieh, Melvin A. Breuer
2005	—	`conf`	Let's Think Analog. ISVLSI Melvin A. Breuer
2005	C	`conf`	Multi-media Applications and Imprecise Computation. DSD Melvin A. Breuer
2005	A	`conf`	Multiple tests for each gate delay fault: higher coverage and lower test application cost. ITC Shahdad Irajpour, Sandeep K. Gupta, Melvin A. Breuer
2004	J	`jnl`	Defect and Error Tolerance in the Presence of Massive Numbers of Defects. IEEE Des. Test Comput. Melvin A. Breuer, Sandeep K. Gupta, T. M. Mak
2004	—	`conf`	Determining error rate in error tolerant VLSI chips. DELTA Melvin A. Breuer
2004	—	`conf`	Efficient Identification of Crosstalk Induced Slowdown Targets. Asian Test Symposium Melvin A. Breuer, Sandeep K. Gupta, Shahin Nazarian
2004	—	`conf`	Intelligible Test Techniques to Support Error-Tolerance. Asian Test Symposium Melvin A. Breuer
2004	—	`conf`	Modeling and Simulation for Crosstalk Aggravated by Weak-Bridge Defects between On-Chip Interconnects. Asian Test Symposium Lei Wang, Sandeep K. Gupta, Melvin A. Breuer
2004	A	`conf`	Timing-Independent Testing of Crosstalk in the Presence of Delay Producing Defects Using Surrogate Fault Models. ITC Shahdad Irajpour, Sandeep K. Gupta, Melvin A. Breuer
2003	—	`conf`	An Enhanced Test Generator for Capacitance Induced Crosstalk Delay Faults. Asian Test Symposium Arani Sinha, Sandeep K. Gupta, Melvin A. Breuer
2003	Misc	`conf`	Analyzing Crosstalk in the Presence of Weak Bridge Defects. VTS Shahdad Irajpour, Shahin Nazarian, Lei Wang, Sandeep K. Gupta, Melvin A. Breuer
2003	Misc	`conf`	Test Generation for Maximizing Ground Bounce Considering Circuit Delay. VTS Yi-Shing Chang, Sandeep K. Gupta, Melvin A. Breuer
2002	C	`conf`	Accurate and Efficient Static Timing Analysis with Crosstalk. ICCD I-De Huang, Sandeep K. Gupta, Melvin A. Breuer
2002	J	`jnl`	Analytical models for crosstalk excitation and propagation in VLSI circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Wei-Yu Chen, Sandeep K. Gupta, Melvin A. Breuer
2002	J	`jnl`	TA-PSV - Timing Analysis for Partially Specified Vectors. J. Electron. Test. Liang-Chi Chen, Sandeep K. Gupta, Melvin A. Breuer
2002	J	`jnl`	Test Generation for Crosstalk-Induced Faults: Framework and Computational Results. J. Electron. Test. Wei-Yu Chen, Sandeep K. Gupta, Melvin A. Breuer
2002	A	`conf`	XIDEN: Crosstalk Target Identification Framework. ITC Shahin Nazarian, Hang Huang, Suriyaprakash Natarajan, Sandeep K. Gupta, Melvin A. Breuer
2001	A*	`conf`	A New Gate Delay Model for Simultaneous Switching and Its Applications. DAC Liang-Chi Chen, Sandeep K. Gupta, Melvin A. Breuer
2001	A	`conf`	Crosstalk test generation on pseudo industrial circuits: a case study. ITC Liang-Chi Chen, T. M. Mak, Sandeep K. Gupta, Melvin A. Breuer
2001	J	`jnl`	Introducing redundant computations in RTL data paths for reducing BIST resources. ACM Trans. Design Autom. Electr. Syst. Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer
2001	A	`conf`	Switch-level delay test of domino logic circuits. ITC Suriyaprakash Natarajan, Sandeep K. Gupta, Melvin A. Breuer
2001	Misc	`conf`	Test Generation for Maximizing Ground Bounce for Internal Circuitry with Reconvergent Fan-out. VTS Yi-Shing Chang, Sandeep K. Gupta, Melvin A. Breuer
2000	—	`conf`	A new framework for static timing analysis, incremental timing refinement, and timing simulation. Asian Test Symposium Liang-Chi Chen, Sandeep K. Gupta, Melvin A. Breuer
2000	—	`conf`	Challenges for the Academic Test Community. Asian Test Symposium Melvin A. Breuer, Kwang-Ting Cheng
2000	J	`jnl`	Fundamental CAD algorithms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Melvin A. Breuer, Majid Sarrafzadeh, Fabio Somenzi
2000	Misc	`conf`	High End and Low End Applications for Defective Chips: Enhanced Availability and Acceptability. VTS Melvin A. Breuer
2000	Misc	`conf`	New Validation and Test Problems for High Performance Deep Submicron VLSI Circuits. VLSI Design Melvin A. Breuer, Sandeep K. Gupta
2000	J	`jnl`	Novel Test Pattern Generators for Pseudoexhaustive Testing. IEEE Trans. Computers Rajagopalan Srinivasan, Sandeep K. Gupta, Melvin A. Breuer
2000	—	`conf`	Test generation for crosstalk-induced faults: framework and computational result. Asian Test Symposium Wei-Yu Chen, Sandeep K. Gupta, Melvin A. Breuer
1999	A	`conf`	Switch-level delay test. ITC Suriyaprakash Natarajan, Sandeep K. Gupta, Melvin A. Breuer
1999	Misc	`conf`	Test Generation for Ground Bounce in Internal Logic Circuitry. VTS Yi-Shing Chang, Sandeep K. Gupta, Melvin A. Breuer
1999	A	`conf`	Test generation for crosstalk-induced delay in integrated circuits. ITC Wei-Yu Chen, Sandeep K. Gupta, Melvin A. Breuer
1999	A	`conf`	Validation and test generation for oscillatory noise in VLSI interconnects. ICCAD Arani Sinha, Sandeep K. Gupta, Melvin A. Breuer
1998	J	`jnl`	Allocation Techniques for Reducing BIST Area Overhead of Data Paths. J. Electron. Test. Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer
1998	J	`jnl`	An IEEE 1149.1 Compliant Test Control Architecture. J. Electron. Test. Debaditya Mukherjee, Melvin A. Breuer
1998	J	`jnl`	Bounds on pseudoexhaustive test lengths. IEEE Trans. Very Large Scale Integr. Syst. Rajagopalan Srinivasan, Sandeep K. Gupta, Melvin A. Breuer
1998	J	`jnl`	Estimation of BIST Resources During High-Level Synthesis. J. Electron. Test. Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer
1998	A*	`conf`	Introducing Redundant Computations in a Behavior for Reducing BIST Resources. DAC Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer
1998	—	`conf`	Process Variations and their Impact on Circuit Operation. DFT Suriyaprakash Natarajan, Melvin A. Breuer, Sandeep K. Gupta
1998	A	`conf`	Scheduling and Module Assignment for Reducing Bist Resources. DATE Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer
1998	A	`conf`	Test generation in VLSI circuits for crosstalk noise. ITC Weiyu Chen, Sandeep K. Gupta, Melvin A. Breuer
1997	Misc	`conf`	Analysis of Ground Bounce in Deep Sub-Micron Circuits. VTS Yi-Shing Chang, Sandeep K. Gupta, Melvin A. Breuer
1997	A	`conf`	Analytic Models for Crosstalk Delay and Pulse Analysis Under Non-Ideal Inputs. ITC Weiyu Chen, Melvin A. Breuer, Sandeep K. Gupta
1997	Misc	`conf`	High Quality Robust Tests for Path Delay Faults. VTS Liang-Chi Chen, Sandeep K. Gupta, Melvin A. Breuer
1997	Misc	`conf`	Will 0.1um Digital Circuits Require Mixed-Signal Testing. VTS Melvin A. Breuer, Bozena Kaminska, John E. McDermid, V. Rayapathi, Donald L. Wheater
1996	A*	`conf`	Lower Bounds on Test Resources for Scheduled Data Flow Graphs. DAC Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer
1996	A	`conf`	Process-Aggravated Noise (PAN): New Validation and Test Problems. ITC Melvin A. Breuer, Sandeep K. Gupta
1995	J	`jnl`	An integrated system for assigning signal flow directions to CMOS transistors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kuen-Jong Lee, Chih-Nan Wang, Rajiv Gupta, Melvin A. Breuer
1995	Misc	`conf`	Asynchronous multiple scan chain. VTS Sridhar Narayanan, Melvin A. Breuer
1995	A*	`conf`	Data Path Allocation for Synthesizing RTL Designs with Low BIST Area Overhead. DAC Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer
1995	J	`jnl`	Partial scan design of register-transfer level circuits. J. Electron. Test. Rajesh Gupta, Melvin A. Breuer
1995	J	`jnl`	Reconfiguration techniques for a single scan chain. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sridhar Narayanan, Melvin A. Breuer
1995	J	`jnl`	Test embedding with discrete logarithms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Mody Lempel, Sandeep K. Gupta, Melvin A. Breuer
1994	—	`conf`	A Low Cost BIST Methodology and Associated Novel Test Pattern Generator. EDAC-ETC-EUROASIC Sen-Pin Lin, Sandeep K. Gupta, Melvin A. Breuer
1994	A	`conf`	Control Strategies for Chip-Based DFT/BIST Hardware. ITC Debaditya Mukherjee, Massoud Pedram, Melvin A. Breuer
1994	A*	`conf`	Extraction of a High-level structural Representation from Circuit Descriptions with Applications to DFT/BIST. DAC Ishwar Parulkar, Melvin A. Breuer, Charles Njinda
1994	J	`jnl`	SWiTEST: a switch level test generation system for CMOS combinational circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kuen-Jong Lee, Charles Njinda, Melvin A. Breuer
1994	Misc	`conf`	Test embedding with discrete logarithms. VTS Mody Lempel, Sandeep K. Gupta, Melvin A. Breuer
1993	A*	`conf`	An Efficient Partitioning Strategy for Pseudo-Exhaustive Testing. DAC Rajagopalan Srinivasan, Sandeep K. Gupta, Melvin A. Breuer
1993	J	`jnl`	Generating a family of testable designs using the BILBO methodology. J. Electron. Test. Sen-Pin Lin, Charles Njinda, Melvin A. Breuer
1993	A	`conf`	Merging multiple FSM controllers for DFT/BIST hardware. ICCAD Debaditya Mukherjee, Massoud Pedram, Melvin A. Breuer
1993	A	`conf`	Novel Test Pattern Generators for Pseudo-Exhaustive Testing. ITC Rajagopalan Srinivasan, Sandeep K. Gupta, Melvin A. Breuer
1993	J	`jnl`	Optimal Configuring of Multiple Scan Chains. IEEE Trans. Computers Sridhar Narayanan, Rajesh Gupta, Melvin A. Breuer
1993	A	`conf`	Reconfigurable scan chains: a novel approach to reduce test application time. ICCAD Sridhar Narayanan, Melvin A. Breuer
1993	J	`jnl`	Test program synthesis for modules and chips having boundary scan. J. Electron. Test. Jung-Cheun Lien, Melvin A. Breuer
1992	A	`conf`	Configuring multiple scan chains for minimum test time. ICCAD Sridhar Narayanan, Rajesh Gupta, Melvin A. Breuer
1992	J	`jnl`	Design and test rules for CMOS circuits to facilitate IDDQ testing of bridging faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kuen-Jong Lee, Melvin A. Breuer
1992	—	`conf`	Minimal area merger of finite state machine controllers. EURO-DAC Debaditya Mukherjee, Massoud Pedram, Melvin A. Breuer
1992	A	`conf`	Optimal Sequencing of Scan Registers. ITC Sridhar Narayanan, Charles Njinda, Melvin A. Breuer
1992	—	`conf`	SIESTA: a multi-facet scan design system. EURO-DAC Sridhar Narayanan, Charles Njinda, Rajesh Gupta, Melvin A. Breuer
1992	A*	`conf`	SWiTEST: A Switch Level Test Generation System for CMOS Combinational Circuits. DAC Kuen-Jong Lee, Charles Njinda, Melvin A. Breuer
1992	Misc	`conf`	Testability properties of acyclic structures and applications to partial scan design. VTS Rajesh Gupta, Melvin A. Breuer
1991	A	`conf`	A Systematic Approach for Designing Testable VLSI Circuits. ICCAD Sen-Pin Lin, Charles Njinda, Melvin A. Breuer
1991	Misc	`conf`	A partitioning method for achieving maximal test concurrency in pseudo-exhaustive testing. VTS Rajagopalan Srinivasan, Charles Njinda, Melvin A. Breuer
1991	J	`jnl`	An optimal scheduling algorithm for testing interconnect using boundary scan. J. Electron. Test. Jung-Cheun Lien, Melvin A. Breuer
1991	Misc	`conf`	Constraints for using IDDQ testing to detect CMOS bridging faults. VTS Kuen-Jong Lee, Melvin A. Breuer
1991	A	`conf`	Maximal Diagnosis for Wiring Networks. ITC Jung-Cheun Lien, Melvin A. Breuer
1991	A	`conf`	Ordering Storage Elements in a Single Scan Chain. ICCAD Rajesh Gupta, Melvin A. Breuer
1991	J	`jnl`	Reorganizing Circuits to Aid Testability. IEEE Des. Test Comput. Rajiv Gupta, Rajagopalan Srinivasan, Melvin A. Breuer
1991	A	`conf`	Synthesis of Optimal 1-Hot Coded On-Chip Controllers for BIST Hardware. ICCAD Debaditya Mukherjee, Charles Njinda, Melvin A. Breuer
1991	J	`jnl`	The probability of error detection in sequential circuits using random test vectors. J. Electron. Test. Asad A. Ismaeel, Melvin A. Breuer
1990	A	`conf`	A New Method for Assigning Signal Flow Directions to MOS Transistors. ICCAD Kuen-Jong Lee, Rajiv Gupta, Melvin A. Breuer
1990	—	`conf`	An Extensible User Interface for an Object-Oriented VLSI CAD Framework. ICSI Rajiv Gupta, Melvin A. Breuer
1990	—	`book`	Digital systems testing and testable design. Miron Abramovici, Melvin A. Breuer, Arthur D. Friedman
1990	J	`jnl`	Fault Tolerance in Linear Systolic Arrays Using Time Redundancy. IEEE Trans. Computers Amitava Majumdar, Cauligi S. Raghavendra, Melvin A. Breuer
1990	A	`conf`	Obstacles and an approach towards concurrent engineering. ITC Melvin A. Breuer
1990	A	`conf`	On the charge sharing problem in CMOS stuck-open fault testing. ITC Kuen-Jong Lee, Melvin A. Breuer
1990	J	`jnl`	The BALLAST Methodology for Structured Partial Scan Design. IEEE Trans. Computers Rajesh Gupta, Rajiv Gupta, Melvin A. Breuer
1989	J	`jnl`	An Object-Oriented VLSI CAD Framework: A Case Study in Rapid Prototyping. Computer Rajiv Gupta, Wesley H. Cheng, Rajesh Gupta, Ido Hardonag, Melvin A. Breuer
1989	—	`conf`	BALLAST: a methodology for partial scan design. FTCS Rajesh Gupta, Rajiv Gupta, Melvin A. Breuer
1989	J	`jnl`	Optimal routing of two rectangular blocks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Mandalagiri S. Chandrasekhar, Melvin A. Breuer
1988	A	`conf`	A Test and Maintenance Controller for a Module Containing Testable Chips. ITC Melvin A. Breuer, Jung-Cheun Lien
1988	J	`jnl`	A knowledge-based system for selecting test methodologies. IEEE Des. Test Xi-an Zhu, Melvin A. Breuer
1988	J	`jnl`	Analysis of testable PLA designs. IEEE Des. Test Xi-an Zhu, Melvin A. Breuer
1988	A	`conf`	Cbase 1.0: a CAD database for VLSI circuits using object oriented technology. ICCAD Melvin A. Breuer, Wesley H. Cheng, Rajiv Gupta, Ido Hardonag, Ellis Horowitz, S. Y. Lin
1988	A	`conf`	Concurrent Control of Multiple BIT Structures. ITC Sandeep K. Gupta, Melvin A. Breuer, Jung-Cheun Lien
1988	J	`jnl`	Detectability of CMOS stuck-open faults using random and pseudorandom test sequences. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sarma Sastry, Melvin A. Breuer
1988	C	`conf`	Fault tolerance and testing aspects of an architecture for a generalized sidelobe cancellor. ICCD Melvin A. Breuer, Amitava Majumdar, Cauligi S. Raghavendra
1988	J	`jnl`	Optimum design of IC power/ground nets subject to reliability constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Salim U. Chowdhury, Melvin A. Breuer
1988	C	`conf`	The POTATO chip architecture: a study in tradeoffs for signal processing chip design. ICCD B. Sharma, Rajiv Jain, Melvin A. Breuer, Alice C. Parker, Cauligi S. Raghavendra, C. Y. Tseng
1987	J	`jnl`	Built-in test for folded programmable logic arrays. Microprocess. Microsystems Melvin A. Breuer, F. Saheban
1986	—	`conf`	A Knowledge-Based TDM Selection System. FJCC Xi-an Zhu, Melvin A. Breuer
1986	J	`jnl`	An O(n) algorithm for width determination of power/ground routes for VLSI circuits. Integr. Salim U. Chowdhury, Melvin A. Breuer
1986	J	`jnl`	Roving Emulation as a Fault Detection Mechanism. IEEE Trans. Computers Melvin A. Breuer, Asad A. Ismaeel
1986	A	`conf`	Scan Path with Look Ahead Shifting (SPLASH). ITC Magdy S. Abadir, Melvin A. Breuer
1986	J	`jnl`	Test Schedules for VLSI Circuits Having Built-In Test Hardware. IEEE Trans. Computers Magdy S. Abadir, Melvin A. Breuer
1985	J	`jnl`	A Knowledge-Based System for Designing Testable VLSI Chips. IEEE Des. Test Magdy S. Abadir, Melvin A. Breuer
1985	A*	`conf`	A knowledge based system for selecting a test methodology for a PLA. DAC Melvin A. Breuer, Xi-an Zhu
1985	J	`jnl`	Automatic Design for Testability Via Testability Measures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ting-Hua Chen, Melvin A. Breuer
1985	A*	`conf`	The construction of minimal area power and ground nets for VLSI circuits. DAC Salim U. Chowdhury, Melvin A. Breuer
1984	J	`jnl`	On Area and Yield Considerations for Fault-Tolerant VLSI Processor Arrays. IEEE Trans. Computers Israel Koren, Melvin A. Breuer
1983	J	`jnl`	A methodology for custom VLSI layout. IEEE Trans. Syst. Man Cybern. Melvin A. Breuer, Anshul Kumar
1983	A*	`conf`	A module interchange placement machine. DAC Alexander Iosupovicz, Clarence King, Melvin A. Breuer
1983	A*	`conf`	A placement algorithm for array processors. DAC Dah-Juh Chyan, Melvin A. Breuer
1983	J	`jnl`	Efficient Single-Layer Routing Along a Line of Points. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Harold W. Carter, Melvin A. Breuer
1982	A*	`conf`	A survey of the state-of-the-art of design automation an invited presentation. DAC Melvin A. Breuer
1982	J	`jnl`	Fault Diagnosis in Synchronous Sequential Circuits Based on an Effect-Cause Analysis. IEEE Trans. Computers Miron Abramovici, Melvin A. Breuer
1982	A*	`conf`	On routing for custom integrated circuits. DAC Zahir A. Syed, Abbas El Gamal, Melvin A. Breuer
1982	A*	`conf`	Optimum placement of two rectangular blocks. DAC Mandalagiri S. Chandrasekhar, Melvin A. Breuer
1981	J	`jnl`	A Survey of the State of the Art of Design Automation. Computer Melvin A. Breuer, Arthur D. Friedman, Alexander Iosupovicz
1981	A*	`conf`	Digital system simulation: Current status and future trends or darwin's theory of simulation. DAC Melvin A. Breuer, Alice C. Parker
1981	J	`jnl`	Probabilistic Aspects of Boolean Switching Functions via a New Transform. J. ACM Sarangan Krishna Kumar, Melvin A. Breuer
1980	J	`jnl`	A probabilistic model for the analysis of the routing process for circuits. Networks Prathima Agrawal, Melvin A. Breuer
1980	A*	`conf`	Fault diagnosis based on effect-cause analysis: An introduction. DAC Miron Abramovici, Melvin A. Breuer
1980	J	`jnl`	Functional Level Primitives in Test Generation. IEEE Trans. Computers Melvin A. Breuer, Arthur D. Friedman
1980	J	`jnl`	Multiple Fault Diagnosis in Combinational Circuits Based on an Effect-Cause Analysis. IEEE Trans. Computers Miron Abramovici, Melvin A. Breuer
1979	J	`jnl`	Experiments with a Density Router for PC Cards. IEEE Trans. Computers Prathima Agrawal, Melvin A. Breuer
1979	A*	`conf`	Incremental processing applied to Steinberg's placement procedure. DAC Harold W. Carter, Melvin A. Breuer, Zahir A. Syed
1979	J	`jnl`	On Redundancy and Fault Detection in Sequential Circuits. IEEE Trans. Computers Miron Abramovici, Melvin A. Breuer
1978	—	`conf`	Mathematical properties of Boolean transformations. MVL Ytzhak H. Levendel, Melvin A. Breuer
1978	—	`conf`	Vector representation of switching and three-valued functions. MVL Ytzhak H. Levendel, Melvin A. Breuer
1977	A*	`conf`	A class of min-cut placement algorithms. DAC Melvin A. Breuer
1977	A*	`conf`	Concurrent fault simulation and functional level modeling. DAC Miron Abramovici, Melvin A. Breuer, K. Kumar
1977	A*	`conf`	Some theoretical aspects of algorithmic routing. DAC Prathima Agrawal, Melvin A. Breuer
1977	—	`conf`	The design of self-checking multi-output combinational circuits. AFIPS National Computer Conference Danny C. C. Ko, Melvin A. Breuer
1976	J	`jnl`	Identification of Multiple Stuck-Type Faults in Combinational Networks. IEEE Trans. Computers Melvin A. Breuer, Shih-Jeh Chang, Stephen Y. H. Su
1974	—	`conf`	Curriculum on design automation at the University of Southern California. ACM Annual Conference (2) Melvin A. Breuer
1974	A*	`conf`	Initial design concepts for an advanced design automation system. DAC Melvin A. Breuer, Arthur D. Friedman
1974	J	`jnl`	Procedures for Eliminating Static and Dynamic Hazards in Test Generation. IEEE Trans. Computers Melvin A. Breuer, R. Loyd Harrison
1974	J	`jnl`	The Effects of Races, Delays, and Delay Faults on Test Generation. IEEE Trans. Computers Melvin A. Breuer
1973	J	`jnl`	Testing for Intermittent Faults in Digital Circuits. IEEE Trans. Computers Melvin A. Breuer
1972	J	`jnl`	A Note on Three-Valued Logic Simulation. IEEE Trans. Computers Melvin A. Breuer
1972	J	`jnl`	Generation of Fault Tests for Linear Logic Networks. IEEE Trans. Computers Melvin A. Breuer
1972	J	`jnl`	Recent Developments in Design Automation. Computer Melvin A. Breuer
1971	J	`jnl`	A Random and an Algorithmic Technique for Fault Detection Test Generation for Sequential Circuits. IEEE Trans. Computers Melvin A. Breuer
1970	J	`jnl`	Functional Partitioning and Simulation of Digital Circuits. IEEE Trans. Computers Melvin A. Breuer
1970	J	`jnl`	Simplification of the Covering Problem with Application to Boolean Expressions. J. ACM Melvin A. Breuer
1969	J	`jnl`	Combinatorial Equivalence of (0, 1) Circulant Matrices. J. Comput. Syst. Sci. Melvin A. Breuer
1969	J	`jnl`	Generation of optimal code for expressions via factorization. Commun. ACM Melvin A. Breuer
1968	—	`conf`	Fault Detection in a Linear Cascade of Identical Machines SWAT Melvin A. Breuer
1968	—	`conf`	Hardware fault detection. AFIPS Fall Joint Computing Conference (2) Melvin A. Breuer
1968	—	`conf`	Heuristic switching expression simplification. ACM National Conference Melvin A. Breuer
1967	J	`jnl`	Adaptive Computers Inf. Control. Melvin A. Breuer
1966	J	`jnl`	Coding the vertexes of a graph. IEEE Trans. Inf. Theory Melvin A. Breuer
1966	A*	`conf`	The application of integer programming in design automation. DAC Melvin A. Breuer
1965	J	`jnl`	Implementation of Threshold Nets by Integer Linear Programming. IEEE Trans. Electron. Comput. Melvin A. Breuer
1964	J	`jnl`	Techniques for the simulation of computer logic. Commun. ACM Melvin A. Breuer
1962	—	`conf`	Computer design: The minimization of Boolean functions containing unequal and nonlinear cost functions. ACM National Conference Melvin A. Breuer