Mei Wen - RankMe

132 papers A* 6A 10B 12C 17Misc 4Journal 44Unranked 39

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	C-CIM: A Multi-Mode Convolution-Capable SRAM-CIM. ACM Trans. Design Autom. Electr. Syst. Renyu Yang, Xin Ju, Mei Wen, Jinjin Deng, Yi Wen, Junzhong Shen, Bin Liang, Tianyu Wang, Zhaoyan Shen, Zili Shao
2026	J	`jnl`	Precision boundary modeling for area-efficient Block Floating Point accumulation. J. Syst. Archit. Jun He, Jing Feng, Xin Ju, Yasong Cao, Zhongdi Luo, Jianchao Yang, Jingkui Yang, Gang Li, Jian Cheng, Dong Chen, Mei Wen
2025	J	`jnl`	A quantized network processor for mixed-precision deep learning models based on enhanced Microscaling format. J. Syst. Archit. Jing Feng, Mei Wen, Xin Ju, Zhuang Cao, Yang Guo
2025	C	`conf`	CAMO: A High-Performance CIM-based Lightweight CNN Accelerator for Mobile Devices. ISCAS Xin Ju, Renyu Yang, Mei Wen, Junzhong Shen, Tianyu Wang, Zhaoyan Shen, Zili Shao, Bin Liang
2025	J	`jnl`	ESCAN: Efficient GPU sharing for cascade neural network inference. Neural Networks Jianan Wang, Yang Shi, Zhaoyun Chen, Mei Wen
2025	J	`jnl`	HWPQ: Hessian-free Weight Pruning-Quantization For LLM Compression And Acceleration. CoRR Yuhan Kang, Zhongdi Luo, Mei Wen, Yang Shi, Jun He, Jianchao Yang, Zeyu Xue, Jing Feng, Xinwang Liu
2025	J	`jnl`	MAP-SIM: A DNN-Specific Mapping Optimization Framework for Shared-Memory CPU-Systolic Array Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yuhang Li, Mei Wen, Junzhong Shen, Zhaoyun Chen, Yang Shi, Tianyu Wang, Zili Shao
2025	J	`jnl`	SPSA: Exploring Sparse-Packing Computation on Systolic Arrays From Scratch. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Minjin Tang, Mei Wen, Jianchao Yang, Zeyu Xue, Junzhong Shen
2025	J	`jnl`	SSpMM: Efficiently Scalable SpMM Kernels Across Multiple Generations of Tensor Cores. IEEE Trans. Parallel Distributed Syst. Zeyu Xue, Mei Wen, Jianchao Yang, Minjin Tang, Zhongdi Luo, Jing Feng, Yang Shi, Zhaoyun Chen, Junzhong Shen, Johannes Langguth
2025	B	`conf`	SmartBlock: Adaptive Block Floating Point Quantization for Efficient DNN Acceleration. ICPP Xin Ju, Jingkui Yang, Mei Wen, Jun He, Jing Feng, Minjin Tang, Zhaoyun Chen, Yang Shi
2025	A	`conf`	SparSynergy: Unlocking Flexible and Efficient DNN Acceleration Through Multi-Level Sparsity. DATE Jingkui Yang, Mei Wen, Junzhong Shen, Jianchao Yang, Yasong Cao, Jun He, Minjin Tang, Zhaoyun Chen, Yang Shi
2025	J	`jnl`	SpikeFlow: A hardware-software co-designed systolic array for spiking neural networks. J. Syst. Archit. Jianan Wang, Yang Shi, Zhaoyun Chen, Mei Wen
2025	C	`conf`	Super Microscaling: Enhancing Precision and Hardware Efficiency in Deep Learning Quantization. ISCAS Jing Feng, Zhuang Cao, Xin Ju, Mei Wen, Yang Guo
2025	—	`conf`	SwiftPrune: Hessian-Free Weight Pruning for Large Language Models. EMNLP (Findings) Yuhan Kang, Yang Shi, Mei Wen, Jun He, Jianchao Yang, Zeyu Xue, Jing Feng, Xinwang Liu
2025	A	`conf`	WinAcc: Window-based Acceleration of Neural Networks Using Block Floating Point. DATE Xin Ju, Jun He, Mei Wen, Jing Feng, Yasong Cao, Junzhong Shen, Zhaoyun Chen, Yang Shi
2024	J	`jnl`	ABS: Accumulation Bit-Width Scaling Method for Designing Low-Precision Tensor Core. IEEE Trans. Very Large Scale Integr. Syst. Yasong Cao, Mei Wen, Zhongdi Luo, Xin Ju, Haolan Huang, Junzhong Shen, Haiyan Chen
2024	—	`conf`	BitShare: An Efficient Precision-Scalable Accelerator with Combining-Like-Terms GEMM. ASAP Yasong Cao, Mei Wen, Junzhong Shen, Zhongxing Li
2024	J	`jnl`	ESEN: Efficient GPU sharing of Ensemble Neural Networks. Neurocomputing Jianan Wang, Yang Shi, Zhaoyun Chen, Mei Wen
2024	C	`conf`	Enhancing the PE Utilization for Multi-Precision Systolic Array via Optimizing Computation Latency. ISCAS Jing Feng, Mei Wen, Xin Ju, Junzhong Shen, Yang Guo
2024	A*	`conf`	HyFiSS: A Hybrid Fidelity Stall-Aware Simulator for GPGPUs. MICRO Jianchao Yang, Mei Wen, Dong Chen, Zhaoyun Chen, Zeyu Xue, Yuhang Li, Junzhong Shen, Yang Shi
2024	—	`conf`	MAP-SIM: A Performance Model for Shared-Memory Heterogeneous Systems with Mapping Awareness. ICA3PP (1) Yuhang Li, Mei Wen, Junzhong Shen, Zhaoyun Chen, Yang Shi
2024	—	`conf`	MSA ICA3PP (3) Minjin Tang, Mei Wen, Junzhong Shen, Jingkui Yang, Zeyu Xue, Zili Shao
2024	J	`jnl`	Optimizing VLIW Instruction Scheduling via a Two-Dimensional Constrained Dynamic Programming. ACM Trans. Design Autom. Electr. Syst. Can Deng, Zhaoyun Chen, Yang Shi, Yimin Ma, Mei Wen, Lei Luo
2023	A*	`conf`	Automatic End-to-End Joint Optimization for Kernel Compilation on DSPs. DAC Xiaolei Zhao, Zhaoyun Chen, Yang Shi, Mei Wen, Chunyun Zhang
2023	C	`conf`	Releasing the Potential of Tensor Core for Unstructured SpMM using Tiled-CSR Format. ICCD Zeyu Xue, Mei Wen, Zhaoyun Chen, Yang Shi, Minjin Tang, Jianchao Yang, Zhongdi Luo
2022	C	`conf`	BP-Im2col: Implicit Im2col Supporting AI Backpropagation on Systolic Arrays. ICCD Jianchao Yang, Mei Wen, Junzhong Shen, Yasong Cao, Minjin Tang, Renyu Yang, Jiawei Fei, Chunyuan Zhang
2022	J	`jnl`	BP-Im2col: Implicit Im2col Supporting AI Backpropagation on Systolic Arrays. CoRR Jianchao Yang, Mei Wen, Junzhong Shen, Yasong Cao, Minjin Tang, Renyu Yang, Jiawei Fei, Chunyuan Zhang
2022	—	`conf`	CORF: Bridging the Gap of Complex Operator Fusion for Faster DNN Inference. HPCC/DSS/SmartCity/DependSys Jianan Wang, Yang Shi, Zhaoyun Chen, Mei Wen
2022	—	`conf`	Exploring ILP for VLIW Architecture by Quantified Modeling and Dynamic Programming-Based Instruction Scheduling. ASP-DAC Can Deng, Zhaoyun Chen, Yang Shi, Xichang Kong, Mei Wen
2022	—	`conf`	Light: A Component Enhances Faster and More Accurate Traffic Measurement ICC Jianchao Yang, Mei Wen, Xiaolei Zhao, Yang Shi
2022	—	`conf`	MZ Core: An Enhanced Matrix Acceleration Engine for HPC/ AI Applications. HPCC/DSS/SmartCity/DependSys Yasong Cao, Mei Wen, Junzhong Shen, Sheng Liu, Zhi Wang, Minjin Tang, Yahao Fang, Jianchao Yang, Renyu Yang, Yuhan Kang, Jiawei Fei
2022	B	`conf`	Mentha: Enabling Sparse-Packing Computation on Systolic Arrays. ICPP Minjin Tang, Mei Wen, Yasong Cao, Junzhong Shen, Jianchao Yang, Jiawei Fei, Yang Guo, Sheng Liu
2022	C	`conf`	S-SIM: A Simulator for Systolic Array-based DNN Accelerators with Tile Access Awareness. ISCAS Yuhang Li, Mei Wen, Renyu Yang, Junzhong Shen, Yasong Cao, Jianan Wang
2022	B	`conf`	TILE-SIM: A Systematic Approach to Systolic Array-based Accelerator Evaluation. ISPASS Yuhang Li, Mei Wen, Jiawei Fei, Junzhong Shen, Yasong Cao
2021	B	`conf`	Automatic mapping and code optimization for OpenCL kernels on FT-matrix architecture (WIP paper). LCTES Xiaolei Zhao, Mei Wen, Zhaoyun Chen, Yang Shi, Chunyuan Zhang
2021	—	`conf`	Embrace the Conflicts: Exploring the Integration of Single Port Memory in Systolic Array-based Accelerators. HPCC/DSS/SmartCity/DependSys Renyu Yang, Junzhong Shen, Mei Wen, Yasong Cao, Yuhang Li
2021	—	`conf`	SAI: Self-Adjusting Incremental Quantile Estimation for Sparse Training of Neural Networks on Hardware Accelerators. HPCC/DSS/SmartCity/DependSys Jianchao Yang, Mei Wen, Minjin Tang, Junzhong Shen, Chunyuan Zhang
2021	J	`jnl`	Sustaining Consumer Trust and Continuance Intention by Institutional Mechanisms: An Empirical Survey of DiDi in China. IEEE Access Minghua He, Jialiang Qin, Mei Wen, Wenbei Chen
2021	B	`conf`	sRouting: Towards a Better Flow Size Estimation Performance through Routing and Sketch Configuration. ICPP Yang Shi, Mei Wen
2020	J	`jnl`	Deep Learning Research and Development Platform: Characterizing and Scheduling with QoS Guarantees on GPU Clusters. IEEE Trans. Parallel Distributed Syst. Zhaoyun Chen, Wei Quan, Mei Wen, Jianbin Fang, Jie Yu, Chunyuan Zhang, Lei Luo
2020	J	`jnl`	Efficient Parallel TLD on CPU-GPU Platform for Real-Time Tracking. KSII Trans. Internet Inf. Syst. Zhaoyun Chen, Dafei Huang, Lei Luo, Mei Wen, Chunyuan Zhang
2020	—	`conf`	HybridSketch: A Memory-centric Precise Approach for Flow Measurement. ICC Xiaolei Zhao, Mei Wen, Minjin Tang, Qun Huang, Chunyuan Zhang
2020	C	`conf`	Incremental Deployment of Programmable Switches for Sketch-based Network Measurement. ISCC Yang Shi, Mei Wen, Chunyuan Zhang
2020	—	`conf`	Optimized HybridSketch: More Efficient with Analysis and Algorithm. ICA3PP (1) Xiaolei Zhao, Mei Wen, Minjin Tang, Qun Huang, Chunyuan Zhang
2020	J	`jnl`	P4 to FPGA-A Fast Approach for Generating Efficient Network Processors. IEEE Access Zhuang Cao, Huayou Su, Qianming Yang, Junzhong Shen, Mei Wen, Chunyuan Zhang
2020	A	`conf`	Scalable FPGA-based Architecture for High-Performance Per-Flow Traffic Measurement. FPGA Junzhong Shen, Mei Wen, Minjin Tang, Xiaolei Zhao, Chunyuan Zhang
2020	J	`jnl`	Toward an Efficient Deep Pipelined Template-Based Architecture for Accelerating the Entire 2-D and 3-D CNNs on FPGA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Junzhong Shen, You Huang, Mei Wen, Chunyuan Zhang
2020	B	`conf`	Towards High-Efficiency Data Centers via Job-Aware Network Scheduling. ICPP Yang Shi, Mei Wen, Chunyuan Zhang
2020	A*	`conf`	Towards Memory-Efficient Streaming Processing with Counter-Cascading Sketching on FPGA. DAC Minjin Tang, Mei Wen, Junzhong Shen, Xiaolei Zhao, Chunyuan Zhang
2020	—	`conf`	Towards a Deep-Pipelined Architecture for Accelerating Deep GCN on a Multi-FPGA Platform. ICA3PP (1) Qixuan Cheng, Mei Wen, Junzhong Shen, Deguang Wang, Chunyuan Zhang
2019	J	`jnl`	A Fast Approach for Generating Efficient Parsers on FPGAs. Symmetry Zhuang Cao, Huiguo Zhang, Junnan Li, Mei Wen, Chunyuan Zhang
2019	A	`conf`	Accelerating 3D CNN-based Lung Nodule Segmentation on a Multi-FPGA System. FPGA Junzhong Shen, Deguang Wang, You Huang, Mei Wen, Chunyuan Zhang
2019	B	`conf`	An Efficient Design Flow for Accelerating Complicated-connected CNNs on a Multi-FPGA Platform. ICPP Deguang Wang, Junzhong Shen, Mei Wen, Chunyuan Zhang
2019	J	`jnl`	Application-Oriented Network Scheduling With Metaflow. IEEE Access Yang Shi, Jiawei Fei, Mei Wen, Chunyuan Zhang
2019	A	`conf`	GENIE: QoS-guided Dynamic Scheduling for CNN-based Tasks on SME Clusters. DATE Zhaoyun Chen, Lei Luo, Haoduo Yang, Jie Yu, Mei Wen, Chunyuan Zhang
2019	J	`jnl`	Interleaved Sketch: Toward Consistent Network Telemetry for Commodity Programmable Switches. IEEE Access Zijun Hang, Mei Wen, Yang Shi, Chunyuan Zhang
2019	C	`conf`	KVSwitch: An In-network Load Balancer for Key-Value Stores. ISCC Yang Shi, Jiawei Fei, Mei Wen, Chunyuan Zhang
2019	—	`conf`	Metaflow: A Better Traffic Abstraction for Distributed Applications. HPCC/SmartCity/DSS Yang Shi, Jiawei Fei, Mei Wen, Qun Huang, Nan Wu
2019	J	`jnl`	Metaflow: A DAG-Based Network Abstraction for Distributed Applications. CoRR Jiawei Fei, Yang Shi, Qun Huang, Mei Wen
2019	—	`conf`	Poster Abstract: A Template-based Framework for Generating Network Processor in FPGA. INFOCOM Workshops Zhuang Cao, Huayou Su, Qianming Yang, Mei Wen, Chunyuan Zhang
2019	—	`conf`	Poster Abstract: Deep Learning Workloads Scheduling with Reinforcement Learning on GPU Clusters. INFOCOM Workshops Zhaoyun Chen, Lei Luo, Wei Quan, Mei Wen, Chunyuan Zhang
2019	—	`conf`	SACC: Configuring Application-Level Cache Intelligently for In-Memory Database Based on Long Short-Term Memory. HPCC/SmartCity/DSS Jiawei Fei, Yang Shi, Mei Wen, Chunyuan Zhang
2019	—	`conf`	SWAP: a sliding window algorithm for in-network packet measurement. HP3C Zijun Hang, Yang Shi, Mei Wen, Wei Quan, Chunyuan Zhang
2019	A*	`conf`	Scale-out Acceleration for 3D CNN-based Lung Nodule Segmentation on a Multi-FPGA System. DAC Junzhong Shen, Deguang Wang, You Huang, Mei Wen, Chunyuan Zhang
2019	—	`conf`	TBSW: Time-Based Sliding Window Algorithm for Network Traffic Measurement. HPCC/SmartCity/DSS Zijun Hang, Yang Shi, Mei Wen, Chunyuan Zhang
2019	C	`conf`	Towards a Uniform Architecture for the Efficient Implementation of 2D and 3D Deconvolutional Neural Networks on FPGAs. ISCAS Deguang Wang, Junzhong Shen, Mei Wen, Chunyuan Zhang
2019	J	`jnl`	Towards a Uniform Architecture for the Efficient Implementation of 2D and 3D Deconvolutional Neural Networks on FPGAs. CoRR Deguang Wang, Junzhong Shen, Mei Wen, Chunyuan Zhang
2018	J	`jnl`	HPGraph: High-Performance Graph Analytics with Productivity on the GPU. Sci. Program. Haoduo Yang, Huayou Su, Qiang Lan, Mei Wen, Chunyuan Zhang
2018	—	`conf`	High performance graph analytics with productivity on hybrid CPU-GPU platforms. HP3C Haoduo Yang, Huayou Su, Qiang Lan, Mei Wen, Chunyuan Zhang
2018	J	`jnl`	MALMM: A multi-array architecture for large-scale matrix multiplication on FPGA. IEICE Electron. Express You Huang, Junzhong Shen, Yuran Qiao, Mei Wen, Chunyuan Zhang
2018	—	`conf`	Multiple CNN-based Tasks Scheduling across Shared GPU Platform in Research and Development Scenarios. HPCC/SmartCity/DSS Zhaoyun Chen, Lei Luo, Wei Quan, Yang Shi, Jie Yu, Mei Wen, Chunyuan Zhang
2018	C	`conf`	Towards a Multi-array Architecture for Accelerating Large-scale Matrix Multiplication on FPGAs. ISCAS Junzhong Shen, Yuran Qiao, You Huang, Mei Wen, Chunyuan Zhang
2018	J	`jnl`	Towards a Multi-array Architecture for Accelerating Large-scale Matrix Multiplication on FPGAs. CoRR Junzhong Shen, Yuran Qiao, You Huang, Mei Wen, Chunyuan Zhang
2018	A	`conf`	Towards a Uniform Template-based Architecture for Accelerating 2D and 3D CNNs on FPGA. FPGA Junzhong Shen, You Huang, Zelong Wang, Yuran Qiao, Mei Wen, Chunyuan Zhang
2017	J	`jnl`	A Highly Parallel and Scalable Motion Estimation Algorithm with GPU for HEVC. Sci. Program. Yun-gang Xue, Huayou Su, Ju Ren, Mei Wen, Chunyuan Zhang, Li-Quan Xiao
2017	J	`jnl`	Applying Detection Proposals to Visual Tracking for Scale and Aspect Ratio Adaptability. Int. J. Comput. Vis. Dafei Huang, Lei Luo, Zhaoyun Chen, Mei Wen, Chunyuan Zhang
2017	J	`jnl`	Exploiting a depth context model in visual tracking with correlation filter. Frontiers Inf. Technol. Electron. Eng. Zhaoyun Chen, Lei Luo, Dafei Huang, Mei Wen, Chunyuan Zhang
2017	J	`jnl`	FPGA-accelerated deep convolutional neural networks for high throughput and energy efficiency. Concurr. Comput. Pract. Exp. Yuran Qiao, Junzhong Shen, Tao Xiao, Qianming Yang, Mei Wen, Chunyuan Zhang
2017	J	`jnl`	High Performance Implementation of 3D Convolutional Neural Networks on a GPU. Comput. Intell. Neurosci. Qiang Lan, Zelong Wang, Mei Wen, Chunyuan Zhang, Yijie Wang
2017	C	`conf`	Optimizing OpenCL Implementation of Deep Convolutional Neural Network on FPGA. NPC Yuran Qiao, Junzhong Shen, Dafei Huang, Qianming Yang, Mei Wen, Chunyuan Zhang
2017	—	`conf`	RVNet: A fast and high energy efficiency network packet processing system on RISC-V. ASAP Yanpeng Wang, Mei Wen, Chunyuan Zhang, Jie Lin
2016	B	`conf`	Enabling Tissue-Scale Cardiac Simulations Using Heterogeneous Computing on Tianhe-2. ICPADS Johannes Langguth, Qiang Lan, Namit Gaur, Xing Cai, Mei Wen, Chunyuan Zhang
2015	J	`jnl`	An analytical GPU performance model for 3D stencil computations from the angle of data traffic. J. Supercomput. Huayou Su, Xing Cai, Mei Wen, Chunyuan Zhang
2015	J	`jnl`	Communication-hiding programming for clusters with multi-coprocessor nodes. Concurr. Comput. Pract. Exp. Xinnan Dong, Mei Wen, Jun Chai, Xing Cai, Mandan Zhao, Chunyuan Zhang
2015	A	`conf`	Enable Scale and Aspect Ratio Adaptability in Visual Tracking with Detection Proposals. BMVC Dafei Huang, Lei Luo, Mei Wen, Zhaoyun Chen, Chunyuan Zhang
2015	J	`jnl`	Enabling a Uniform OpenCL Device View for Heterogeneous Platforms. IEICE Trans. Inf. Syst. Dafei Huang, Changqing Xun, Nan Wu, Mei Wen, Chunyuan Zhang, Xing Cai, Qianming Yang
2015	B	`conf`	Fast tracking via context depth model learning. ICIP Zhaoyun Chen, Lei Luo, Mei Wen, Chunyuan Zhang
2015	J	`jnl`	Improving performance portability for GPU-specific OpenCL kernels on multi-core/many-core CPUs by analysis-based transformations. Frontiers Inf. Technol. Electron. Eng. Mei Wen, Dafei Huang, Changqing Xun, Dong Chen
2015	J	`jnl`	Towards simulation of subcellular calcium dynamics at nanometre resolution. Int. J. High Perform. Comput. Appl. Jun Chai, Johan Hake, Nan Wu, Mei Wen, Xing Cai, Glenn Terje Lines, Jing Yang, Huayou Su, Chunyuan Zhang, Xiangke Liao
2015	—	`conf`	Unified Virtual Memory Support for Deep CNN Accelerator on SoC FPGA. ICA3PP (1) Tao Xiao, Yuran Qiao, Junzhong Shen, Qianming Yang, Mei Wen
2014	—	`conf`	Automated Transformation of GPU-Specific OpenCL Kernels Targeting Performance Portability on Multi-Core/Many-Core CPUs. Euro-Par Dafei Huang, Mei Wen, Changqing Xun, Dong Chen, Xing Cai, Yuran Qiao, Nan Wu, Chunyuan Zhang
2014	J	`jnl`	High efficient sedimentary basin simulations on hybrid CPU-GPU clusters. Clust. Comput. Mei Wen, Huayou Su, Wenjie Wei, Nan Wu, Xing Cai, Chunyuan Zhang
2014	—	`conf`	Utilizing Multiple Xeon Phi Coprocessors on One Compute Node. ICA3PP (2) Xinnan Dong, Jun Chai, Jing Yang, Mei Wen, Nan Wu, Xing Cai, Chunyuan Zhang, Zhaoyun Chen
2013	—	`conf`	ACF: Networks-on-Chip Deadlock Recovery with Accurate Detection and Elastic Credit. APPT Nan Wu, Yuran Qiao, Mei Wen, Chunyuan Zhang
2013	J	`jnl`	Accelerating thread-intensive and explicit memory management programs with dynamic partial reconfiguration. J. Supercomput. Qianming Yang, Mei Wen, Nan Wu, Chunyuan Zhang
2013	—	`conf`	Automatic Mapping Single-Device OpenCL Program to Heterogeneous Multi-device Platform. HPCC/EUC Dong Chen, Changqing Xun, Dafei Huang, Mei Wen, Chunyuan Zhang
2013	C	`conf`	On the GPU Performance of 3D Stencil Computations Implemented in OpenCL. ISC Huayou Su, Nan Wu, Mei Wen, Chunyuan Zhang, Xing Cai
2013	B	`conf`	On the GPU-CPU Performance Portability of OpenCL for 3D Stencil Computations. ICPADS Huayou Su, Nan Wu, Mei Wen, Chunyuan Zhang, Xing Cai
2013	Misc	`conf`	Performance of Sediment Transport Simulations on NVIDIA's Kepler Architecture. ICCS Huayou Su, Nan Wu, Mei Wen, Chunyuan Zhang, Xing Cai
2013	J	`jnl`	Resource-efficient utilization of CPU/GPU-based heterogeneous supercomputers for Bayesian phylogenetic inference. J. Supercomput. Jun Chai, Huayou Su, Mei Wen, Xing Cai, Nan Wu, Chunyuan Zhang
2013	J	`jnl`	Simulating Cardiac Electrophysiology in the Era of GPU-Cluster Computing. IEICE Trans. Inf. Syst. Jun Chai, Mei Wen, Nan Wu, Dafei Huang, Jing Yang, Xing Cai, Chunyuan Zhang, Qianming Yang
2013	—	`conf`	Solving the Cardiac Model Using Multi-core CPU and Many Integrated Cores (MIC). HPCC/EUC Jing Yang, Jun Chai, Mei Wen, Nan Wu, Chunyuan Zhang
2012	B	`conf`	A Parallel H.264 Encoder with CUDA: Mapping and Evaluation. ICPADS Nan Wu, Mei Wen, Huayou Su, Ju Ren, Chunyuan Zhang
2012	B	`conf`	Extending BORPH for shared memory reconfigurable computers. FPL Changqing Xun, Mei Wen, Nan Wu, Chunyuan Zhang, Hayden Kwok-Hay So
2012	C	`conf`	Improving Performance of GPU Specific OpenCL Program on CPUs. PDCAT Qiang Lan, Changqing Xun, Mei Wen, Huayou Su, Lifang Liu, Chunyuan Zhang
2012	A	`conf`	Parallelization Design of Irregular Algorithms of Video Processing on GPUs. ICME Huayou Su, Jun Chai, Mei Wen, Ju Ren, Chunyuan Zhang
2012	A	`conf`	The masala machine: accelerating thread-intensive and explicit memory management programs with dynamically reconfigurable FPGAs (abstract only). FPGA Mei Wen, Nan Wu, Qianming Yang, Chunyuan Zhang, Liang Zhao
2012	C	`conf`	Using 1000+ GPUs and 10000+ CPUs for Sedimentary Basin Simulations. CLUSTER Mei Wen, Huayou Su, Wenjie Wei, Nan Wu, Xing Cai, Chunyuan Zhang
2011	Misc	`conf`	A Multilevel Parallel Intra Coding for H.264/AVC Based on CUDA. ICIG Huayou Su, Nan Wu, Chunyuan Zhang, Mei Wen, Ju Ren
2011	—	`conf`	A high-efficient software parallel CAVCL encoder based on GPU. TSP Huayou Su, Chunyuan Zhang, Jun Chai, Mei Wen, Nan Wu, Ju Ren
2011	J	`jnl`	Cross-Market Financial Risk Analysis: an Agent-Based Computational Finance. Int. J. Inf. Technol. Decis. Mak. Xiong Xiong, Mei Wen, Wei Zhang, Yongjie Zhang
2011	A*	`conf`	High-efficient software parallel CAVLC encoder based on programmable stream processor. ACM Multimedia Huayou Su, Chunyuan Zhang, Jun Chai, Mei Wen, Nan Wu, Ju Ren
2011	J	`jnl`	Tiled Multi-Core Stream Architecture. Trans. High Perform. Embed. Archit. Compil. Nan Wu, Qianming Yang, Mei Wen, Yi He, Ju Ren, Maolin Guan, Chunyuan Zhang
2010	—	`conf`	A Parallel Streaming Motion Estimation for Real-Time HD H.264 Encoding on Programmable Processors. FCST Ju Ren, Mei Wen, Chunyuan Zhang, Huayou Su, Yi He, Nan Wu
2010	C	`conf`	SAT: A Stream Architecture Template for Embedded Applications. CIT Qianming Yang, Nan Wu, Mei Wen, Yi He, Huayou Su, Chunyuan Zhang
2010	C	`conf`	Software Managed Instruction Scratchpad Memory Optimization in Stream Architecture Based on Hot Code Analysis of Kernels. DSD Yi He, Ju Ren, Mei Wen, Qianming Yang, Nan Wu, Chunyuan Zhang
2009	Misc	`conf`	Cache streamization for high performance stream processor. HiPC Nan Wu, Mei Wen, Ju Ren, Yi He, Changqing Xun, Wei Wu, Chunyuan Zhang
2009	—	`conf`	Software parallel CAVLC encoder based on stream processing. ESTIMedia Ju Ren, Yi He, Wei Wu, Mei Wen, Nan Wu, Chunyuan Zhang
2009	A*	`conf`	Streaming HD H.264 encoder on programmable processors. ACM Multimedia Nan Wu, Mei Wen, Wei Wu, Ju Ren, Huayou Su, Changqing Xun, Chunyuan Zhang
2008	A	`conf`	FPGA-based Equivalent Simulation Technology (FEST) for clustered stream architecture. ACSAC Yi He, Ju Ren, Qianming Yang, Mei Wen, Nan Wu, Chunyuan Zhang
2008	—	`conf`	Load scheduling: Reducing pressure on distributed register files for free. ASP-DAC Mei Wen, Nan Wu, Maolin Guan, Chunyuan Zhang
2008	J	`jnl`	On-Chip Memory System Optimization Design for the FT64 Scientific Stream Accelerator. IEEE Micro Mei Wen, Nan Wu, Chunyuan Zhang, Qianming Yang, Ju Ren, Yi He, Wei Wu, Jun Chai, Maolin Guan, Changqing Xun
2007	—	`conf`	A Stream System-on-Chip Architecture for High Speed Target Recognition Based on Biologic Vision. Asia-Pacific Computer Systems Architecture Conference Nan Wu, Qianming Yang, Mei Wen, Yi He, Changqing Xun, Chunyuan Zhang
2007	Misc	`conf`	FT64: Scientific Computing with Streams. HiPC Mei Wen, Nan Wu, Chunyuan Zhang, Wei Wu, Qianming Yang, Changqing Xun
2006	—	`conf`	Analysis and Performance Results of a fluid dynamics Application on MASA Stream Processor. ACIS-ICIS Mei Wen, Nan Wu, Changqing Xun, Wei Wu, Chunyuan Zhang
2006	—	`conf`	Optimization and Evaluating of StreamYGX2 on MASA Stream Processor. Asia-Pacific Computer Systems Architecture Conference Mei Wen, Nan Wu, Changqing Xun, Wei Wu, Chunyuan Zhang
2006	—	`conf`	Register Allocation on Stream Processor with Local Register File. Asia-Pacific Computer Systems Architecture Conference Nan Wu, Mei Wen, Ju Ren, Yi He, Chunyuan Zhang
2005	—	`conf`	A Stream Architecture Supporting Multiple Stream Execution Models. Asia-Pacific Computer Systems Architecture Conference Nan Wu, Mei Wen, Haiyan Li, Li Li, Chunyuan Zhang
2005	—	`conf`	Accelerated Motion Estimation of H.264 on Imagine Stream Processor. ICIAR Haiyan Li, Mei Wen, Chunyuan Zhang, Nan Wu, Li Li, Changqing Xun
2005	J	`jnl`	Multiple-Morphs Adaptive Stream Architecture. J. Comput. Sci. Technol. Mei Wen, Nan Wu, Haiyan Li, Chunyuan Zhang
2004	C	`conf`	A Parallel Reed-Solomon Decoder on the Imagine Stream Processor. ISPA Mei Wen, Chunyuan Zhang, Nan Wu, Haiyan Li, Li Li
2004	—	`conf`	Multiple-Dimension Scalable Adaptive Stream Architecture. Asia-Pacific Computer Systems Architecture Conference Mei Wen, Nan Wu, Haiyan Li, Chunyuan Zhang