Mehran Goli

41 papers A 3C 14Misc 2Journal 8Unranked 13
YearRankTypeTitle / Venue / Authors
2025 J jnl
OPTI-Sim: Performing Optical Probing Simulation on Layout Design Files.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Sajjad Parvin, Mehran Goli, Frank Sill Torres, Rolf Drechsler
2024 J jnl
Early SoCs Information Flow Policies Validation Using SystemC-Based Virtual Prototypes at the ESL.
ACM Trans. Embed. Comput. Syst.
Mehran Goli, Rolf Drechsler
2023 — conf
EDDY: A Multi-Core BDD Package with Dynamic Memory Management and Reduced Fragmentation.
ASP-DAC
Rune Krauss, Mehran Goli, Rolf Drechsler
2023 C conf
Efficient Binary Decision Diagram Manipulation by Reducing the Number of Intermediate Nodes.
DDECS
Rune Krauss, Mehran Goli, Rolf Drechsler
2023 C conf
Efficient ML-Based Performance Estimation Approach Across Different Microarchitectures for RISC-V Processors.
DSD
Weiyan Zhang, Mehran Goli, Muhammad Hassan, Rolf Drechsler
2023 A conf
FELOPi: A Framework for Simulation and Evaluation of Post-Layout File Against Optical Probing.
DATE
Sajjad Parvin, Mehran Goli, Frank Sill Torres, Rolf Drechsler
2023 — conf
Fast and Accurate: Machine Learning Techniques for Performance Estimation of CNNs for GPGPUs.
IPDPS Workshops
Christopher A. Metz, Mehran Goli, Rolf Drechsler
2023 — conf
LAT-UP: Exposing Layout-Level Analog Hardware Trojans Using Contactless Optical Probing.
ISVLSI
Sajjad Parvin, Mehran Goli, Thilo Krachenfels, Shahin Tajik, Jean-Pierre Seifert, Frank Sill Torres, Rolf Drechsler
2023 — conf
Polynomial Formal Verification of a Processor: A RISC-V Case Study.
ISQED
Lennart Weingarten, Alireza Mahzoon, Mehran Goli, Rolf Drechsler
2023 — conf
Trojan-D2: Post-Layout Design and Detection of Stealthy Hardware Trojans - A RISC-V Case Study.
ASP-DAC
Sajjad Parvin, Mehran Goli, Frank Sill Torres, Rolf Drechsler
2023 — conf
VAST: Validation of VP-based Heterogeneous Systems against Availability Security Properties using Static Information Flow Tracking.
ISQED
Ece Nur Demirhan Coskun, Muhammad Hassan, Mehran Goli, Rolf Drechsler
2022 C conf
ANN-based Performance Estimation of Embedded Software for RISC-V Processors.
RSP
Weiyan Zhang, Mehran Goli, Alireza Mahzoon, Rolf Drechsler
2022 C conf
Early Performance Estimation of Embedded Software on RISC-V Processor using Linear Regression.
DDECS
Weiyan Zhang, Mehran Goli, Rolf Drechsler
2022 C conf
ML-based Power Estimation of Convolutional Neural Networks on GPGPUs.
DDECS
Christopher A. Metz, Mehran Goli, Rolf Drechsler
2022 — conf
Simulation-based Verification of SystemC-based VPs at the ESL.
MBMV
Mehran Goli, Rolf Drechsler
2022 J jnl
Simulation-based Verification of SystemC-based VPs at the ESL.
CoRR
Mehran Goli, Rolf Drechsler
2022 J jnl
Through the Looking Glass: Automated Design Understanding of SystemC-Based VPs at the ESL.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Mehran Goli, Rolf Drechsler
2022 — conf
Towards Neural Hardware Search: Power Estimation of CNNs for GPGPUs with Dynamic Frequency Scaling.
MLCAD
Christopher A. Metz, Mehran Goli, Rolf Drechsler
2022 C conf
Towards Polynomial Formal Verification of Complex Arithmetic Circuits.
DDECS
Rolf Drechsler, Alireza Mahzoon, Mehran Goli
2021 — conf
ATLaS: Automatic Detection of Timing-based Information Leakage Flows for SystemC HLS Designs.
ASP-DAC
Mehran Goli, Rolf Drechsler
2021 C conf
Automated Debugging-Aware Visualization Technique for SystemC HLS Designs.
DSD
Mehran Goli, Alireza Mahzoon, Rolf Drechsler
2021 A conf
Early Validation of SoCs Security Architecture Against Timing Flows Using SystemC-based VPs.
ICCAD
Mehran Goli, Rolf Drechsler
2021 Misc conf
Early power estimation of CUDA-based CNNs on GPGPUs: work-in-progress.
CODES+ISSS
Christopher A. Metz, Mehran Goli, Rolf Drechsler
2021 J jnl
Pick the Right Edge Device: Towards Power and Performance Estimation of CUDA-based CNNs on GPGPUs.
CoRR
Christopher A. Metz, Mehran Goli, Rolf Drechsler
2021 C conf
VIP-VP: Early Validation of SoCs Information Flow Policies using SystemC-based Virtual Prototypes.
FDL
Mehran Goli, Rolf Drechsler
2020 C conf
ASCHyRO: Automatic Fault Localization of SystemC HLS Designs Using a Hybrid Accurate Rank Ordering Technique.
ICCD
Mehran Goli, Alireza Mahzoon, Rolf Drechsler
2020 — conf
Automated Design Understanding of SystemC-Based Virtual Prototypes: Data Extraction, Analysis and Visualization.
ISVLSI
Mehran Goli, Rolf Drechsler
2020 J jnl
Automated Nonintrusive Analysis of Electronic System Level Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Mehran Goli, Jannis Stoppe, Rolf Drechsler
2020 J jnl
PREASC: Automatic Portion Resilience Evaluation for Approximating SystemC-based Designs Using Regression Analysis Techniques.
ACM Trans. Design Autom. Electr. Syst.
Mehran Goli, Rolf Drechsler
2020 C conf
Towards Generation of a Programmable Power Management Unit at the Electronic System Level.
DDECS
David Lemma, Mehran Goli, Daniel Große, Rolf Drechsler
2019 — conf
Automated Analysis of Virtual Prototypes at Electronic System Level.
ACM Great Lakes Symposium on VLSI
Mehran Goli, Muhammad Hassan, Daniel Große, Rolf Drechsler
2019 — ch.
Automatisierte Analyse virtueller Prototypen auf der ESL.
Ausgezeichnete Informatikdissertationen
Mehran Goli
2019 C conf
Scalable Simulation-Based Verification of SystemC-Based Virtual Prototypes.
DSD
Mehran Goli, Rolf Drechsler
2019 J jnl
Security validation of VP-based SoCs using dynamic information flow tracking.
it Inf. Technol.
Mehran Goli, Muhammad Hassan, Daniel Große, Rolf Drechsler
2018 — conf
Power Intent from Initial ESL Prototypes: Extracting Power Management Parameters
NORCAS
David Lemma, Mehran Goli, Daniel Große, Rolf Drechsler
2018 C conf
Resilience Evaluation for Approximating SystemC Designs Using Machine Learning Techniques.
RSP
Mehran Goli, Jannis Stoppe, Rolf Drechsler
2017 C conf
Automatic Protocol Compliance Checking of SystemC TLM-2.0 Simulation Behavior Using Timed Automata.
ICCD
Mehran Goli, Jannis Stoppe, Rolf Drechsler
2017 A conf
Automatic equivalence checking for SystemC-TLM 2.0 models against their formal specifications.
DATE
Mehran Goli, Jannis Stoppe, Rolf Drechsler
2016 C conf
AIBA: An Automated Intra-cycle Behavioral Analysis for SystemC-based design exploration.
ICCD
Mehran Goli, Jannis Stoppe, Rolf Drechsler
2015 — conf
Application-specific power-aware mapping for reconfigurable NoC architectures.
DTIS
Mehran Goli, Amin Ghasemazar, Zainalabedin Navabi
2014 Misc conf
Embedded Complex Floating Point Hardware Accelerator.
VLSID
Amin Ghasemazar, Mehran Goli, Ali Afzali-Kusha