Mehdi Sadi

34 papers A* 1A 3C 2Misc 3Journal 19Unranked 6
YearRankTypeTitle / Venue / Authors
2026 A* conf
Exploration of LLM Workload Reliability Based on di/dt Effects and Voltage Droops.
HPCA
Zhixing Jiang, Justin Garrigus, Allison Seigler, Ethan Syed, Yan-Lun Huang, Mehdi Sadi, Tawfik Rahal-Arabi, Lizy Kurian John
2025 J jnl
Chiplet-Gym: Optimizing Chiplet-Based AI Accelerator Design With Reinforcement Learning.
IEEE Trans. Computers
Kaniz Mishty, Mehdi Sadi
2024 J jnl
Chiplet-Gym: Optimizing Chiplet-based AI Accelerator Design with Reinforcement Learning.
CoRR
Kaniz Mishty, Mehdi Sadi
2024 J jnl
SNNLP: Energy-Efficient Natural Language Processing Using Spiking Neural Networks.
CoRR
R. Alexander Knipper, Kaniz Mishty, Mehdi Sadi, Shubhra Kanti Karmaker Santu
2024 J jnl
System and Design Technology Co-Optimization of SOT-MRAM for High-Performance AI Accelerator Memory System.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Kaniz Mishty, Mehdi Sadi
2023 J jnl
Attacking Deep Learning AI Hardware with Universal Adversarial Perturbation.
Inf.
Mehdi Sadi, Bashir Mohammad Sabquat Bahar Talukder, Kaniz Mishty, Md. Tauhidur Rahman
2023 — conf
System and Design Technology Co-optimization of Chiplet-based AI Accelerator with Machine Learning.
ACM Great Lakes Symposium on VLSI
Kaniz Mishty, Mehdi Sadi
2023 J jnl
System and Design Technology Co-optimization of SOT-MRAM for High-Performance AI Accelerator Memory System.
CoRR
Kaniz Mishty, Mehdi Sadi
2022 — conf
Analogy-Guided Evolutionary Pretraining of Binary Word Embeddings.
AACL/IJCNLP (1)
R. Alexander Knipper, Md. Mahadi Hassan, Mehdi Sadi, Shubhra Kanti Karmaker Santu
2022 Misc conf
Special Session: On the Reliability of Conventional and Quantum Neural Network Hardware.
VTS
Mehdi Sadi, Yi He, Yanjing Li, Mahabubul Alam, Satwik Kundu, Swaroop Ghosh, Javad Bahrami, Naghmeh Karimi
2022 J jnl
Test and Yield Loss Reduction of AI and Deep Learning Accelerators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Mehdi Sadi, Ujjwal Guin
2021 J jnl
Attacking Deep Learning AI Hardware with Universal Adversarial Perturbation.
CoRR
Mehdi Sadi, Bashir M. Sabquat Bahar Talukder, Kaniz Mishty, Md. Tauhidur Rahman
2021 J jnl
Designing Efficient and High-Performance AI Accelerators With Customized STT-MRAM.
IEEE Trans. Very Large Scale Integr. Syst.
Kaniz Mishty, Mehdi Sadi
2021 J jnl
Designing Efficient and High-performance AI Accelerators with Customized STT-MRAM.
CoRR
Kaniz Mishty, Mehdi Sadi
2021 Misc conf
Special Session: Reliability Analysis for AI/ML Hardware.
VTS
Shamik Kundu, Kanad Basu, Mehdi Sadi, Twisha Titirsha, Shihao Song, Anup Das, Ujjwal Guin
2021 J jnl
Special Session: Reliability Analysis for ML/AI Hardware.
CoRR
Shamik Kundu, Kanad Basu, Mehdi Sadi, Twisha Titirsha, Shihao Song, Anup Das, Ujjwal Guin
2021 — conf
True Random Number Generation using Latency Variations of Commercial MRAM Chips.
ISQED
Farah Ferdaus, Bashir M. Sabquat Bahar Talukder, Mehdi Sadi, Md. Tauhidur Rahman
2021 J jnl
True Random Number Generation using Latency Variations of Commercial MRAM Chips.
CoRR
Farah Ferdaus, Bashir M. Sabquat Bahar Talukder, Mehdi Sadi, Md. Tauhidur Rahman
2020 J jnl
Soft-HaT: Software-Based Silicon Reprogramming for Hardware Trojan Implementation.
ACM Trans. Design Autom. Electr. Syst.
Md. Mahbub Alam, Adib Nahiyan, Mehdi Sadi, Domenic Forte, Mark Tehranipoor
2020 J jnl
Yield Loss Reduction and Test of AI and Deep Learning Accelerators.
CoRR
Mehdi Sadi, Ujjwal Guin
2018 J jnl
Hardware Trojan Detection through Information Flow Security Verification.
CoRR
Adib Nahiyan, Mehdi Sadi, Rahul Vittal, Gustavo K. Contreras, Domenic Forte, Mark Tehranipoor
2017 J jnl
Design of Reliable SoCs With BIST Hardware and Machine Learning.
IEEE Trans. Very Large Scale Integr. Syst.
Mehdi Sadi, Gustavo K. Contreras, Jifeng Chen, LeRoy Winemberg, Mark Tehranipoor
2017 C conf
Design of a digital IP for 3D-IC die-to-die clock synchronization.
ISCAS
Mehdi Sadi, Sukeshwar Kannan, Luke England, Mark Tehranipoor
2017 A conf
Hardware trojan detection through information flow security verification.
ITC
Adib Nahiyan, Mehdi Sadi, Rahul Vittal, Gustavo K. Contreras, Domenic Forte, Mark Tehranipoor
2017 J jnl
SoC Speed Binning Using Machine Learning and On-Chip Slack Sensors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Mehdi Sadi, Sukeshwar Kannan, LeRoy Winemberg, Mark Tehranipoor
2017 J jnl
TRO: An On-Chip Ring Oscillator-Based GHz Transient IR-Drop Monitor.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Xiaoxiao Wang, Pengyuan Jiao, Mehdi Sadi, Donglin Su, LeRoy Winemberg, Mark Tehranipoor
2016 C conf
An efficient all-digital IR-Drop Alarmer for DVFS-based SoC.
ISCAS
Liting Yu, Xiaoxiao Wang, Yuanqing Cheng, Xiaoying Zhao, Pengyuan Jiao, Aixin Chen, Donglin Su, LeRoy Winemberg, Mehdi Sadi, Mark Tehranipoor
2016 A conf
BIST-RM: BIST-assisted reliability management of SoCs using on-chip clock sweeping and machine learning.
ITC
Mehdi Sadi, Gustavo K. Contreras, Dat Tran, Jifeng Chen, LeRoy Winemberg, Mark Tehranipoor
2016 J jnl
Design of a Network of Digital Sensor Macros for Extracting Power Supply Noise Profile in SoCs.
IEEE Trans. Very Large Scale Integr. Syst.
Mehdi Sadi, Mark Tehranipoor
2016 A conf
Power delivery in 3D packages: current crowding effects, dynamic IR drop and compensation network using sensors (invited paper).
ICCAD
Sukeshwar Kannan, Mehdi Sadi, Luke England
2015 Misc conf
A robust digital sensor IP and sensor insertion flow for in-situ path timing slack monitoring in SoCs.
VTS
Mehdi Sadi, LeRoy Winemberg, Mark Tehranipoor
2015 — conf
Speed Binning Using Machine Learning And On-chip Slack Sensors.
ACM Great Lakes Symposium on VLSI
Mehdi Sadi, Mark Tehranipoor, Xiaoxiao Wang, LeRoy Winemberg
2014 — conf
An All Digital Distributed Sensor Network Based Framework for Continuous Noise Monitoring and Timing Failure Analysis in SoCs.
ATS
Mehdi Sadi, Zoe Conroy, Bill Eklow, Matthias Kamm, Nematollah Bidokhti, Mark Mohammad Tehranipoor
2012 — conf
Design of near threshold All Digital Delay Locked Loops.
SoCC
Mehdi Sadi, Mircea Stan