Meghna Madhusudan

31 papers A* 1A 10B 1Journal 9Unranked 10

Year	Rank	Type	Title / Venue / Authors
2024	J	`jnl`	Constructive Place-and-Route for FinFET-Based Transistor Arrays in Analog Circuits Under Nonlinear Gradients. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Arvind K. Sharma, Meghna Madhusudan, Steven M. Burns, Soner Yaldiz, Parijat Mukherjee, Ramesh Harjani, Sachin S. Sapatnekar
2024	J	`jnl`	MMM: Machine Learning-Based Macro-Modeling for Linear Analog ICs and ADC/DACs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yishuang Lin, Yaguang Li, Meghna Madhusudan, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu
2024	B	`conf`	Reinforcing the Connection between Analog Design and EDA (Invited Paper). ASPDAC Kishor Kunal, Meghna Madhusudan, Jitesh Poojary, S. Ramprasath, Arvind K. Sharma, Ramesh Harjani, Sachin S. Sapatnekar
2023	J	`jnl`	A Generalized Methodology for Well Island Generation and Well-tap Insertion in Analog/Mixed-signal Layouts. ACM Trans. Design Autom. Electr. Syst. Ramprasath Srinivasa Gopalakrishnan, Meghna Madhusudan, Arvind K. Sharma, Jitesh Poojary, Soner Yaldiz, Ramesh Harjani, Steven M. Burns, Sachin S. Sapatnekar
2023	J	`jnl`	Constructive Placement and Routing for Common-Centroid Capacitor Arrays in Binary-Weighted and Split DACs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Nibedita Karmokar, Arvind K. Sharma, Jitesh Poojary, Meghna Madhusudan, Ramesh Harjani, Sachin S. Sapatnekar
2023	J	`jnl`	GNN-Based Hierarchical Annotation for Analog Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kishor Kunal, Tonmoy Dhar, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Jiang Hu, Ramesh Harjani, Sachin S. Sapatnekar
2023	—	`conf`	MMM: Machine Learning-Based Macro-Modeling for Linear Analog ICs and ADC/DACs. MLCAD Yishuang Lin, Yaguang Li, Meghna Madhusudan, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu
2023	J	`jnl`	Performance-driven Wire Sizing for Analog Integrated Circuits. ACM Trans. Design Autom. Electr. Syst. Yaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind K. Sharma, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu
2023	—	`conf`	Understanding Distance-Dependent Variations for Analog Circuits in a FinFET Technology. ESSDERC Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Ramprasath S, Kishor Kunal, Sachin S. Sapatnekar, Ramesh Harjani
2022	—	`conf`	Analog/Mixed-Signal Layout Optimization using Optimal Well Taps. ISPD Ramprasath S, Meghna Madhusudan, Arvind K. Sharma, Jitesh Poojary, Soner Yaldiz, Ramesh Harjani, Steven M. Burns, Sachin S. Sapatnekar
2022	A	`conf`	Are Analytical Techniques Worthwhile for Analog IC Placement? DATE Yishuang Lin, Yaguang Li, Donghao Fang, Meghna Madhusudan, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu
2022	—	`conf`	Common-Centroid Layout for Active and Passive Devices: A Review and the Road Ahead. ASP-DAC Nibedita Karmokar, Meghna Madhusudan, Arvind K. Sharma, Ramesh Harjani, Mark Po-Hung Lin, Sachin S. Sapatnekar
2022	A	`conf`	Constructive Common-Centroid Placement and Routing for Binary-Weighted Capacitor Arrays. DATE Nibedita Karmokar, Arvind K. Sharma, Jitesh Poojary, Meghna Madhusudan, Ramesh Harjani, Sachin S. Sapatnekar
2021	—	`conf`	A Circuit Attention Network-Based Actor-Critic Learning Approach to Robust Analog Transistor Sizing. MLCAD Yaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind K. Sharma, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu
2021	J	`jnl`	ALIGN: A System for Automating Analog Layout. IEEE Des. Test Tonmoy Dhar, Kishor Kunal, Yaguang Li, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Ramesh Harjani, Jiang Hu, Desmond A. Kirkpatrick, Parijat Mukherjee, Soner Yaldiz, Sachin S. Sapatnekar
2021	A	`conf`	Analog Layout Generation using Optimized Primitives. DATE Meghna Madhusudan, Arvind K. Sharma, Yaguang Li, Jiang Hu, Sachin S. Sapatnekar, Ramesh Hajiani
2021	A	`conf`	Common-Centroid Layouts for Analog Circuits: Advantages and Limitations. DATE Arvind K. Sharma, Meghna Madhusudan, Steven M. Burns, Parijat Mukherjee, Soner Yaldiz, Ramesh Harjani, Sachin S. Sapatnekar
2021	—	`conf`	Fast and Efficient Constraint Evaluation of Analog Layout Using Machine Learning Models. ASP-DAC Tonmoy Dhar, Jitesh Poojary, Yaguang Li, Kishor Kunal, Meghna Madhusudan, Arvind K. Sharma, Susmita Dey Manasi, Jiang Hu, Ramesh Harjani, Sachin S. Sapatnekar
2021	A	`conf`	From Specification to Silicon: Towards Analog/Mixed-Signal Design Automation using Surrogate NN Models with Transfer Learning. ICCAD Juzheng Liu, Shiyu Su, Meghna Madhusudan, Mohsen Hassanpourghadi, Samuel Saunders, Qiaochu Zhang, Rezwan A. Rasul, Yaguang Li, Jiang Hu, Arvind Kumar Sharma, Sachin S. Sapatnekar, Ramesh Harjani, Anthony Levi, Sandeep Gupta, Mike Shuo-Wei Chen
2021	—	`conf`	Machine Learning Techniques in Analog Layout Automation. ISPD Tonmoy Dhar, Kishor Kunal, Yaguang Li, Yishuang Lin, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Steven M. Burns, Ramesh Harjani, Jiang Hu, Parijat Mukherjee, Soner Yaldiz, Sachin S. Sapatnekar
2021	A	`conf`	Performance-Aware Common-Centroid Placement and Routing of Transistor Arrays in Analog Circuits. ICCAD Arvind K. Sharma, Meghna Madhusudan, Steven M. Burns, Soner Yaldiz, Parijat Mukherjee, Ramesh Harjani, Sachin S. Sapatnekar
2020	A	`conf`	A Customized Graph Neural Network Model for Guiding Analog IC Placement. ICCAD Yaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind K. Sharma, Wenbin Xu, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu
2020	A	`conf`	A general approach for identifying hierarchical symmetry constraints for analog circuit layout. ICCAD Kishor Kunal, Jitesh Poojary, Tonmoy Dhar, Meghna Madhusudan, Ramesh Harjani, Sachin S. Sapatnekar
2020	J	`jnl`	A general approach for identifying hierarchical symmetry constraints for analog circuit layout. CoRR Kishor Kunal, Jitesh Poojary, Tonmoy Dhar, Meghna Madhusudan, Ramesh Harjani, Sachin S. Sapatnekar
2020	J	`jnl`	ALIGN: A System for Automating Analog Layout. CoRR Tonmoy Dhar, Kishor Kunal, Yaguang Li, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Ramesh Harjani, Jiang Hu, Desmond A. Kirkpatrick, Parijat Mukherjee, Sachin S. Sapatnekar, Soner Yaldiz
2020	—	`conf`	Exploring a Machine Learning Approach to Performance Driven Analog IC Placement. ISVLSI Yaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind K. Sharma, Wenbin Xu, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu
2020	A	`conf`	GANA: Graph Convolutional Network Based Automated Netlist Annotation for Analog Circuits. DATE Kishor Kunal, Tonmoy Dhar, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Jiang Hu, Ramesh Harjani, Sachin S. Sapatnekar
2020	—	`conf`	Learning from Experience: Applying ML to Analog Circuit Design. ISPD Kishor Kunal, Tonmoy Dhar, Yaguang Li, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Ramesh Harjani, Jiang Hu, Parijat Mukherjee, Sachin S. Sapatnekar
2020	A	`conf`	The ALIGN Open-Source Analog Layout Generator: v1.0 and Beyond (Invited talk). ICCAD Tonmoy Dhar, Kishor Kunal, Yaguang Li, Yishuang Lin, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Steven M. Burns, Ramesh Harjani, Jiang Hu, Parijat Mukherjee, Soner Yaldiz, Sachin S. Sapatnekar
2019	A*	`conf`	ALIGN: Open-Source Analog Layout Automation from the Ground Up. DAC Kishor Kunal, Meghna Madhusudan, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Ramesh Harjani, Jiang Hu, Desmond A. Kirkpatrick, Sachin S. Sapatnekar
2019	—	`conf`	Design Techniques for Zero Steady-State Output Ripple in Digital Low Dropout Regulators. MWSCAS Saurabh Chaubey, Meghna Madhusudan, Ramesh Harjani