Mayukh Bhattacharya

23 papers A 3C 1Misc 6Journal 7Unranked 5

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	Enhancing Analog IC Security Using Randomized Obfuscation Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jayeeta Chaudhuri, Mayukh Bhattacharya, Krishnendu Chakrabarty
2024	J	`jnl`	DAWN: Efficient Trojan Detection in Analog Circuits Using Circuit Watermarking and Neural Twins. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jayeeta Chaudhuri, Mayukh Bhattacharya, Krishnendu Chakrabarty
2023	Misc	`conf`	Accelerating Defect Simulation in Analog and Mixed-Signal Circuits by Parallel Defect Injection. VLSID Sayandeep Sanyal, Mayukh Bhattacharya, Pallab Dasgupta, Amit Patra
2022	A	`conf`	Application of Sampling in Industrial Analog Defect Simulation. ITC Mayukh Bhattacharya, Beatrice Solignac, Michael Dürr
2022	A	`conf`	Automatic Structural Test Generation for Analog Circuits using Neural Twins. ITC Jonti Talukdar, Arjun Chaudhuri, Mayukh Bhattacharya, Krishnendu Chakrabarty
2020	J	`jnl`	A Methodology for Identification of Internal Nets for Improving Fault Coverage in Analog and Mixed Signal Circuits. J. Electron. Test. Sayandeep Sanyal, Mayukh Bhattacharya, Amit Patra, Pallab Dasgupta
2019	—	`conf`	A Structured Approach for Rapid Identification of Fault-Sensitive Nets in Analog Circuits. ATS Sayandeep Sanyal, Amit Patra, Pallab Dasgupta, Mayukh Bhattacharya
2019	—	`conf`	Fault Classification and Coverage of Analog Circuits using DC Operating Point and Frequency Response Analysis. ACM Great Lakes Symposium on VLSI Sayandeep Sanyal, Shan Pavan Pani Krishna Garapati, Amit Patra, Pallab Dasgupta, Mayukh Bhattacharya
2018	Misc	`conf`	Innovative practices on functional testing and fault simulation for FuSa. VTS Anandh Krishnan, John van Gelder, Mayukh Bhattacharya, Sreejit Chakravarty, Prashant Goteti
2001	—	`conf`	A 250-MHz, 32-bit quantum MOS correlator prototype. ICECS Shriram Kulkarni, Mayukh Bhattacharya, Alejandro F. González, Pinaki Mazumder
2001	J	`jnl`	A physical design tool for built-in self-repairable RAMs. IEEE Trans. Very Large Scale Integr. Syst. Kanad Chakraborty, Shriram Kulkarni, Mayukh Bhattacharya, Pinaki Mazumder, Anurag Gupta
2001	J	`jnl`	Augmentation of SPICE for simulation of circuits containingresonant tunneling diodes. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Mayukh Bhattacharya, Pinaki Mazumder
2001	J	`jnl`	CMOS implementation of a multiple-valued logic signed-digit full adder based on negative-differentiaI-resistance devices. IEEE J. Solid State Circuits Alejandro F. González, Mayukh Bhattacharya, Shriram Kulkarni, Pinaki Mazumder
2001	Misc	`conf`	Fd-Tlm Electromagnetic Field Simulation Of High-Speed Iii-V Heterojunction Bipolar Transistor Digital Logic Gates. VLSI Design Mayukh Bhattacharya, Pinaki Mazumder, Ronald J. Lomax
2001	Misc	`conf`	Modeling of Nonuniform Interconnects by Using Differential Quadrature Method. VLSI Design Qinwei Xu, Pinaki Mazumder, Mayukh Bhattacharya
2000	C	`conf`	A prototyping technique for large-scale RTD-CMOS circuits. ISCAS Mayukh Bhattacharya, Shriram Kulkarni, Alejandro F. González, Pinaki Mazumder
2000	Misc	`conf`	Convergence Issues in Resonant Tunneling Diode Circuit Simulation. VLSI Design Mayukh Bhattacharya, Pinaki Mazumder
2000	—	`conf`	Standard CMOS Implementation of a Multiple-Valued Logic Signed-Digit Adder Based on Negative Differential-Resistance Devices. ISMVL Alejandro F. González, Mayukh Bhattacharya, Shriram Kulkarni, Pinaki Mazumder
1999	A	`conf`	A Physical Design Tool for Built-in Self-Repairable Static RAMs. DATE Kanad Chakraborty, Anurag Gupta, Mayukh Bhattacharya, Shriram Kulkarni, Pinaki Mazumder
1999	—	`—`	Simulation and emulation of digital integrated circuits containing resonant tunneling diodes. Mayukh Bhattacharya
1998	Misc	`conf`	Circuit Design using Resonant Tunneling Diodes. VLSI Design Pinaki Mazumder, Shriram Kulkarni, Mayukh Bhattacharya, Alejandro F. González
1998	J	`jnl`	Digital circuit applications of resonant tunneling devices. Proc. IEEE Pinaki Mazumder, Shriram Kulkarni, Mayukh Bhattacharya, Jian Ping Sun, George I. Haddad
1998	—	`conf`	Noise Margins of Threshold Logic Gates containing Resonant Tunneling Diodes. Great Lakes Symposium on VLSI Mayukh Bhattacharya, Pinaki Mazumder