Mayler G. A. Martins

27 papers C 5Journal 9Unranked 13
YearRankTypeTitle / Venue / Authors
2023 J jnl
A Security-Aware and LUT-Based CAD Flow for the Physical Synthesis of hASICs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Zain Ul Abideen, Tiago Diadami Perez, Mayler G. A. Martins, Samuel Pagliarini
2022 J jnl
A Security-aware and LUT-based CAD Flow for the Physical Synthesis of eASICs.
CoRR
Zain Ul Abideen, Tiago Diadami Perez, Mayler G. A. Martins, Samuel Pagliarini
2020 J jnl
From Virtual Characterization to Test-Chips: DFM Analysis Through Pattern Enumeration.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Mayler G. A. Martins, Samuel N. Pagliarini, Mehmet Meric Isgenc, Lawrence T. Pileggi
2020 J jnl
Logic IP for Low-Cost IC Design in Advanced CMOS Nodes.
IEEE Trans. Very Large Scale Integr. Syst.
Mehmet Meric Isgenc, Mayler G. A. Martins, V. Mohammed Zackriya, Samuel N. Pagliarini, Lawrence T. Pileggi
2018 J jnl
A Simple and Effective Heuristic Method for Threshold Logic Identification.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Augusto Neutzling, Mayler G. A. Martins, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas
2018 J jnl
Application and Product-Volume-Specific Customization of BEOL Metal Pitch.
IEEE Trans. Very Large Scale Integr. Syst.
Samuel N. Pagliarini, Mehmet Meric Isgenc, Mayler G. A. Martins, Lawrence T. Pileggi
2018 J jnl
Design of approximate-TMR using approximate library and heuristic approaches.
Microelectron. Reliab.
Iuri Albandes Cunha Gomes, Alejandro Serrano-Cases, Mayler G. A. Martins, Antonio Martínez-Álvarez, Sergio Cuenca-Asensi, Fernanda Lima Kastensmidt
2018 — conf
Improving approximate-TMR using multi-objective optimization genetic algorithm.
LATS
Iuri Albandes Cunha Gomes, Alejandro Serrano-Cases, Antonio J. Sanchez-Clemente, Mayler G. A. Martins, Antonio Martínez-Álvarez, Sergio Cuenca-Asensi, Fernanda Lima Kastensmidt
2017 — conf
Virtual characterization for exhaustive DFM evaluation of logic cell libraries.
ISQED
Samuel Pagliarini, Mayler G. A. Martins, Lawrence T. Pileggi
2015 C conf
Bottom-up disjoint-support decomposition based on cofactor and boolean difference analysis.
ICCD
Vinicius Callegaro, Felipe S. Marranghello, Mayler G. A. Martins, Renato P. Ribas, André Inácio Reis
2015 C conf
Enhanced Spin-Diode Synthesis Using Logic Sharing.
DSD
Mayler G. A. Martins, Felipe S. Marranghello, Joseph S. Friedman, Alan V. Sahakian, Renato P. Ribas, André Inácio Reis
2015 J jnl
Exploring the use of approximate TMR to mask transient faults in logic with low area overhead.
Microelectron. Reliab.
Iuri A. C. Gomes, Mayler G. A. Martins, André Inácio Reis, Fernanda Lima Kastensmidt
2015 J jnl
Factored Forms for Memristive Material Implication Stateful Logic.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Felipe S. Marranghello, Vinicius Callegaro, Mayler G. A. Martins, André Inácio Reis, Renato P. Ribas
2015 C conf
Improved logic synthesis for memristive stateful logic using multi-memristor implication.
ISCAS
Felipe S. Marranghello, Vinicius Callegaro, Mayler G. A. Martins, André Inácio Reis, Renato P. Ribas
2015 — conf
Open Cell Library in 15nm FreePDK Technology.
ISPD
Mayler G. A. Martins, Jody Maick Matos, Renato P. Ribas, André Inácio Reis, Guilherme Schlinker, Lucio Rech, Jens Michelsen
2015 — conf
Using only redundant modules with approximate logic to reduce drastically area overhead in TMR.
LATS
Iuri A. C. Gomes, Mayler G. A. Martins, André Inácio Reis, Fernanda Lima Kastensmidt
2014 C conf
A constructive approach for threshold logic circuit synthesis.
ISCAS
Augusto Neutzling, Mayler G. A. Martins, Renato P. Ribas, André Inácio Reis
2014 — conf
Methodology for achieving best trade-off of area and fault masking coverage in ATMR.
LATW
Iuri A. C. Gomes, Mayler G. A. Martins, Fernanda Lima Kastensmidt, André Inácio Reis, Renato P. Ribas, Sylvain P. Novales
2014 — conf
Semi-custom NCL Design with Commercial EDA Frameworks: Is it Possible?
ASYNC
Matheus T. Moreira, Augusto Neutzling, Mayler G. A. Martins, André Inácio Reis, Renato P. Ribas, Ney Calazans
2013 — conf
Iterative remapping respecting timing constraints.
ISVLSI
Lucas Machado, Mayler G. A. Martins, Vinicius Callegaro, Renato P. Ribas, André Inácio Reis
2013 — conf
Read-polarity-once Boolean functions.
SBCCI
Vinicius Callegaro, Mayler G. A. Martins, Renato P. Ribas, André Inácio Reis
2013 — conf
Spin diode network synthesis using functional composition.
SBCCI
Mayler G. A. Martins, Felipe S. Marranghello, Joseph S. Friedman, Alan V. Sahakian, Renato P. Ribas, André Inácio Reis
2013 — conf
Synthesis of threshold logic gates to nanoelectronics.
SBCCI
Augusto Neutzling, Mayler G. A. Martins, Renato P. Ribas, André Inácio Reis
2012 — conf
Functional composition: A new paradigm for performing logic synthesis.
ISQED
Mayler G. A. Martins, Renato P. Ribas, André Inácio Reis
2012 — conf
KL-cut based digital circuit remapping.
NORCHIP
Lucas Machado, Mayler G. A. Martins, Vinicius Callegaro, Renato P. Ribas, André Inácio Reis
2011 — conf
Efficient method to compute minimum decision chains of Boolean functions.
ACM Great Lakes Symposium on VLSI
Mayler G. A. Martins, Vinicius Callegaro, Renato P. Ribas, André Inácio Reis
2010 C conf
Boolean factoring with multi-objective goals.
ICCD
Mayler G. A. Martins, Leomar S. da Rosa Jr., Anders B. Rasmussen, Renato P. Ribas, André Inácio Reis