Maxime Nassar - RankMe

14 papers A 3B 1Misc 2Journal 2Unranked 6

Year	Rank	Type	Title / Venue / Authors
2012	A	`conf`	RSM: A small and fast countermeasure for AES, secure against 1st and 2nd-order zero-offset SCAs. DATE Maxime Nassar, Youssef Souissi, Sylvain Guilley, Jean-Luc Danger
2012	B	`conf`	Towards Different Flavors of Combined Side Channel Attacks. CT-RSA Youssef Souissi, Shivam Bhasin, Sylvain Guilley, Maxime Nassar, Jean-Luc Danger
2011	—	`conf`	"Rank Correction": A New Side-Channel Approach for Secret Key Recovery. InfoSecHiComNet Maxime Nassar, Youssef Souissi, Sylvain Guilley, Jean-Luc Danger
2011	—	`conf`	"Re-synchronization by moments": An efficient solution to align Side-Channel traces. WIFS Nicolas Debande, Youssef Souissi, Maxime Nassar, Sylvain Guilley, Thanh-Ha Le, Jean-Luc Danger
2011	—	`conf`	Embedded systems security: An evaluation methodology against Side Channel Attacks. DASIP Youssef Souissi, Jean-Luc Danger, Sylvain Guilley, Shivam Bhasin, Maxime Nassar
2011	Misc	`conf`	Formal Analysis of the Entropy / Security Trade-off in First-Order Masking Countermeasures against Side-Channel Attacks. INDOCRYPT Maxime Nassar, Sylvain Guilley, Jean-Luc Danger
2011	J	`jnl`	Formal Analysis of the Entropy / Security Trade-off in First-Order Masking Countermeasures against Side-Channel Attacks. IACR Cryptol. ePrint Arch. Maxime Nassar, Sylvain Guilley, Jean-Luc Danger
2010	A	`conf`	BCDL: A high speed balanced DPL for FPGA with global precharge and no early evaluation. DATE Maxime Nassar, Shivam Bhasin, Jean-Luc Danger, Guillaume Duc, Sylvain Guilley
2010	J	`jnl`	Exploiting Dual-Output Programmable Blocks to Balance Secure Dual-Rail Logics. Int. J. Reconfigurable Comput. Laurent Sauvage, Maxime Nassar, Sylvain Guilley, Florent Flament, Jean-Luc Danger, Yves Mathieu
2010	Misc	`conf`	First Principal Components Analysis: A New Side Channel Distinguisher. ICISC Youssef Souissi, Maxime Nassar, Sylvain Guilley, Jean-Luc Danger, Florent Flament
2009	—	`conf`	Combined SCA and DFA Countermeasures Integrable in a FPGA Design Flow. ReConFig Shivam Bhasin, Jean-Luc Danger, Florent Flament, Tarik Graba, Sylvain Guilley, Yves Mathieu, Maxime Nassar, Laurent Sauvage, Nidhal Selmane
2009	—	`conf`	DPL on Stratix II FPGA: What to Expect?. ReConFig Laurent Sauvage, Maxime Nassar, Sylvain Guilley, Florent Flament, Jean-Luc Danger, Yves Mathieu
2009	A	`conf`	Successful attack on an FPGA-based WDDL DES cryptoprocessor without place and route constraints. DATE Laurent Sauvage, Sylvain Guilley, Jean-Luc Danger, Yves Mathieu, Maxime Nassar
2008	—	`conf`	Place-and-Route Impact on the Security of DPL Designs in FPGAs. HOST Sylvain Guilley, Sumanta Chaudhuri, Jean-Luc Danger, Laurent Sauvage, Philippe Hoogvorst, Maxime Nassar, Tarik Graba, Vinh-Nga Vong