Mauro Olivieri

130 papers A* 4A 4B 3C 6Misc 1Journal 61Unranked 50

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Configurable Hardware Acceleration for Hyperdimensional Computing Extension on RISC-V. IEEE Trans. Computers Rocco Martino, Marco Angioli, Antonello Rosato, Marcello Barbirotta, Abdallah Cheikh, Mauro Olivieri
2026	J	`jnl`	HD-CB: The First Exploration of Hyperdimensional Computing for Contextual Bandits Problems. IEEE Open J. Comput. Soc. Marco Angioli, Antonello Rosato, Marcello Barbirotta, Rocco Martino, Francesco Menichelli, Mauro Olivieri
2025	J	`jnl`	Efficient Hyperdimensional Computing with Modular Composite Representations. CoRR Marco Angioli, Christopher J. Kymn, Antonello Rosato, Amy Loutfi, Mauro Olivieri, Denis Kleyko
2025	J	`jnl`	Efficient Implementation of LinearUCB through Algorithmic Improvements and Vector Computing Acceleration for Embedded Learning Systems. CoRR Marco Angioli, Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Mauro Olivieri
2025	J	`jnl`	Efficient Implementation of LinearUCB through Algorithmic Improvements and Vector Computing Acceleration for Embedded Learning Systems. ACM Trans. Embed. Comput. Syst. Marco Angioli, Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Mauro Olivieri
2025	J	`jnl`	HD-CB: The First Exploration of Hyperdimensional Computing for Contextual Bandits Problems. CoRR Marco Angioli, Antonello Rosato, Marcello Barbirotta, Rocco Martino, Francesco Menichelli, Mauro Olivieri
2025	B	`conf`	HD-CBBIN: A Lightweight Approach for Contextual Bandit Learning in Real-Time Applications. IJCNN Marco Angioli, Antonello Rosato, Marcello Barbirotta, Rocco Martino, Andrea Marcelli, Antonio Mastrandrea, Mauro Olivieri
2025	—	`conf`	Implementing the RISC-V Debug Specification on an Interleaved Multi-Threading Core. ApplePies Andrea Marcelli, Marco Pisani, Marco Angioli, Rocco Martino, Antonio Mastrandrea, Mauro Olivieri
2025	—	`conf`	Innovative Techniques for Efficient Hyperdimensional Computing on Hardware: Enhance Accuracy and On-the-Fly Hypervector Generation. IJCCI (3) Saeid Jamili, Sabereh Taghdisi Rastkar, Marco Angioli, Mauro Olivieri
2025	—	`conf`	Re-Architecting RISC-V: A 64-Bit Take on Interleaved Multi-threading. ApplePies Andrea Marcelli, Marco Pisani, Rocco Martino, Abdallah Cheikh, Francesco Menichelli, Mauro Olivieri
2025	C	`conf`	Towards RISC-V-based HPC: The Italian Pathfinding Activities in the DARE-SGA1 Project. DSD Giovanni Agosta, Marco Aldinucci, Andrea Bartolini, Laura Bellentani, Andrea Biagioni, Daniele Cesarini, Carlotta Chiarini, Iacopo Colonnelli, Pietro Delugas, Lev Denisov, Ottorino Frezza, Marco Grangetto, Francesca Lo Cicero, Alessandro Lonardo, Michele Martinelli, Andrea Maslov, Mauro Olivieri, Pierpaolo Perticaroli, Luca Pontisso, Cristian Rossi, Davide Rossi, Sergio Saponara, Antonio Sciarappa, Francesco Simula, Matteo Sonza Reorda, Massimo Torquati, Piero Vicini
2024	J	`jnl`	A RISC-V Fault-Tolerant Soft-Processor Based on Full/Partial Heterogeneous Dual-Core Protection. IEEE Access Francesco Vigli, Marcello Barbirotta, Abdallah Cheikh, Francesco Menichelli, Antonio Mastrandrea, Mauro Olivieri
2024	B	`conf`	AeneasHDC: An Automatic Framework for Deploying Hyperdimensional Computing Models on FPGAs. IJCNN Marco Angioli, Saeid Jamili, Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Antonello Rosato, Mauro Olivieri
2024	—	`conf`	Alternative Implementations of Error Correcting Codes in Register Files of a RISC-V Safety Critical Processor. ApplePies Marcello Barbirotta, Marco Angioli, Antonio Mastrandrea, Abdallah Cheikh, Francesco Menichelli, Mauro Olivieri
2024	J	`jnl`	Design, Implementation and Evaluation of a New Variable Latency Integer Division Scheme. IEEE Trans. Computers Marco Angioli, Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Saeid Jamili, Mauro Olivieri
2024	—	`conf`	Dual-Modular-Redundancy Voting Circuits for Single-Event-Transient Mitigation. DFT Marcello Barbirotta, Marco Angioli, Antonio Mastrandrea, Francesco Menichelli, Abdallah Cheikh, Mauro Olivieri
2024	J	`jnl`	Dynamic Triple Modular Redundancy in Interleaved Hardware Threads: An Alternative Solution to Lockstep Multi-Cores for Fault-Tolerant Systems. IEEE Access Marcello Barbirotta, Francesco Menichelli, Abdallah Cheikh, Antonio Mastrandrea, Marco Angioli, Mauro Olivieri
2024	J	`jnl`	Enhancing Fault Tolerance in High-Performance Computing: A Real Hardware Case Study on a RISC-V Vector Processing Unit. IEEE Open J. Comput. Soc. Marcello Barbirotta, Francesco Minervini, Carlos Rojas Morales, Adrián Cristal, Osman S. Unsal, Mauro Olivieri
2024	—	`conf`	Exploring Variable Latency Dividers in Vector Hardware Accelerators. PRIME Marco Angioli, Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Mauro Olivieri
2024	—	`conf`	Special Session: SE-UVM, an Integrated Simulation Environment for Single Event Induced Failures Characterization and its Application to the CV32E40P Processor. DFT Marcello Barbirotta, Marco Angioli, Antonio Mastrandrea, Francesco Menichelli, Abdallah Cheikh, Mauro Olivieri
2023	—	`conf`	A Universal Hardware Emulator for Verification IPs on FPGA: A Novel and Low-Cost Approach. ApplePies Saeid Jamili, Antonio Mastrandrea, Abdallah Cheikh, Marcello Barbirotta, Francesco Menichelli, Marco Angioli, Mauro Olivieri
2023	—	`conf`	Alessandro De Gloria, a Pioneer in Electronic Engineering Applications. ApplePies Francesco Bellotti, Elisa Bricco, Agostino G. Bruzzone, Daniele D. Caviglia, Ermanno Di Zitti, Paolo Gastaldo, Daniele Grosso, Lauro Magnani, Mauro Olivieri, Marco Raggio, Maurizio Valle, Alessandro Verri, Riccardo Berta
2023	—	`conf`	Automatic Hardware Accelerators Reconfiguration through LinearUCB Algorithms on a RISC-V Processor. PRIME Marco Angioli, Marcello Barbirotta, Antonio Mastrandrea, Saeid Jamili, Mauro Olivieri
2023	J	`jnl`	FAUST: Design and implementation of a pipelined RISC-V vector floating-point unit. Microprocess. Microsystems Mate Kovac, Leon Dragic, Branimir Malnar, Francesco Minervini, Oscar Palomar, Carlos Rojas, Mauro Olivieri, Josip Knezovic, Mario Kovac
2023	—	`conf`	Heterogeneous Tightly-Coupled Dual Core Architecture Against Single Event Effects. ApplePies Marcello Barbirotta, Francesco Menichelli, Antonio Mastrandrea, Abdallah Cheikh, Marco Angioli, Saeid Jamili, Mauro Olivieri
2023	A*	`conf`	Mix-GEMM: An efficient HW-SW Architecture for Mixed-Precision Quantized Deep Neural Networks Inference on Edge Devices. HPCA Enrico Reggiani, Alessandro Pappalardo, Max Doblas, Miquel Moretó, Mauro Olivieri, Osman Sabri Unsal, Adrián Cristal
2023	—	`conf`	Single Event Transient Reliability Analysis on a Fault-Tolerant RISC-V Microprocessor Design. ApplePies Marcello Barbirotta, Marco Angioli, Antonio Mastrandrea, Abdallah Cheikh, Saeid Jamili, Francesco Menichelli, Mauro Olivieri
2023	J	`jnl`	Vitruvius+: An Area-Efficient RISC-V Decoupled Vector Coprocessor for High Performance Computing Applications. ACM Trans. Archit. Code Optim. Francesco Minervini, Oscar Palomar, Osman S. Unsal, Enrico Reggiani, Josue V. Quiroga, Joan Marimon, Carlos Rojas, Roger Figueras, Abraham Ruiz, Alberto González, Jonnatan Mendoza, Iván Vargas, César Hernández, Joan Cabre, Lina Khoirunisya, Mustapha Bouhali, Julian Pavon, Francesc Moll, Mauro Olivieri, Mario Kovac, Mate Kovac, Leon Dragic, Mateo Valero, Adrián Cristal
2022	—	`conf`	Analysis of a Fault Tolerant Edge-Computing Microarchitecture Exploiting Vector Acceleration. PRIME Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Mauro Olivieri
2022	A*	`conf`	BiSon-e: a lightweight and high-performance accelerator for narrow integer linear algebra computing on the edge. ASPLOS Enrico Reggiani, Cristóbal Ramírez Lazo, Roger Figueras Bagué, Adrián Cristal, Mauro Olivieri, Osman Sabri Unsal
2022	—	`conf`	Contextual Bandits Algorithms for Reconfigurable Hardware Accelerators. ApplePies Marco Angioli, Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Saeid Jamili, Mauro Olivieri
2022	J	`jnl`	Design and Evaluation of Buffered Triple Modular Redundancy in Interleaved-Multi-Threading Processors. IEEE Access Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Mauro Olivieri
2022	—	`conf`	Implementation of Dynamic Acceleration Unit Exchange on a RISC-V Soft-Processor. ApplePies Saeid Jamili, Abdallah Cheikh, Antonio Mastrandrea, Marcello Barbirotta, Francesco Menichelli, Marco Angioli, Mauro Olivieri
2021	—	`conf`	A Fault Tolerant soft-core obtained from an Interleaved-Multi- Threading RISC- V microprocessor design. DFT Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Francesco Vigli, Mauro Olivieri
2021	J	`jnl`	Klessydra-T: Designing Vector Coprocessors for Multithreaded Edge-Computing Cores. IEEE Micro Abdallah Cheikh, Stefano Sordillo, Antonio Mastrandrea, Francesco Menichelli, Giuseppe Scotti, Mauro Olivieri
2021	—	`conf`	The Italian research on HPC key technologies across EuroHPC. CF Marco Aldinucci, Giovanni Agosta, Antonio Andreini, Claudio Agostino Ardagna, Andrea Bartolini, Alessandro Cilardo, Biagio Cosenza, Marco Danelutto, Roberto Esposito, William Fornaciari, Roberto Giorgi, Davide Lengani, Raffaele Montella, Mauro Olivieri, Sergio Saponara, Daniele Simoni, Massimo Torquati
2020	—	`conf`	Fault resilience analysis of a RISC-V microprocessor design through a dedicated UVM environment. DFT Marcello Barbirotta, Antonio Mastrandrea, Francesco Menichelli, Francesco Vigli, Luigi Blasi, Abdallah Cheikh, Stefano Sordillo, Fabio Di Gennaro, Mauro Olivieri
2020	J	`jnl`	Klessydra-T: Designing Vector Coprocessors for Multi-Threaded Edge-Computing Cores. CoRR Abdallah Cheikh, Stefano Sordillo, Antonio Mastrandrea, Francesco Menichelli, Giuseppe Scotti, Mauro Olivieri
2020	J	`jnl`	SC-DDPL: A Novel Standard-Cell Based Approach for Counteracting Power Analysis Attacks in the Presence of Unbalanced Routing. IEEE Trans. Circuits Syst. I Regul. Pap. Davide Bellizia, Simone Bongiovanni, Mauro Olivieri, Giuseppe Scotti
2019	—	`conf`	A RISC-V Fault-Tolerant Microcontroller Core Architecture Based on a Hardware Thread Full/Partial Protection and a Thread-Controlled Watch-Dog Timer. ApplePies Luigi Blasi, Francesco Vigli, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Mauro Olivieri
2019	—	`conf`	Efficient Mathematical Accelerator Design Coupled with an Interleaved Multi-threading RISC-V Microprocessor. ApplePies Abdallah Cheikh, Stefano Sordillo, Antonio Mastrandrea, Francesco Menichelli, Mauro Olivieri
2019	J	`jnl`	Full System Emulation of Approximate Memory Platforms with AppropinQuo. J. Low Power Electron. Giulia Stazi, Antonio Mastrandrea, Mauro Olivieri, Francesco Menichelli
2019	—	`conf`	Quality Aware Approximate Memory in RISC-V Linux Kernel. PRIME Giulia Stazi, Antonio Mastrandrea, Mauro Olivieri, Francesco Menichelli
2019	—	`conf`	Quality Aware Selective ECC for Approximate DRAM. ApplePies Giulia Stazi, Antonio Mastrandrea, Mauro Olivieri, Francesco Menichelli
2019	J	`jnl`	The international race towards Exascale in Europe. CCF Trans. High Perform. Comput. Fabrizio Gagliardi, Miquel Moretó, Mauro Olivieri, Mateo Valero
2018	—	`conf`	AppropinQuo: A Platform Emulator for Exploring the Approximate Memory Design Space. NGCAS Giulia Stazi, Antonio Mastrandrea, Mauro Olivieri, Francesco Menichelli
2018	—	`conf`	Approximate Memory Support for Linux Early Allocators in ARM Architectures. ApplePies Giulia Stazi, Antonio Mastrandrea, Mauro Olivieri, Francesco Menichelli
2018	C	`conf`	Characterizing noise pulse effects on the power consumption of idle digital cells. ISCAS Mauro Olivieri, Usman Khalid, Antonio Mastrandrea, Francesco Menichelli
2018	—	`conf`	Impact of Approximate Memory Data Allocation on a H.264 Software Video Encoder. ISC Workshops Giulia Stazi, Lorenzo Adani, Antonio Mastrandrea, Mauro Olivieri, Francesco Menichelli
2018	—	`conf`	LEADER: Leakage Currents Estimation Technique for Aging Degradation Aware 16 nm CMOS Circuits. VDAT Zia Abbas, Andleeb Zahra, Mauro Olivieri
2018	—	`conf`	Synthesis Time Reconfigurable Floating Point Unit for Transprecision Computing. ApplePies Giulia Stazi, Federica Silvestri, Antonio Mastrandrea, Mauro Olivieri, Francesco Menichelli
2017	J	`jnl`	Effect of NBTI/PBTI Aging and Process Variations on Write Failures in MOSFET and FinFET Flip-Flops. CoRR Usman Khalid, Antonio Mastrandrea, Mauro Olivieri
2017	—	`conf`	Investigation on the Optimal Pipeline Organization in RISC-V Multi-threaded Soft Processor Cores. NGCAS Mauro Olivieri, Abdallah Cheikh, Gianmarco Cerutti, Antonio Mastrandrea, Francesco Menichelli
2017	—	`conf`	The Microarchitecture of a Multi-threaded RISC-V Compliant Processing Core Family for IoT End-Nodes. ApplePies Abdallah Cheikh, Gianmarco Cerutti, Antonio Mastrandrea, Francesco Menichelli, Mauro Olivieri
2017	J	`jnl`	The microarchitecture of a multi-threaded RISC-V compliant processing core family for IoT end-nodes. CoRR Abdallah Cheikh, Gianmarco Cerutti, Antonio Mastrandrea, Francesco Menichelli, Mauro Olivieri
2016	—	`conf`	An Emulator for Approximate Memory Platforms Based on QEmu. ApplePies Francesco Menichelli, Giulia Stazi, Antonio Mastrandrea, Mauro Olivieri
2016	J	`jnl`	Optimal transistor sizing for maximum yield in variation-aware standard cell design. Int. J. Circuit Theory Appl. Zia Abbas, Mauro Olivieri
2015	J	`jnl`	Effect of NBTI/PBTI aging and process variations on write failures in MOSFET and FinFET flip-flops. Microelectron. Reliab. Usman Khalid, Antonio Mastrandrea, Mauro Olivieri
2015	A	`conf`	Message from the general chairs. ISLPED Luca Benini, Renu Mehra, Mauro Olivieri
2015	—	`conf`	Narrowband Delay Tolerant Protocols for WSN Applications: Characterization and Selection Guide. ApplePies Claudio Santo Malavenda, Francesco Menichelli, Mauro Olivieri
2014	—	`conf`	A Model-Based Methodology to Generate Code for Timer Units. ApplePies Marco Marazza, Francesco Menichelli, Mauro Olivieri, Orlando Ferrante, Alberto Ferrari
2014	—	`conf`	A Platform-Based Emulator for Mass-Storage Flash Cards Evaluation in Embedded Systems. ApplePies Francesco Menichelli, Mauro Olivieri
2014	J	`jnl`	A Regulation-Based Security Evaluation Method for Data Link in Wireless Sensor Network. J. Comput. Networks Commun. Claudio Santo Malavenda, Francesco Menichelli, Mauro Olivieri
2014	J	`jnl`	A Voltage-Based Leakage Current Calculation Scheme and its Application to Nanoscale MOSFET and FinFET Standard-Cell Designs. IEEE Trans. Very Large Scale Integr. Syst. Zia Abbas, Antonio Mastrandrea, Mauro Olivieri
2014	C	`conf`	Combined Impact of NBTI Aging and Process Variations on Noise Margins of Flip-Flops. DSD Usman Khalid, Antonio Mastrandrea, Mauro Olivieri
2014	J	`jnl`	Impact of technology scaling on leakage power in nano-scale bulk CMOS digital standard cells. Microelectron. J. Zia Abbas, Mauro Olivieri
2014	J	`jnl`	Logic Drivers: A Propagation Delay Modeling Paradigm for Statistical Simulation of Standard Cell Designs. IEEE Trans. Very Large Scale Integr. Syst. Mauro Olivieri, Antonio Mastrandrea
2013	J	`jnl`	A General Design Methodology for Synchronous Early-Completion-Prediction Adders in Nano-CMOS DSP Architectures. VLSI Design Mauro Olivieri, Antonio Mastrandrea
2013	—	`conf`	A flip-flop implementation for the DPA-resistant Delay-based Dual-rail Pre-charge Logic family. MIXDES Simone Bongiovanni, Mauro Olivieri, Giuseppe Scotti, Alessandro Trifiletti
2013	J	`jnl`	Design centering/yield optimization of power aware band pass filter based on CMOS current controlled current conveyor (CCCII+). Microelectron. J. Zia Abbas, Mauro Olivieri, Marat Yakupov, Andreas Ripp
2013	J	`jnl`	First integration of MOSFET band-to-band-tunneling current in BSIM4. Microelectron. J. Fabrizio Ramundo, Paolo Nenzi, Mauro Olivieri
2013	—	`conf`	Wireless and Ad Hoc Sensor Networks: An Industrial Example Using Delay Tolerant, Low Power Protocols for Security-Critical Applications. ApplePies Claudio Santo Malavenda, Francesco Menichelli, Mauro Olivieri
2012	J	`jnl`	Delay-Tolerant, Low-Power Protocols for Large Security-Critical Wireless Sensor Networks. J. Comput. Networks Commun. Claudio Santo Malavenda, Francesco Menichelli, Mauro Olivieri
2012	—	`conf`	Yield optimization for low power current controlled current conveyor. SBCCI Zia Abbas, Marat Yakupov, Mauro Olivieri, Andreas Ripp, Gunter Strube
2011	C	`conf`	Performance evaluation of Jpeg2000 implementation on VLIW cores, SIMD cores and multi-cores. ISCAS Francesco Menichelli, Mauro Olivieri, Simone Smorfa
2010	J	`jnl`	TikTak: A Scalable Simulator of Wireless Sensor Networks Including Hardware/Software Interaction. Wirel. Sens. Netw. Francesco Menichelli, Mauro Olivieri
2009	A	`conf`	Adaptive idleness distribution for non-uniform aging tolerance in MultiProcessor Systems-on-Chip. DATE Francesco Paterna, Luca Benini, Andrea Acquaviva, Francesco Papariello, Giuseppe Desoli, Mauro Olivieri
2009	J	`jnl`	Static Minimization of Total Energy Consumption in Memory Subsystem for Scratchpad-Based Systems-on-Chips. IEEE Trans. Very Large Scale Integr. Syst. Francesco Menichelli, Mauro Olivieri
2008	—	`conf`	A new dynamic differential logic style as a countermeasure to power analysis attacks. ICECS Luca Giancane, Piero Marietti, Mauro Olivieri, Giuseppe Scotti, Alessandro Trifiletti
2008	J	`jnl`	A novel high-quality YUV-based image coding technique for efficient image storage in portable electronic appliances. IEEE Trans. Consumer Electron. Roberto Mancuso, Simone Smorfa, Mauro Olivieri
2008	J	`jnl`	High-Level Side-Channel Attack Modeling and Simulation for Security-Critical Systems on Chips. IEEE Trans. Dependable Secur. Comput. Francesco Menichelli, Renato Menicocci, Mauro Olivieri, Alessandro Trifiletti
2008	—	`ch.`	LCD Design Techniques. Wiley Encyclopedia of Computer Science and Engineering Simone Smorfa, Mauro Olivieri, Roberto Mancuso
2007	J	`jnl`	A Reconfigurable, Low Power, Temperature Compensated IC for 8-segment Gamma Correction Curve in TFT, OLED and PDP Displays. IEEE Trans. Consumer Electron. Mauro Olivieri, Roberto Mancuso, Friedbert Riedel
2007	—	`conf`	A Statistical Model of Logic Gates for Monte Carlo Simulation Including On-Chip Variations. PATMOS Francesco Centurelli, Luca Giancane, Mauro Olivieri, Giuseppe Scotti, Alessandro Trifiletti
2007	J	`jnl`	Analysis and Implementation of a Novel Leading Zero Anticipation Algorithm for Floating-Point Arithmetic Units. IEEE Trans. Circuits Syst. II Express Briefs Mauro Olivieri, Francesco Pappalardo, Simone Smorfa, Giuseppe Visalli
2007	J	`jnl`	HW-SW optimisation of JPEG2000 wavelet transform for dedicated multimedia processor architectures. IET Comput. Digit. Tech. Simone Smorfa, Mauro Olivieri
2007	J	`jnl`	Testing power-analysis attack susceptibility in register-transfer level designs. IET Inf. Secur. Marco Bucci, Raimondo Luzzi, Francesco Menichelli, Renato Menicocci, Mauro Olivieri, Alessandro Trifiletti
2006	J	`jnl`	A physical-level LCD driver model and simulator with application to pixel crosstalk suppression. IEEE Trans. Consumer Electron. Simone Smorfa, Mauro Olivieri, Roberto Mancuso, Martin Lienhard
2006	C	`conf`	Side channel analysis resistant design flow. ISCAS Manfred Josef Aigner, Stefan Mangard, Francesco Menichelli, Renato Menicocci, Mauro Olivieri, Thomas Popp, Giuseppe Scotti, Alessandro Trifiletti
2005	—	`conf`	A novel CMOS logic style with data independent power consumption. ISCAS (2) Manfred Josef Aigner, Stefan Mangard, Renato Menicocci, Mauro Olivieri, Giuseppe Scotti, Alessandro Trifiletti
2005	J	`jnl`	A novel yield optimization technique for digital CMOS circuits design by means of process parameters run-time estimation and body bias active control. IEEE Trans. Very Large Scale Integr. Syst. Mauro Olivieri, Giuseppe Scotti, Alessandro Trifiletti
2005	—	`conf`	Circuit-level power efficiency investigation of advanced DSP architectures based on a specialized power modeling technique. ISCAS (5) Mauro Olivieri, Mirko Scarana, Simone Smorfa
2005	J	`jnl`	Design and Test of a Novel Programmable Clock Generator Semi-Custom Core for Energy-Efficient Systems-on-Chips. J. Low Power Electron. Mauro Olivieri, Simone Smorfa, Alessandro Trifiletti
2005	—	`conf`	Design issues for bus switch systems in deep sub-micro metric CMOS technologies. Circuits, Signals, and Systems Mauro Olivieri, Francesco Pappalardo, Giuseppe Visalli
2005	—	`conf`	Encoding circuits for low power optical on-chip communications. ISCAS (5) Mauro Olivieri, Francesco Pappalardo, Giuseppe Visalli
2005	J	`jnl`	MPARM: Exploring the Multi-Processor SoC Design Space with SystemC. J. VLSI Signal Process. Luca Benini, Davide Bertozzi, Alessandro Bogliolo, Francesco Menichelli, Mauro Olivieri
2005	—	`conf`	Software optimization of the JPEG2000 algorithm on a VLIW CPU core for system-on-chip implementation. Circuits, Signals, and Systems Francesco Menichelli, Mauro Olivieri, Simone Smorfa, Irene Zaccardini
2005	—	`conf`	statistical analysis, for reducing the energy dissipation in a bus-switch encoder. Circuits, Signals, and Systems Mauro Olivieri, Francesco Pappalardo, Giuseppe Visalli
2004	J	`jnl`	A Class of Code Compression Schemes for Reducing Power Consumption in Embedded Microprocessor Systems. IEEE Trans. Computers Luca Benini, Francesco Menichelli, Mauro Olivieri
2004	A	`conf`	A Simulation-Based Power-Aware Architecture Exploration of a Multiprocessor System-on-Chip Design. DATE Francesco Menichelli, Mauro Olivieri, Luca Benini, Monica Donno, Labros Bisdounis
2004	Misc	`conf`	A post-compiler approach to scratchpad mapping of code. CASES Federico Angiolini, Francesco Menichelli, Alberto Ferrero, Luca Benini, Mauro Olivieri
2004	J	`jnl`	Bus-switch coding for reducing power dissipation in off-chip buses. IEEE Trans. Very Large Scale Integr. Syst. Mauro Olivieri, Francesco Pappalardo, Giuseppe Visalli
2004	—	`conf`	Robust three-state PFD architecture with enhanced frequency acquisition capabilities. ISCAS (4) Francesco Centurelli, Stefano Costi, Mauro Olivieri, Salvatore Pennisi, Alessandro Trifiletti
2004	—	`conf`	Yield Optimization by Means of Process Parameters Estimation: Comparison Between ABB and ASV Techniques. PATMOS Mauro Olivieri, Mirko Scarana, Giuseppe Scotti, Alessandro Trifiletti
2003	A	`conf`	Power Efficiency of Application-Dependent Self-Configuring Pipeline Depth in DSP Microprocessors. IPDPS Mauro Olivieri, Marco Raspa
2002	J	`jnl`	Theoretical system-level limits of power dissipation reduction under a performance constraint in VLSI microprocessor design. IEEE Trans. Very Large Scale Integr. Syst. Mauro Olivieri
2001	—	`conf`	A genetic approach to the design space exploration of superscalar microprocessor architectures. ISCAS (5) Mauro Olivieri
2001	—	`conf`	An all-digital clock generator firm-core based on differential fine-tuned delay for reusable microprocessor cores. ISCAS (4) Mauro Olivieri, Alessandro Trifiletti
2001	—	`conf`	An application specific multi-port RAM cell circuit for register renaming units in high speed microprocessors. ISCAS (4) Alessandro De Gloria, Mauro Olivieri
2001	J	`jnl`	Correction to "design of synchronous and asynchronous variable-latency pipelined multipliers". IEEE Trans. Very Large Scale Integr. Syst. Mauro Olivieri
2001	J	`jnl`	Design of synchronous and asynchronous variable-latency pipelined multipliers. IEEE Trans. Very Large Scale Integr. Syst. Mauro Olivieri
2000	J	`jnl`	Semicustom Design of an IEEE 1394-Compliant Reusable IC Core. IEEE Des. Test Comput. Mauro Bertacchi, Alessandro De Gloria, Daniele Grosso, Mauro Olivieri
1999	C	`conf`	A Low-Power Microcontroller with on-Chip Self-Tuning Digital Clock-Generator for Variable-Load Applications. ICCD Mauro Olivieri, Alessandro Trifiletti, Alessandro De Gloria
1999	—	`conf`	Delay-Insensitive Synthesis of the MCS 251 Microcontroller Core for Low Power Applications. EUROMICRO Alessandro De Gloria, Paolo Palma, Mauro Olivieri
1997	J	`jnl`	Fuzzy logic microcontroller. IEEE Micro Alessandra Costa, Alessandro De Gloria, Fabrizio Giudici, Mauro Olivieri
1996	J	`jnl`	An asynchronous distributed architecture model for the Boltzmann machine control mechanism. IEEE Trans. Neural Networks Alessandro De Gloria, Mauro Olivieri
1996	J	`jnl`	Hardware design of asynchronous fuzzy controllers. IEEE Trans. Fuzzy Syst. Alessandra Costa, Alessandro De Gloria, Mauro Olivieri
1996	J	`jnl`	Statistical Carry Lookahead Adders. IEEE Trans. Computers Alessandro De Gloria, Mauro Olivieri
1995	J	`jnl`	Efficient semicustom micropipeline design. IEEE Trans. Very Large Scale Integr. Syst. Alessandro De Gloria, Mauro Olivieri
1994	B	`conf`	An evaluation system for distributed-time VHDL simulation. PADS Alessandra Costa, Alessandro De Gloria, Paolo Faraboschi, Mauro Olivieri
1994	J	`jnl`	Block placement with a Boltzmann Machine. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Alessandro De Gloria, Paolo Faraboschi, Mauro Olivieri
1993	J	`jnl`	A delay insensitive approach to the VLSI design of a DRAM controller. Microprocess. Microprogramming Alessandro De Gloria, Paolo Faraboschi, Mauro Olivieri
1993	J	`jnl`	A parallel architecture for the Color Doppler flow technique in ultrasound imaging. Microprocess. Microprogramming Alessandra Costa, Alessandro De Gloria, Paolo Faraboschi, Mauro Olivieri
1993	A*	`conf`	An analysis of dynamic scheduling techniques for symbolic applications. MICRO Alessandra Costa, Alessandro De Gloria, Paolo Faraboschi, Mauro Olivieri
1993	J	`jnl`	An asynchronous approach to the RISC design of a micro-controller. Microprocess. Microprogramming Alessandra Costa, Alessandro De Gloria, Paolo Faraboschi, Giovanni Nateri, Mauro Olivieri
1993	J	`jnl`	Clustered Boltzmann Machines: Massively Parallel Architectures for Constrained Optimization Problems. Parallel Comput. Alessandro De Gloria, Paolo Faraboschi, Mauro Olivieri
1993	J	`jnl`	Delay insensitive micro-pipelined combinational logic. Microprocess. Microprogramming Alessandro De Gloria, Paolo Faraboschi, Mauro Olivieri
1993	J	`jnl`	Design of a massively parallel SIMD architecture for the Boltzmann machine. Microprocess. Microprogramming Alessandro De Gloria, Paolo Faraboschi, Mauro Olivieri
1993	J	`jnl`	Efficient implementation of the Boltzmann machine algorithm. IEEE Trans. Neural Networks Alessandro De Gloria, Paolo Faraboschi, Mauro Olivieri
1992	A*	`conf`	A non-deterministic scheduler for a software pipelining compiler. MICRO Alessandro De Gloria, Paolo Faraboschi, Mauro Olivieri