Mauro Cesar Zanella

20 papers A 1C 2Journal 2Unranked 11
YearRankTypeTitle / Venue / Authors
2013 — ed.
Embedded Systems: Design, Analysis and Verification - 4th IFIP TC 10 International Embedded Systems Symposium, IESS 2013, Paderborn, Germany, June 17-19, 2013. Proceedings
IESS
Gunar Schirner, Marcelo Götz, Achim Rettberg, Mauro Cesar Zanella, Franz J. Rammig
2009 — ed.
Analysis, Architectures and Modelling of Embedded Systems, Third IFIP TC 10 International Embedded Systems Symposium, IESS 2009, Langenargen, Germany, September 14-16, 2009. Proceedings
IESS
Achim Rettberg, Mauro Cesar Zanella, Michael Amann, Michael Keckeisen, Franz J. Rammig
2007 — ed.
Embedded System Design: Topics, Techniques and Trends, IFIP TC10 Working Conference: International Embedded Systems Symposium (IESS), May 30 - June 1, 2007, Irvine, CA, USA
IESS
Achim Rettberg, Mauro Cesar Zanella, Rainer Dömer, Andreas Gerstlauer, Franz-Josef Rammig
2005 — ed.
From Specification to Embedded Systems Application [International Embedded Systems Symposium, IESS 2005, Manaus, Brazil, August 2005]
IESS
Achim Rettberg, Mauro Cesar Zanella, Franz J. Rammig
2004 — conf
A New High-Level Synthesis Approach of a Synchronous Bit-Serial Architecture.
MBMV
Achim Rettberg, Florian Dittmann, Thomas Lehmann, Mauro Cesar Zanella
2004 — conf
Invariants for Distributed Local Control Elements of a New Synchronous Bit-Serial Architecture.
DELTA
Florian Dittmann, Achim Rettberg, Thomas Lehmann, Mauro Cesar Zanella
2004 J jnl
Rapid prototyping of real-time control laws for complex mechatronic systems: a case study.
J. Syst. Softw.
Markus Deppe, Mauro Cesar Zanella, Michael Robrecht, Wolfram Hardt
2004 — conf
Towards a Modular Communication System for FPGAs.
DELTA
Natascha Petry Ligocki, Achim Rettberg, Mauro Cesar Zanella, Andreas Hennig, André Luiz de Freitas Francisco
2003 A conf
A Fully Self-Timed Bit-Serial Pipeline Architecture for Embedded Systems.
DATE
Achim Rettberg, Mauro Cesar Zanella, Christophe Bobda, Thomas Lehmann
2003 C conf
A New Approach of a Self-Timed Bit-Serial Synchronous Pipeline Architecture.
IEEE International Workshop on Rapid System Prototyping
Achim Rettberg, Mauro Cesar Zanella, Thomas Lehmann, Christophe Bobda
2003 — conf
Control Development for Mechatronic Systems with a Fully Reconfigurable Pipeline Architecture.
SBCCI
Achim Rettberg, Mauro Cesar Zanella, Thomas Lehmann, Ulrich Dierkes, Carsten Rustemeier
2003 — conf
Towards a High-Level Synthesis of Reconfigurable Bit-Serial Architectures.
SBCCI
Achim Rettberg, Florian Dittmann, Mauro Cesar Zanella, Thomas Lehmann
2002 — conf
Design and Realization of Distributed Real-Time Controller for Mechatronic Systems.
DIPES
Markus Deppe, Mauro Cesar Zanella
2002 — conf
Deterministic and High-Performance Communication System for the Distributed Control of Mechatronic Systems Using the IEEE1394a.
DIPES
Mauro Cesar Zanella, Thomas Lehmann, Thorsten Hestermeyer, Andreas Pottharst
2002 — conf
Modeling and Software Synthesis of Interrupt Systems.
MBMV
Thomas Lehmann, Mauro Cesar Zanella
2001 — conf
RABBIT - A Modular Rapid Prototyping Platform for Distributed Mechatronic Systems.
SBCCI
Mauro Cesar Zanella, Michael Robrecht, André Luiz de Freitas Francisco, A. Horst, Thomas Lehmann, R. Gielow
2001 C conf
Rapid Prototyping of Real-Time Control Laws for Complex Mechatronic Systems.
IEEE International Workshop on Rapid System Prototyping
Markus Deppe, Michael Robrecht, Mauro Cesar Zanella, Wolfram Hardt
2000 J jnl
Rapid-Prototyping von verteilten, hierarchischen Regelungen am Beispiel eines Fahrzeugs mit hybridem Antriebsstrang (Rapid Prototyping of Distributed Hierarchical Controllers, Applied to a Series Hybrid Drive Train).
Informationstechnik Tech. Inform.
Ralf Stolpe, Markus Deppe, Mauro Cesar Zanella
1998 — conf
A Distributed Hardware-in-the-Loop Simulation Environment in Use on a Testbed of a Series Hybrid Drive.
ESM
Ralf Stolpe, Mauro Cesar Zanella
1998 — conf
Distributed HIL-Simulation of Mechatronic Systems Applied to an Agriculture Machine.
DIPES
Mauro Cesar Zanella, Ralf Stolpe