Maurizio Zamboni

102 papers A* 1A 6B 1C 4Misc 4Journal 45Unranked 38

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	AEQUAM: Accelerating Quantum Algorithm Validation Through FPGA-Based Emulation. IEEE Access Lorenzo Lagostina, Deborah Volpe, Maurizio Zamboni, Giovanna Turvani
2025	J	`jnl`	AEQUAM: Accelerating Quantum Algorithm Validation through FPGA-Based Emulation. CoRR Lorenzo Lagostina, Deborah Volpe, Maurizio Zamboni, Giovanna Turvani
2025	J	`jnl`	DExIMA: Design Explorer for In-Memory Architectures. IEEE Access Andrea Coluccio, Alessio Naclerio, Marco Vacca, Giovanna Turvani, Mariagrazia Graziano, Maurizio Zamboni
2025	J	`jnl`	Evaluating Angle and Amplitude Encoding Strategies for Variational Quantum Machine Learning: their impact on model's accuracy. CoRR Antonio Tudisco, Andrea Marchesin, Maurizio Zamboni, Mariagrazia Graziano, Giovanna Turvani
2025	J	`jnl`	Improving the exploitability of Simulated Adiabatic Bifurcation through a flexible and open-source digital architecture. ACM Trans. Quantum Comput. Deborah Volpe, Giovanni Amedeo Cirillo, Maurizio Zamboni, Mariagrazia Graziano, Giovanna Turvani
2025	C	`conf`	Mage: a Decoupled Access-Execute CGRA tailored for Static Control Applications. ISCAS Alessio Naclerio, Fabrizio Riente, Giovanna Turvani, Marco Vacca, Maurizio Zamboni, Mariagrazia Graziano
2025	—	`conf`	Optimizing TCN Inference: A Hardware-Software Co-Design Approach with CGRA Acceleration. ISVLSI Alessandro Varaldi, Alessio Naclerio, Fabrizio Riente, Maurizio Zamboni, Mariagrazia Graziano, Marco Vacca
2024	J	`jnl`	AMARETTO: Enabling Efficient Quantum Algorithm Emulation on Low-Tier FPGAs. CoRR Christian Conti, Deborah Volpe, Mariagrazia Graziano, Maurizio Zamboni, Giovanna Turvani
2024	Misc	`conf`	Towards Quantum Circuit Emulation on Low-Tier FPGAs. QCE Christian Conti, Deborah Volpe, Giovanni Amedeo Cirillo, Mariagrazia Graziano, Maurizio Zamboni, Giovanna Turvani
2023	J	`jnl`	Integration of Simulated Quantum Annealing in Parallel Tempering and Population Annealing for Heterogeneous-Profile QUBO Exploration. IEEE Access Deborah Volpe, Giovanni Amedeo Cirillo, Maurizio Zamboni, Giovanna Turvani
2022	J	`jnl`	Engineering Grover Adaptive Search: Exploring the Degrees of Freedom for Efficient QUBO Solving. IEEE J. Emerg. Sel. Topics Circuits Syst. Luigi Giuffrida, Deborah Volpe, Giovanni Amedeo Cirillo, Maurizio Zamboni, Giovanna Turvani
2022	J	`jnl`	Hybrid-SIMD: A Modular and Reconfigurable Approach to Beyond von Neumann Computing. IEEE Trans. Computers Andrea Coluccio, Umberto Casale, Angela Guastamacchia, Giovanna Turvani, Marco Vacca, Massimo Ruo Roch, Maurizio Zamboni, Mariagrazia Graziano
2022	J	`jnl`	Towards Compact Modeling of Noisy Quantum Computers: A Molecular-Spin-Qubit Case of Study. ACM J. Emerg. Technol. Comput. Syst. Mario Simoni, Giovanni Amedeo Cirillo, Giovanna Turvani, Mariagrazia Graziano, Maurizio Zamboni
2021	—	`conf`	Octantis: An Exploration Tool for Beyond von Neumann architectures. DTIS Andrea Marchesin, Giovanna Turvani, Andrea Coluccio, Fabrizio Riente, Marco Vacca, Massimo Ruo Roch, Mariagrazia Graziano, Maurizio Zamboni
2020	J	`jnl`	Data Processing and Information Classification - An In-Memory Approach. Sensors Milena Andrighetti, Giovanna Turvani, Giulia Santoro, Marco Vacca, Andrea Marchesin, Fabrizio Ottati, Massimo Ruo Roch, Mariagrazia Graziano, Maurizio Zamboni
2019	—	`conf`	Bitmap Index: A Processing-in-Memory Reconfigurable Implementation. ApplePies Milena Andrighetti, Giovanna Turvani, Giulia Santoro, Marco Vacca, Massimo Ruo Roch, Maurizio Graziano, Maurizio Zamboni
2019	—	`conf`	WINNER: a high speed high energy efficient Neural Network implementation for image classification. ICECS Simone Domenico Antonietta, Andrea Coluccio, Giovanna Turvani, Marco Vacca, Mariagrazia Graziano, Maurizio Zamboni
2018	J	`jnl`	Exploration of multilayer field-coupled nanomagnetic circuits. Microelectron. J. Giulia Santoro, Marco Vacca, Matteo Bollo, Fabrizio Riente, Mariagrazia Graziano, Maurizio Zamboni
2017	J	`jnl`	Domain Wall Interconnections for NML. IEEE Trans. Very Large Scale Integr. Syst. Fabrizio Cairo, Marco Vacca, Giovanna Turvani, Maurizio Zamboni, Mariagrazia Graziano
2017	J	`jnl`	Efficient and reliable fault analysis methodology for nanomagnetic circuits. Int. J. Circuit Theory Appl. Giovanna Turvani, Fabrizio Riente, Fabrizio Cairo, Marco Vacca, Umberto Garlando, Maurizio Zamboni, Mariagrazia Graziano
2017	—	`conf`	NANOcom: A Mosaic Approach for nanoelectronic circuits design. DTIS Matteo Bollo, Giulia Santoro, Umberto Garlando, Maurizio Zamboni
2017	J	`jnl`	ToPoliNano: A CAD Tool for Nano Magnetic Logic. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Fabrizio Riente, Giovanna Turvani, Marco Vacca, Massimo Ruo Roch, Maurizio Zamboni, Mariagrazia Graziano
2016	—	`conf`	A Reconfigurable Array Architecture for NML. ISVLSI Giovanni Causapruno, Umberto Garlando, Fabrizio Cairo, Maurizio Zamboni, Mariagrazia Graziano
2016	J	`jnl`	Reconfigurable Systolic Array: From Architecture to Physical Design for NML. IEEE Trans. Very Large Scale Integr. Syst. Giovanni Causapruno, Fabrizio Riente, Giovanna Turvani, Marco Vacca, Massimo Ruo Roch, Maurizio Zamboni, Mariagrazia Graziano
2015	J	`jnl`	Feedbacks in QCA: A Quantitative Approach. IEEE Trans. Very Large Scale Integr. Syst. Marco Vacca, Juanchi Wang, Mariagrazia Graziano, Massimo Ruo Roch, Maurizio Zamboni
2015	J	`jnl`	Interleaving in Systolic-Arrays: A Throughput Breakthrough. IEEE Trans. Computers Giovanni Causapruno, Marco Vacca, Mariagrazia Graziano, Maurizio Zamboni
2015	C	`conf`	Logic-in-Memory architecture made real. ISCAS D. Pala, Giovanni Causapruno, Marco Vacca, Fabrizio Riente, Giovanna Turvani, Mariagrazia Graziano, Maurizio Zamboni
2015	—	`conf`	Logic-in-Memory: A Nano Magnet Logic Implementation. ISVLSI Mario Cofano, Giulia Santoro, Marco Vacca, D. Pala, Giovanni Causapruno, Fabrizio Cairo, Fabrizio Riente, Giovanna Turvani, Massimo Ruo Roch, Mariagrazia Graziano, Maurizio Zamboni
2015	J	`jnl`	Protein Alignment Systolic Array Throughput Optimization. IEEE Trans. Very Large Scale Integr. Syst. Giovanni Causapruno, Gianvito Urgese, Marco Vacca, Mariagrazia Graziano, Maurizio Zamboni
2014	J	`jnl`	A Joint Source/Channel Approach to Strengthen Embedded Programmable Devices against Flash Memory Errors. IEEE Embed. Syst. Lett. Maurizio Martina, Carlo Condo, Guido Masera, Maurizio Zamboni
2014	—	`conf`	A standard cell approach for MagnetoElastic NML circuits. NANOARCH Davide Giri, Marco Vacca, Giovanni Causapruno, Wenjing Rao, Mariagrazia Graziano, Maurizio Zamboni
2014	—	`conf`	Dynamic Gap Selector: A Smith Waterman Sequence Alignment Algorithm with Affine Gap Model Optimization. IWBBIO Gianvito Urgese, Giulia Paciello, Andrea Acquaviva, Elisa Ficarra, Mariagrazia Graziano, Maurizio Zamboni
2014	—	`ch.`	Electric Clock for NanoMagnet Logic Circuits. Field-Coupled Nanocomputing Marco Vacca, Mariagrazia Graziano, Alessandro Chiolerio, Andrea Lamberti, Marco Laurenti, Davide Balma, Emanuele Enrico, Federica Celegato, Paola Tiberto, Luca Boarino, Maurizio Zamboni
2014	J	`jnl`	Enabling design and simulation of massive parallel nanoarchitectures. J. Parallel Distributed Comput. Stefano Frache, Diego Chiabrando, Mariagrazia Graziano, Marco Vacca, Luca Boarino, Maurizio Zamboni
2014	Misc	`conf`	Fault tolerant nanoarray circuits: Automatic design and verification. VTS Pasquale Ranone, Giovanna Turvani, Fabrizio Riente, Mariagrazia Graziano, Massimo Ruo Roch, Maurizio Zamboni
2014	—	`ch.`	NanoMagnet Logic: An Architectural Level Overview. Field-Coupled Nanocomputing Marco Vacca, Mariagrazia Graziano, Juanchi Wang, Fabrizio Cairo, Giovanni Causapruno, Gianvito Urgese, Andrea Biroli, Maurizio Zamboni
2014	J	`jnl`	Nanoarray architectures multilevel simulation. ACM J. Emerg. Technol. Comput. Syst. Stefano Frache, Mariagrazia Graziano, Maurizio Zamboni
2014	—	`conf`	Physical design and testing of Nano Magnetic architectures. DTIS Giovanna Turvani, A. Tohti, Matteo Bollo, Fabrizio Riente, Marco Vacca, Mariagrazia Graziano, Maurizio Zamboni
2014	J	`jnl`	Simulation and design of an UWB imaging system for breast cancer detection. Integr. Xiaolu Guo, Mario R. Casu, Mariagrazia Graziano, Maurizio Zamboni
2014	—	`ch.`	ToPoliNano: NanoMagnet Logic Circuits Design and Simulation. Field-Coupled Nanocomputing Marco Vacca, Stefano Frache, Mariagrazia Graziano, Fabrizio Riente, Giovanna Turvani, Massimo Ruo Roch, Maurizio Zamboni
2014	J	`jnl`	UWB microwave imaging for breast cancer detection: Many-core, GPU, or FPGA? ACM Trans. Embed. Comput. Syst. Mario R. Casu, Francesco Colonna, Marco Crepaldi, Danilo Demarchi, Mariagrazia Graziano, Maurizio Zamboni
2013	J	`jnl`	A Hardware Viewpoint on Biosequence Analysis: What's Next? ACM J. Emerg. Technol. Comput. Syst. Mariagrazia Graziano, Stefano Frache, Maurizio Zamboni
2013	—	`conf`	Automatic Place&Route of Nano-magnetic Logic circuits. NANOARCH Marco Vacca, Stefano Frache, Mariagrazia Graziano, L. Di Crescenzo, Fabrizio Cairo, Maurizio Zamboni
2013	—	`conf`	Biosequences analysis on NanoMagnet Logic. ICICDT Juanchi Wang, Marco Vacca, Mariagrazia Graziano, Massimo Ruo Roch, Maurizio Zamboni
2013	—	`conf`	Breast cancer detection based on an UWB imaging system: Receiver design and simulations. ICICDT Xiaolu Guo, Mario R. Casu, Mariagrazia Graziano, Maurizio Zamboni
2013	J	`jnl`	Hardware Acceleration of Beamforming in a UWB Imaging Unit for Breast Cancer Detection. VLSI Design Francesco Colonna, Mariagrazia Graziano, Mario Roberto Casu, Xiaolu Guo, Maurizio Zamboni
2013	J	`jnl`	LAURA-NoC: Local Automatic Rate Adjustment in Network-on-Chips With a Simple DVFS. IEEE Trans. Circuits Syst. II Express Briefs Manoj Kumar Yadav, Mario R. Casu, Maurizio Zamboni
2013	J	`jnl`	Nanomagnetic Logic Microprocessor: Hierarchical Power Model. IEEE Trans. Very Large Scale Integr. Syst. Marco Vacca, Mariagrazia Graziano, Maurizio Zamboni
2013	—	`conf`	On the functional test of the BTB logic in pipelined and superscalar processors. LATW D. Changdao, Mariagrazia Graziano, Ernesto Sánchez, Matteo Sonza Reorda, Maurizio Zamboni, N. Zhifan
2013	—	`conf`	UWB receiver for breast cancer detection: Comparison between two different approaches. SoCC Xiaolu Guo, Mario R. Casu, Mariagrazia Graziano, Maurizio Zamboni
2012	—	`conf`	DVFS Based on Voltage Dithering and Clock Scheduling for GALS Systems. ASYNC Manoj Kumar Yadav, Mario R. Casu, Maurizio Zamboni
2012	—	`conf`	Protein alignment HW/SW optimizations. ICECS Gianvito Urgese, Mariagrazia Graziano, Marco Vacca, Muhammad Awais, Stefano Frache, Maurizio Zamboni
2012	—	`conf`	ToPoliNano: nanoarchitectures design made real. NANOARCH Stefano Frache, Diego Chiabrando, Mariagrazia Graziano, Fabrizio Riente, Giovanna Turvani, Maurizio Zamboni
2011	J	`jnl`	A NoC-based hybrid message-passing/shared-memory approach to CMP design. Microprocess. Microsystems Mario R. Casu, Massimo Ruo Roch, Sergio Tota, Maurizio Zamboni
2011	J	`jnl`	Asynchronous Solutions for Nanomagnetic Logic Circuits. ACM J. Emerg. Technol. Comput. Syst. Marco Vacca, Mariagrazia Graziano, Maurizio Zamboni
2011	J	`jnl`	Asynchrony in Quantum-Dot Cellular Automata Nanocomputation: Elixir or Poison? IEEE Des. Test Comput. Mariagrazia Graziano, Marco Vacca, Davide Blua, Maurizio Zamboni
2011	—	`conf`	Nanofabric power analysis: Biosequence alignment case study. NANOARCH Stefano Frache, Luca Gaetano Amarù, Mariagrazia Graziano, Maurizio Zamboni
2010	C	`conf`	A flexible simulation methodology and tool for nanoarray-based architectures. ICCD Stefano Frache, Mariagrazia Graziano, Maurizio Zamboni
2010	A	`conf`	MEDEA: a hybrid shared-memory/message-passing multiprocessor NoC-based architecture. DATE Sergio Tota, Mario R. Casu, Massimo Ruo Roch, Luca Rostagno, Maurizio Zamboni
2009	J	`jnl`	A Case Study for NoC-Based Homogeneous MPSoC Architectures. IEEE Trans. Very Large Scale Integr. Syst. Sergio Tota, Mario R. Casu, Massimo Ruo Roch, Luca Macchiarulo, Maurizio Zamboni
2009	J	`jnl`	A Fully Differential Digital CMOS UWB Pulse Generator. Circuits Syst. Signal Process. Mario R. Casu, Mariagrazia Graziano, Maurizio Zamboni
2009	J	`jnl`	A mixed-signal demodulator for a low-complexity IR-UWB receiver: Methodology, simulation and design. Integr. Marco Crepaldi, Mario R. Casu, Mariagrazia Graziano, Maurizio Zamboni
2007	—	`conf`	A methodology and a case-study for network-on-chip based MP-SoC architectures. Nano-Net Sergio Tota, Mario R. Casu, Paolo Motto Ros, Massimo Ruo Roch, Maurizio Zamboni
2007	A	`conf`	An effective AMS top-down methodology applied to the design of a mixed-signal UWB system-on-chip. DATE Marco Crepaldi, Mario R. Casu, Mariagrazia Graziano, Maurizio Zamboni
2007	—	`conf`	The NoCRay Graphic Accelerator: a Case-study for MP-SoC Network-on-Chip Design Methodology. SoC Sergio Tota, Mario R. Casu, Paolo Motto Ros, Massimo Ruo Roch, Maurizio Zamboni
2004	J	`jnl`	An electromigration and thermal model of power wires for a priori high-level reliability prediction. IEEE Trans. Very Large Scale Integr. Syst. Mario R. Casu, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni
2004	J	`jnl`	Effects of temperature in deep-submicron global interconnect optimization in future technology nodes. Microelectron. J. Mariagrazia Graziano, Mario R. Casu, Guido Masera, Gianluca Piccinini, Maurizio Zamboni
2003	—	`conf`	A Block-Based Approach for SoC Global Interconnect Electrical Parameters Characterization. PATMOS M. Addino, Mario R. Casu, Guido Masera, Gianluca Piccinini, Maurizio Zamboni
2003	J	`jnl`	Coupled electro-thermal modeling and optimization of clock networks. Microelectron. J. Mario R. Casu, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni
2003	—	`conf`	Effects of Temperature in Deep-Submicron Global Interconnect Optimization. PATMOS Mario R. Casu, Mariagrazia Graziano, Gianluca Piccinini, Guido Masera, Maurizio Zamboni
2003	J	`jnl`	Novel JPEG 2000 Compliant DWT and IWT VLSI Implementations. J. VLSI Signal Process. Maurizio Martina, Guido Masera, Gianluca Piccinini, Maurizio Zamboni
2003	A	`conf`	Wireless sensor networks: a power-scalable motion estimation IP for hybrid video coding. FPGA Federico Quaglio, Maurizio Martina, Fabrizio Vacca, Guido Masera, Andrea Molino, Gianluca Piccinini, Maurizio Zamboni
2002	J	`jnl`	Architectural strategies for low-power VLSI turbo decoders. IEEE Trans. Very Large Scale Integr. Syst. Guido Masera, Marco Mazza, Gianluca Piccinini, Fabrizio Viglione, Maurizio Zamboni
2002	—	`conf`	Clock Distribution Network Optimization under Self-Heating and Timing Constraints. PATMOS Mario R. Casu, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, M. M. Prono, Maurizio Zamboni
2002	—	`conf`	Embedded IWT evaluation in reconfigurable wireless sensor network. ICECS Maurizio Martina, Guido Masera, Gianluca Piccinini, Fabrizio Vacca, Maurizio Zamboni
2002	B	`conf`	Energy Evaluation on a Reconfigurable, Multimedia-Oriented Wireless Sensor. FPL Maurizio Martina, Guido Masera, Gianluca Piccinini, Fabrizio Vacca, Maurizio Zamboni
2002	Misc	`conf`	Reconfigurable DSP IP for multimedia applications. ICASSP Maurizio Martina, Guido Masera, Gianluca Piccinini, Fabrizio Vacca, Maurizio Zamboni
2002	—	`conf`	System architecture for error-resilient, embedded JPEG2000 wireless delivery. DSP Maurizio Martina, Guido Masera, Gianluca Piccinini, Fabrizio Vacca, Maurizio Zamboni
2001	—	`conf`	Hierarchical power supply noise evaluation for early power grid design prediction. SLIP Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni
2001	—	`conf`	JPEG 2000: finite precision representation and hardware implications. ICECS Maurizio Martina, Guido Masera, Gianluca Piccinini, Fabrizio Vacca, Maurizio Zamboni
2001	—	`conf`	Reconfigurable coprocessor based JPEG 2000 implementation. ICECS Maurizio Martina, Guido Masera, Gianluca Piccinini, Fabrizio Vacca, Maurizio Zamboni
2001	Misc	`conf`	Switching Noise Analysis Framework For High Speed Logic Families. VLSI Design Marco Delaurenti, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni
2001	A	`conf`	Synthesis of low-leakage PD-SOI circuits with body-biasing. ISLPED Mario R. Casu, Gianluca Piccinini, Guido Masera, Maurizio Zamboni
2000	A	`conf`	A 50 Mbit/s Iterative Turbo-Decoder. DATE Fabrizio Viglione, Guido Masera, Gianluca Piccinini, Massimo Ruo Roch, Maurizio Zamboni
2000	C	`conf`	A high accuracy-low complexity model for CMOS delays. ISCAS Mario Roberto Casu, Guido Masera, Gianluca Piccinini, Massimo Ruo Roch, Maurizio Zamboni
2000	—	`conf`	Noise Safety Design Methodologies. ISQED Mariagrazia Graziano, Marco Delaurenti, Guido Masera, Gianluca Piccinini, Maurizio Zamboni
2000	—	`conf`	Power supply design parameters prediction for high performance IC design flows. SLIP Mariagrazia Graziano, Marco Delaurenti, Maurizio Zamboni
1999	—	`conf`	A Quantitative Approach to the Design of an Optimized Hardware Interpreter for Java Byte-Code. Applied Informatics Guido Masera, Gianluca Piccinini, Massimo Ruo Roch, Maurizio Zamboni
1999	—	`conf`	A global optimization tool for CMOS logic circuits. ICECS Marco Delaurenti, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni
1999	—	`conf`	New 2 Gbit/s CMOS I/O pads. Great Lakes Symposium on VLSI Guido Masera, Gianluca Piccinini, Massimo Ruo Roch, Maurizio Zamboni
1999	J	`jnl`	VLSI architectures for turbo codes. IEEE Trans. Very Large Scale Integr. Syst. Guido Masera, Gianluca Piccinini, Massimo Ruo Roch, Maurizio Zamboni
1998	—	`conf`	A 500 MHz 2d-DWT VLSI processor. EUSIPCO A. Brizio, Guido Masera, Gianluca Piccinini, Massimo Ruo Roch, Maurizio Zamboni
1998	—	`conf`	A receiver architecture conforming to the OFDM based digital video broadcasting standard for terrestrial transmission (DVB-T). ICC Pierre Combelles, Christophe Del Toso, Dietmar Hepper, David Le Goff, J. J. Ma, Patrick Robertson, Fabio Scalise, Laurent Soyer, Maurizio Zamboni
1998	A	`conf`	Fanout optimization under a submicron transistor-level delay model. ICCAD Pasquale Cocchini, Massoud Pedram, Gianluca Piccinini, Maurizio Zamboni
1997	J	`jnl`	A comprehensive submicrometer MOST delay model and its application to CMOS buffers. IEEE J. Solid State Circuits Pasquale Cocchini, Gianluca Piccinini, Maurizio Zamboni
1996	—	`conf`	A 650 MHz pipelined MAC for DSP applications using a new clocking strategy. EUSIPCO F. Fraternali, Guido Masera, Gianluca Piccinini, Maurizio Zamboni
1995	—	`conf`	Input and output processor for an ATM high speed switch (2.5 Gb/s): the CMC. ED&TC Pierre Plaza, Juan Carlos Diaz, Fermín Calvo, Luis A. Merayo, Maurizio Zamboni, Pietro Scarfone, Marco Barbini
1993	J	`jnl`	PROXIMA: PROlog eXecutIon MAchine. IEEE J. Solid State Circuits Livio Baldi, Pierluigi Civera, Angela Iurlaro, Guido Masera, Andrea Pagni, Gianluca Piccinini, Rinaldo Poluzzi, Massimo Ruo Roch, Maurizio Zamboni
1992	J	`jnl`	Deflection network: Principles, implementation, services. Eur. Trans. Telecommun. Guido Albertengo, Pierluigi Civera, Renato Lo Cigno, Gianluca Piccinini, Maurizio Zamboni, Flaminio Borgonovo, Luigi Fratta, Giuseppe Panizzardi
1989	J	`jnl`	Implementation studies for a VLSI Prolog coprocessor. IEEE Micro Pierluigi Civera, Gianluca Piccinini, Maurizio Zamboni
1987	A*	`conf`	An Experimental VLSI Prolog Interpreter: Preliminary Measurements and Results. ISCA Pierluigi Civera, Franco Maddaleno, Gianluca Piccinini, Maurizio Zamboni
1987	J	`jnl`	Design considerations on a VLSI Prolog interpreter. Microprocess. Microprogramming Pierluigi Civera, Gianluca Piccinini, Maurizio Zamboni