Maurizio Palesi

207 papers A* 2A 10B 6C 23Misc 4Journal 93Unranked 58

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Assessing the Role of Communication in Modular Multi-Core Quantum Systems. ACM Trans. Design Autom. Electr. Syst. Maurizio Palesi, Enrico Russo, Giuseppe Ascia, Hamaad Rafique, Davide Patti, Vincenzo Catania, Sergi Abadal, Abhijit Das, Pau Escofet, Eduard Alarcón, Carmen G. Almudéver
2026	J	`jnl`	CHAOS: Controlled Hardware fAult injectOr System for gem5. CoRR Elio Vinciguerra, Enrico Russo, Giuseppe Ascia, Maurizio Palesi
2026	J	`jnl`	Thermal-Aware NoC for AI Computing: Tools, Algorithms, and Applications. IEEE Open J. Circuits Syst. Fakhrul Zaman Rokhani, Mircea R. Stan, Maurizio Palesi, Kun-Chih Chen
2026	J	`jnl`	Timechain-level modeling and analysis of the bitcoin lightning network. Comput. Networks Davide Patti, Salvatore Monteleone, Enrico Russo, Maurizio Palesi
2025	J	`jnl`	A Characteristics-Based Least Common Multiple Algorithm to Optimize Magnetic-Field-Based Indoor Localization. IEEE Internet Things J. Hamaad Rafique, Davide Patti, Maurizio Palesi, Gaetano Carmelo La Delfa
2025	—	`conf`	A Data-Driven Approach to Dataflow-Aware Online Scheduling for Graph Neural Network Inference. ASP-DAC Pol Puigdemont, Enrico Russo, Axel Wassington, Abhijit Das, Sergi Abadal, Maurizio Palesi
2025	J	`jnl`	A Survey on Deep Learning Hardware Accelerators for Heterogeneous HPC Platforms. ACM Comput. Surv. Cristina Silvano, Daniele Ielmini, Fabrizio Ferrandi, Leandro Fiorin, Serena Curzel, Luca Benini, Francesco Conti, Angelo Garofalo, Cristian Zambelli, Enrico Calore, Sebastiano Fabio Schifano, Maurizio Palesi, Giuseppe Ascia, Davide Patti, Nicola Petra, Davide De Caro, Luciano Lavagno, Teodoro Urso, Valeria Cardellini, Gian Carlo Cardarilli, Robert Birke, Stefania Perri
2025	C	`conf`	An Anomaly Detection Model for RISC-V in Automotive Applications: A Domain-Specific Accelerator Perspective. PDP Elio Vinciguerra, Enrico Russo, Maurizio Palesi, Giuseppe Ascia
2025	J	`jnl`	Assessing the Role of Communication in Modular Multi-Core Quantum Systems. CoRR Maurizio Palesi, Enrico Russo, Giuseppe Ascia, Hamaad Rafique, Davide Patti, Vincenzo Catania, Sergi Abadal, Abhijit Das, Pau Escofet, Eduard Alarcón, Carmen G. Almudéver
2025	—	`conf`	Decentralized Framework for Teleportation in Quantum Core Interconnects. ISVLSI P. S. Rajeswari Suance, Ruchika Gupta, Maurizio Palesi, John Jose
2025	—	`conf`	Improving Machine Learning Anomaly Detection for Safety-Critical RISC-V Automotive Systems. CPS Summer School, PhD Workshop Elio Vinciguerra, Maurizio Palesi, Giuseppe Ascia
2025	J	`jnl`	Indoor localization by projecting magnetic field signals onto images with vision transformer. Comput. Electr. Eng. Hamaad Rafique, Davide Patti, Maurizio Palesi, Gaetano Carmelo La Delfa
2025	—	`conf`	Instruction-Directed MAC for Efficient Classical Communication in Scalable Multi-Chip Quantum Systems. MCSoC Maurizio Palesi, Enrico Russo, Hamaad Rafique, Giuseppe Ascia, Davide Patti, Abhijit Das, Sergi Abadal
2025	J	`jnl`	Lattice Surgery Aware Resource Analysis for the Mapping and Scheduling of Quantum Circuits for Scalable Modular Architectures. CoRR Batuhan Keskin, Cameron Afradi, Sylvain Lovis, Maurizio Palesi, Pau Escofet, Carmen G. Almudéver, Edoardo Charbon
2025	A	`conf`	Optimizing Qubit Assignment in Modular Quantum Systems via Attention-Based Deep Reinforcement Learning. DATE Enrico Russo, Maurizio Palesi, Davide Patti, Giuseppe Ascia, Vincenzo Catania
2025	J	`jnl`	Survey of smartphone-based datasets for indoor localization: A machine learning perspective. Internet Things Gaetano Carmelo La Delfa, Javier Prieto, Salvatore Monteleone, Hamaad Rafique, Maurizio Palesi, Davide Patti
2024	J	`jnl`	A Data-Driven Approach to Dataflow-Aware Online Scheduling for Graph Neural Network Inference. CoRR Pol Puigdemont, Enrico Russo, Axel Wassington, Abhijit Das, Sergi Abadal, Maurizio Palesi
2024	A*	`conf`	A Deep Reinforcement Learning based Online Scheduling Policy for Deep Neural Network Multi-Tenant Multi-Accelerator Systems. DAC Francesco Giulio Blanco, Enrico Russo, Maurizio Palesi, Davide Patti, Giuseppe Ascia, Vincenzo Catania
2024	—	`conf`	A Novel Timechain-Level Approach to the Modeling of the Bitcoin Lightning Network. Blockchain Davide Patti, Salvatore Monteleone, Enrico Russo, Maurizio Palesi, Vincenzo Catania
2024	C	`conf`	Abstracting Bitcoin Lightning Network Complexity with Ultraviolet. ICBC Davide Patti, Salvatore Monteleone, Enrico Russo, Maurizio Palesi, Vincenzo Catania
2024	—	`conf`	Assessing the Role of Communication in Scalable Multi-Core Quantum Architectures. MCSoC Maurizio Palesi, Enrico Russo, Davide Patti, Giuseppe Ascia, Vincenzo Catania
2024	J	`jnl`	Attention-Based Deep Reinforcement Learning for Qubit Allocation in Modular Quantum Architectures. CoRR Enrico Russo, Maurizio Palesi, Davide Patti, Giuseppe Ascia, Vincenzo Catania
2024	C	`conf`	Characteristics-Based Least Common Multiple: A Novel Clustering Algorithm to Optimize Indoor Positioning. ICINCO (1) Hamaad Rafique, Davide Patti, Maurizio Palesi, Gaetano Carmelo La Delfa
2024	J	`jnl`	Chip and Package-Scale Interconnects for General-Purpose, Domain-Specific, and Quantum Computing Systems - Overview, Challenges, and Opportunities. IEEE J. Emerg. Sel. Topics Circuits Syst. Abhijit Das, Maurizio Palesi, John Kim, Partha Pratim Pande
2024	J	`jnl`	Correction to: The position-based compression techniques for DNN model. J. Supercomput. Minghua Tang, Enrico Russo, Maurizio Palesi
2024	—	`conf`	Data-Driven Simulation Based Fault Detection in Automotive RISC-V Applications. MCSoC Elio Vinciguerra, Enrico Russo, Maurizio Palesi, Giuseppe Ascia
2024	J	`jnl`	Deep Reinforcement Learning based Online Scheduling Policy for Deep Neural Network Multi-Tenant Multi-Accelerator Systems. CoRR Francesco Giulio Blanco, Enrico Russo, Maurizio Palesi, Davide Patti, Giuseppe Ascia, Vincenzo Catania
2024	C	`conf`	Fusing Visuals with Magnetic Signals to Improve Indoor Localization Using Vision Transformer. IPIN Hamaad Rafique, Davide Patti, Maurizio Palesi, Gaetano Carmelo La Delfa
2024	J	`jnl`	Guest Editorial Chip and Package-Scale Communication-Aware Architectures for General-Purpose, Domain-Specific, and Quantum Computing Systems. IEEE J. Emerg. Sel. Topics Circuits Syst. Abhijit Das, Maurizio Palesi, John Kim, Partha Pratim Pande
2024	—	`conf`	Improving LSTM-based Indoor Positioning via Simulation-Augmented Geomagnetic Field Dataset. MOST Elio Vinciguerra, Enrico Russo, Maurizio Palesi, Giuseppe Ascia, Hamaad Rafique
2024	—	`conf`	Lessons Learned on the Design of Cost-Effective and Highly Compatible Smart Gloves. MECO Marco Finocchiaro, Salvatore Monteleone, Enrico Russo, Maurizio Palesi, Davide Patti
2024	J	`jnl`	Multi-Objective Hardware-Mapping Co-Optimisation for Multi-DNN Workloads on Chiplet-Based Accelerators. IEEE Trans. Computers Abhijit Das, Enrico Russo, Maurizio Palesi
2024	C	`conf`	Towards Fair and Firm Real-Time Scheduling in DNN Multi-Tenant Multi-Accelerator Systems via Reinforcement Learning. ISCAS Enrico Russo, Francesco Giulio Blanco, Maurizio Palesi, Giuseppe Ascia, Davide Patti, Vincenzo Catania
2024	J	`jnl`	Towards Fair and Firm Real-Time Scheduling in DNN Multi-Tenant Multi-Accelerator Systems via Reinforcement Learning. CoRR Enrico Russo, Francesco Giulio Blanco, Maurizio Palesi, Giuseppe Ascia, Davide Patti, Vincenzo Catania
2023	J	`jnl`	A Survey on Deep Learning Hardware Accelerators for Heterogeneous HPC Platforms. CoRR Cristina Silvano, Daniele Ielmini, Fabrizio Ferrandi, Leandro Fiorin, Serena Curzel, Luca Benini, Francesco Conti, Angelo Garofalo, Cristian Zambelli, Enrico Calore, Sebastiano Fabio Schifano, Maurizio Palesi, Giuseppe Ascia, Davide Patti, Stefania Perri, Nicola Petra, Davide De Caro, Luciano Lavagno, Teodoro Urso, Valeria Cardellini, Gian Carlo Cardarilli, Robert Birke
2023	J	`jnl`	A Survey on Design Methodologies for Accelerating Deep Learning on Heterogeneous Architectures. CoRR Fabrizio Ferrandi, Serena Curzel, Leandro Fiorin, Daniele Ielmini, Cristina Silvano, Francesco Conti, Alessio Burrello, Francesco Barchi, Luca Benini, Luciano Lavagno, Teodoro Urso, Enrico Calore, Sebastiano Fabio Schifano, Cristian Zambelli, Maurizio Palesi, Giuseppe Ascia, Enrico Russo, Nicola Petra, Davide De Caro, Gennaro Di Meo, Valeria Cardellini, Salvatore Filippone, Francesco Lo Presti, Francesco Silvestri, Paolo Palazzari, Stefania Perri
2023	J	`jnl`	EXplainable AI for Decision Support to Obesity Comorbidities Diagnosis. IEEE Access Grazia Veronica Aiosa, Maurizio Palesi, Francesca Sapuppo
2023	B	`conf`	Explainable AI-Based Clinical Decision Support System for Obesity Comorbidity Analysis. e-Science Grazia Veronica Aiosa, Maurizio Palesi, Francesca Sapuppo, Maria Gabriella Xibilia
2023	—	`conf`	Memory-Aware DNN Algorithm-Hardware Mapping via Integer Linear Programming. CF Enrico Russo, Maurizio Palesi, Giuseppe Ascia, Davide Patti, Salvatore Monteleone, Vincenzo Catania
2023	J	`jnl`	Multiobjective End-to-End Design Space Exploration of Parameterized DNN Accelerators. IEEE Internet Things J. Enrico Russo, Maurizio Palesi, Davide Patti, Salvatore Monteleone, Giuseppe Ascia, Vincenzo Catania
2023	C	`conf`	Scalable multi-chip quantum architectures enabled by cryogenic hybrid wireless/quantum-coherent network-in-package. ISCAS Eduard Alarcón, Sergi Abadal, Fabio Sebastiano, Masoud Babaie, Edoardo Charbon, Peter Haring Bolívar, Maurizio Palesi, Elena Blokhina, Dirk Leipold, Robert Bogdan Staszewski, Artur García-Sáez, Carmen G. Almudéver
2023	J	`jnl`	Scalable multi-chip quantum architectures enabled by cryogenic hybrid wireless/quantum-coherent network-in-package. CoRR Eduard Alarcón, Sergi Abadal, Fabio Sebastiano, Masoud Babaie, Edoardo Charbon, Peter Haring Bolívar, Maurizio Palesi, Elena Blokhina, Dirk Leipold, Robert Bogdan Staszewski, Artur García-Sáez, Carmen G. Almudéver
2023	J	`jnl`	The position-based compression techniques for DNN model. J. Supercomput. Minghua Tang, Enrico Russo, Maurizio Palesi
2023	—	`conf`	Wireless enabled Inter-Chiplet Communication in DNN Hardware Accelerators. IPDPS Workshops Maurizio Palesi, Enrico Russo, Abhijit Das, John Jose
2023	—	`conf`	m-BMC: Exploration of Magnetic Field Measurements for Indoor Positioning Using mini-Batch Magnetometer Calibration. MOST Hamaad Rafique, Davide Patti, Maurizio Palesi, Vincenzo Catania
2022	—	`conf`	Analyzing the Impact of DNN Hardware Accelerators-Oriented Compression Techniques on General-Purpose Low-End Boards. MobiWIS Giuliano Canzonieri, Salvatore Monteleone, Maurizio Palesi, Enrico Russo, Davide Patti
2022	—	`conf`	Combined Application of Approximate Computing Techniques in DNN Hardware Accelerators. IPDPS Workshops Enrico Russo, Maurizio Palesi, Davide Patti, Habiba Lahdhiri, Salvatore Monteleone, Giuseppe Ascia, Vincenzo Catania
2022	J	`jnl`	DNN Model Compression for IoT Domain-Specific Hardware Accelerators. IEEE Internet Things J. Enrico Russo, Maurizio Palesi, Salvatore Monteleone, Davide Patti, Andrea Mineo, Giuseppe Ascia, Vincenzo Catania
2022	J	`jnl`	Design Challenges of Intrachiplet and Interchiplet Interconnection. IEEE Des. Test Chixiao Chen, Jieming Yin, Yarui Peng, Maurizio Palesi, Wenxu Cao, Letian Huang, Amit Kumar Singh, Haocong Zhi, Xiaohang Wang
2022	—	`conf`	Exploiting the Approximate Computing Paradigm with DNN Hardware Accelerators. MECO Enrico Russo, Maurizio Palesi, Salvatore Monteleone, Davide Patti, Habiba Lahdhiri, Giuseppe Ascia, Vincenzo Catania
2022	A	`conf`	MEDEA: A Multi-objective Evolutionary Approach to DNN Hardware Mapping. DATE Enrico Russo, Maurizio Palesi, Salvatore Monteleone, Davide Patti, Giuseppe Ascia, Vincenzo Catania
2022	J	`jnl`	Multi-Objective Hardware-Mapping Co-Optimisation for Multi-Tenant DNN Accelerators. CoRR Abhijit Das, Enrico Russo, Maurizio Palesi
2022	J	`jnl`	Revising NoC in Future Multicore-Based Consumer Electronics for Performance. IEEE Consumer Electron. Mag. Abhijit Das, Abhishek Kumar, John Jose, Maurizio Palesi
2021	—	`conf`	A Methodology for Simulating Multi-chiplet Systems Using Open-source Simulators. NANOCOM Haocong Zhi, Xianuo Xu, Weijian Han, Zhilin Gao, Xiaohang Wang, Maurizio Palesi, Amit Kumar Singh, Letian Huang
2021	—	`ed.`	CF '21: Computing Frontiers Conference, Virtual Event, Italy, May 11-13, 2021 CF Maurizio Palesi, Antonino Tumeo, Georgios I. Goumas, Carmen G. Almudéver
2021	J	`jnl`	COPE: Reducing Cache Pollution and Network Contention by Inter-tile Coordinated Prefetching in NoC-based MPSoCs. ACM Trans. Design Autom. Electr. Syst. Dipika Deb, John Jose, Maurizio Palesi
2021	—	`conf`	LAMBDA: An Open Framework for Deep Neural Network Accelerators Simulation. PerCom Workshops Enrico Russo, Maurizio Palesi, Salvatore Monteleone, Davide Patti, Giuseppe Ascia, Vincenzo Catania
2021	J	`jnl`	On Performance Optimization and Quality Control for Approximate-Communication-Enabled Networks-on-Chip. IEEE Trans. Computers Siyuan Xiao, Xiaohang Wang, Maurizio Palesi, Amit Kumar Singh, Liang Wang, Terrence S. T. Mak
2021	J	`jnl`	Opportunistic Caching in NoC: Exploring Ways to Reduce Miss Penalty. IEEE Trans. Computers Abhijit Das, Abhishek Kumar, John Jose, Maurizio Palesi
2021	J	`jnl`	Power density aware application mapping in mesh-based network-on-chip architecture: An evolutionary multi-objective approach. Integr. Nizar Dahir, Ammar Karkar, Maurizio Palesi, Terrence S. T. Mak, Alex Yakovlev
2020	J	`jnl`	An Enhanced Dynamic Weighted Incremental Technique for QoS Support in NoC. ACM Trans. Parallel Comput. Alireza Monemi, Farshad Khunjush, Maurizio Palesi, Hamid Sarbazi-Azad
2020	J	`jnl`	An Overview of Efficient Interconnection Networks for Deep Neural Network Accelerators. IEEE J. Emerg. Sel. Topics Circuits Syst. Seyed Morteza Nabavinejad, Mohammad Baharloo, Kun-Chih Chen, Maurizio Palesi, Tim Kogel, Masoumeh Ebrahimi
2020	—	`conf`	Cloud-Based Energy Efficient Scheme for Sigfox Monarch as Asset Tracking Service. COINS Andrea Mineo, Maurizio Palesi, Davide Patti, Vincenzo Catania
2020	C	`conf`	DNNZip: Selective Layers Compression Technique in Deep Neural Network Accelerators. DSD Habiba Lahdhiri, Maurizio Palesi, Salvatore Monteleone, Davide Patti, Giuseppe Ascia, Jordane Lorandel, Emmanuelle Bourdel, Vincenzo Catania
2020	C	`conf`	Efficient Compression Technique for NoC-based Deep Neural Network Accelerators. DSD Jordane Lorandel, Habiba Lahdhiri, Emmanuelle Bourdel, Salvatore Monteleone, Maurizio Palesi
2020	J	`jnl`	Exploiting Data Resilience in Wireless Network-on-chip Architectures. ACM J. Emerg. Technol. Comput. Syst. Giuseppe Ascia, Vincenzo Catania, Salvatore Monteleone, Maurizio Palesi, Davide Patti, John Jose, Valerio Mario Salerno
2020	—	`conf`	Exploiting On-Chip Routers to Store Dirty Cache Blocks in Tiled Chip Multi-processors. ISVLSI Abhijit Das, Abhishek Kumar, John Jose, Maurizio Palesi
2020	J	`jnl`	Guest Editorial: Communication-Aware Designs and Methodologies for Reliable and Adaptable On-Chip AI SubSystems and Accelerators. IEEE J. Emerg. Sel. Topics Circuits Syst. Kun-Chih Chen, Masoumeh Ebrahimi, Maurizio Palesi, Tim Kogel
2020	J	`jnl`	Impact of Users' Beliefs in Text-Based Linguistic Interaction. IEEE Access Vincenzo Catania, Salvatore Monteleone, Maurizio Palesi, Davide Patti
2020	B	`conf`	Implementing On-Chip Wireless Communication in Multi-stage Interconnection NoCs. AINA Sirine Mnejja, Yassine Aydi, Mohamed Abid, Salvatore Monteleone, Maurizio Palesi, Davide Patti
2020	—	`conf`	Improving Inference Latency and Energy of DNNs through Wireless Enabled Multi-Chip-Module-based Architectures and Model Parameters Compression. NOCS Giuseppe Ascia, Vincenzo Catania, Andrea Mineo, Salvatore Monteleone, Maurizio Palesi, Davide Patti
2020	—	`conf`	Improving Inference Latency and Energy of Network-on-Chip based Convolutional Neural Networks through Weights Compression. IPDPS Workshops Giuseppe Ascia, Vincenzo Catania, John Jose, Salvatore Monteleone, Maurizio Palesi, Davide Patti
2020	J	`jnl`	Introduction to the special section on intelligent computing systems and their applications. Comput. Electr. Eng. Fangyang Shen, Mei Yang, Maurizio Palesi
2020	—	`ed.`	Proceedings of the 17th ACM International Conference on Computing Frontiers, CF 2020, Catania, Sicily, Italy, May 11-13, 2020 CF Maurizio Palesi, Gianluca Palermo, Catherine Graves, Eishi Arima
2020	J	`jnl`	Special issue on energy-efficient many-core embedded systems and architectures (SI: NoCArc18). J. Syst. Archit. Maurizio Palesi, Kun-Chih Jimmy Chen, Midia Reshadi
2019	A	`conf`	ACDC: An Accuracy- and Congestion-aware Dynamic Traffic Control Method for Networks-on-Chip. DATE Siyuan Xiao, Xiaohang Wang, Maurizio Palesi, Amit Kumar Singh, Terrence S. T. Mak
2019	—	`conf`	Analyzing networks-on-chip based deep neural networks. NOCS Giuseppe Ascia, Vincenzo Catania, Salvatore Monteleone, Maurizio Palesi, Davide Patti, John Jose
2019	J	`jnl`	ECAP: energy-efficient caching for prefetch blocks in tiled chip multiprocessors. IET Comput. Digit. Tech. Dipika Deb, John Jose, Maurizio Palesi
2019	—	`conf`	Networks-on-Chip based Deep Neural Networks Accelerators for IoT Edge Devices. IoTSMS Giuseppe Ascia, Vincenzo Catania, Salvatore Monteleone, Maurizio Palesi, Davide Patti, John Jose
2019	Misc	`conf`	Performance Enhancement of Caches in TCMPs Using Near Vicinity Prefetcher. VLSID Dipika Deb, John Jose, Maurizio Palesi
2019	—	`conf`	Study on logic-based routing for 3D NOCs. NoCArc@MICRO Minghua Tang, Maurizio Palesi
2018	J	`jnl`	An optimized hybrid algorithm in term of energy and performance for mapping real time workloads on 2d based on-chip networks. Appl. Intell. Sarzamin Khan, Sheraz Anjum, Usman Ali Gulzari, Farruh Ishmanov, Maurizio Palesi, Muhammad Khalil Afzal
2018	—	`conf`	Approximate Wireless Networks-on-Chip. DCIS Giuseppe Ascia, Vincenzo Catania, Salvatore Monteleone, Maurizio Palesi, Davide Patti, John Jose
2018	—	`conf`	Critical Packet Prioritisation by Slack-Aware Re-Routing in On-Chip Networks. NOCS Abhijit Das, Sarath Babu, John Jose, Sangeetha Jose, Maurizio Palesi
2018	J	`jnl`	Improving Energy Efficiency in Wireless Network-on-Chip Architectures. ACM J. Emerg. Technol. Comput. Syst. Vincenzo Catania, Andrea Mineo, Salvatore Monteleone, Maurizio Palesi, Davide Patti
2018	—	`conf`	Improving energy consumption of NoC based architectures through approximate communication. MECO Giuseppe Ascia, Vincenzo Catania, Salvatore Monteleone, Maurizio Palesi, Davide Patti, John Jose
2018	C	`conf`	Packetization of Shared-Memory Traces for Message Passing Oriented NoC Simulation. ISC Vincenzo Catania, Salvatore Monteleone, Maurizio Palesi, Davide Patti
2018	J	`jnl`	The Suboptimal Routing Algorithm for 2D Mesh Network. IEEE Trans. Computers Minghua Tang, Jing Lin, Maurizio Palesi
2018	C	`conf`	Traffic Aware Deflection Rerouting Mechanism for Mesh Network on Chip. VLSI-SoC Simi Zerine Sleeba, John Jose, Maurizio Palesi, Rekha K. James, Maniyelil Govindankutty Mini
2018	—	`conf`	smARTworks: A Multi-sided Context-aware Platform for the Smart Museum. PECCS Salvatore Michele Biondi, Vincenzo Catania, Salvatore Monteleone, Maurizio Palesi, Davide Patti
2017	—	`conf`	Energy aware Networks-on-Chip cortex inspired communication. PATMOS Erwan Moreac, Johann Laurent, Pierre Bomel, André Rossi, Emmanuel Boutillon, Maurizio Palesi
2017	J	`jnl`	Ping-lock round robin arbiter. Microelectron. J. Alireza Monemi, Chia Yee Ooi, Maurizio Palesi, Muhammad N. Marsono
2017	J	`jnl`	ProNoC: A low latency network-on-chip based many-core system-on-chip prototyping platform. Microprocess. Microsystems Alireza Monemi, Jia Wei Tang, Maurizio Palesi, Muhammad N. Marsono
2017	J	`jnl`	The Repetitive Turn Model for Adaptive Routing. IEEE Trans. Computers Minghua Tang, Xiaola Lin, Maurizio Palesi
2016	J	`jnl`	Cycle-Accurate Network on Chip Simulation with Noxim. ACM Trans. Model. Comput. Simul. Vincenzo Catania, Andrea Mineo, Salvatore Monteleone, Maurizio Palesi, Davide Patti
2016	C	`conf`	Efficient Congestion-Aware Scheme for Wireless on-Chip Networks. PDP Amin Rezaei, Masoud Daneshtalab, Maurizio Palesi, Danella Zhao
2016	A	`conf`	Energy efficient transceiver in wireless Network on Chip architectures. DATE Vincenzo Catania, Andrea Mineo, Salvatore Monteleone, Maurizio Palesi, Davide Patti
2016	J	`jnl`	Exploiting antenna directivity in wireless NoC architectures. Microprocess. Microsystems Andrea Mineo, Maurizio Palesi, Giuseppe Ascia, Vincenzo Catania
2016	—	`conf`	Improved Flow Control for Minimal Fully Adaptive Routing in 2D Mesh NoC. NoCArc@MICRO Alireza Monemi, Chia Yee Ooi, Muhammad Nadzir Marsono, Maurizio Palesi
2016	—	`conf`	Improving the energy efficiency of wireless Network on Chip architectures through online selective buffers and receivers shutdown. CCNC Vincenzo Catania, Andrea Mineo, Salvatore Monteleone, Maurizio Palesi, Davide Patti
2016	J	`jnl`	Introduction to the special section on "Sustainable processor architectures and applications". Microprocess. Microsystems Fangyang Shen, Maurizio Palesi, Mei Yang
2016	J	`jnl`	Local Congestion Avoidance in Network-on-Chip. IEEE Trans. Parallel Distributed Syst. Minghua Tang, Xiaola Lin, Maurizio Palesi
2016	J	`jnl`	Many-core System-on-Chip: architectures and applications. Microprocess. Microsystems Mohamed Bakhouya, Masoud Daneshtalab, Maurizio Palesi, Hassan Ghasemzadeh
2016	J	`jnl`	On-Chip Communication Energy Reduction Through Reliability Aware Adaptive Voltage Swing Scaling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Andrea Mineo, Maurizio Palesi, Giuseppe Ascia, Partha Pratim Pande, Vincenzo Catania
2016	J	`jnl`	Runtime Tunable Transmitting Power Technique in mm-Wave WiNoC Architectures. IEEE Trans. Very Large Scale Integr. Syst. Andrea Mineo, Maurizio Palesi, Giuseppe Ascia, Vincenzo Catania
2016	J	`jnl`	Special issue on energy efficient methods and systems in the emerging cloud era. J. Comput. Syst. Sci. Maurizio Palesi, Mario Collotta, Masoud Daneshtalab, Pradip Bose
2015	A	`conf`	A closed loop transmitting power self-calibration scheme for energy efficient WiNoC architectures. DATE Andrea Mineo, Mohd Shahrizal Rusli, Maurizio Palesi, Giuseppe Ascia, Vincenzo Catania, Muhammad N. Marsono
2015	J	`jnl`	An Offline Method for Designing Adaptive Routing Based on Pressure Model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Minghua Tang, Xiaola Lin, Maurizio Palesi
2015	J	`jnl`	Coupling Routing Algorithm and Data Encoding for Low Power Networks on Chip. J. Comput. Sci. Maurizio Palesi, Davide Patti, Giuseppe Ascia, Daniela Panno, Vincenzo Catania
2015	J	`jnl`	Introduction to the special issue on "Emerging research in Internet of Things". Comput. Electr. Eng. Fangyang Shen, Lingjia Liu, Maurizio Palesi
2015	J	`jnl`	Introduction to the special issue on NoC-based many-core architectures. Comput. Electr. Eng. Masoud Daneshtalab, Maurizio Palesi, Terrence S. T. Mak
2015	J	`jnl`	Low Energy yet Reliable Data Communication Scheme for Network-on-Chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Nima Jafarzadeh, Maurizio Palesi, Saeedeh Eskandari, Shaahin Hessabi, Ali Afzali-Kusha
2015	—	`conf`	Message from the Chairs. ESTIMedia Hyunok Oh, Muhammad Shafique, Todor P. Stefanov, Maurizio Palesi
2015	—	`conf`	Noxim: An open, extensible and cycle-accurate network on chip simulator. ASAP Vincenzo Catania, Andrea Mineo, Salvatore Monteleone, Maurizio Palesi, Davide Patti
2015	—	`ed.`	Proceedings of the 3rd International Workshop on Many-core Embedded Systems (MES'2015) held on June 13, 2015 in conjunction with the 42nd International Symposium on Computer Architecture (ISCA'2015), Portland, OR, USA MES@ISCA Masoumeh Ebrahimi, Diana Goehringer, Masoud Daneshtalab, Maurizio Palesi, Sören Sonntag, Federico Angiolini
2015	J	`jnl`	Routing Pressure: A Channel-Related and Traffic-Aware Metric of Routing Algorithm. IEEE Trans. Parallel Distributed Syst. Minghua Tang, Xiaola Lin, Maurizio Palesi
2014	—	`conf`	A Closed Loop Control based Power Manager for WiNoC Architectures. MES Mohd Shahrizal Rusli, Andrea Mineo, Maurizio Palesi, Giuseppe Ascia, Vincenzo Catania, Muhammad N. Marsono
2014	A	`conf`	Adaptive power allocation for many-core systems inspired from multiagent auction model. DATE Xiaohang Wang, Baoxin Zhao, Terrence S. T. Mak, Mei Yang, Yingtao Jiang, Masoud Daneshtalab, Maurizio Palesi
2014	A	`conf`	An adaptive transmitting power technique for energy efficient mm-wave wireless NoCs. DATE Andrea Mineo, Maurizio Palesi, Giuseppe Ascia, Vincenzo Catania
2014	J	`jnl`	Data Encoding Techniques for Reducing Energy Consumption in Network-on-Chip. IEEE Trans. Very Large Scale Integr. Syst. Nima Jafarzadeh, Maurizio Palesi, Ahmad Khademzadeh, Ali Afzali-Kusha
2014	J	`jnl`	Editorial: Special Section on ESTIMedia'13. ACM Trans. Embed. Comput. Syst. Maurizio Palesi, Todor P. Stefanov
2014	J	`jnl`	Editorial: Special issue on design challenges for many-core processors. ACM Trans. Embed. Comput. Syst. Masoud Daneshtalab, Maurizio Palesi, Juha Plosila
2014	J	`jnl`	Introduction to the Special Issue on Network-on-Chip Architectures. Comput. Electr. Eng. Masoud Daneshtalab, Maurizio Palesi, Terrence S. T. Mak
2014	—	`conf`	Merging Compilation and Microarchitectural Configuration Spaces for Performance/Power Optimization in VLIW-Based Systems. CSOC Davide Patti, Maurizio Palesi, Vincenzo Catania
2014	J	`jnl`	On self-tuning networks-on-chip for dynamic network-flow dominance adaptation. ACM Trans. Embed. Comput. Syst. Xiaohang Wang, Mei Yang, Yingtao Jiang, Peng Liu, Masoud Daneshtalab, Maurizio Palesi, Terrence S. T. Mak
2014	—	`ed.`	Proceedings of the 2nd International Workshop on Many-core Embedded Systems, MES'2014, in conjunction with the 41st International Symposium on Computer Architecture, ISCA'2014, Minneapolis, MN, USA, June 15, 2014. MES Masoud Daneshtalab, Masoumeh Ebrahimi, Maurizio Palesi, Federico Angiolini, Juha Plosila
2014	A*	`conf`	SHiFA: System-Level Hierarchy in Run-Time Fault-Aware Management of Many-Core Systems. DAC Mohammad Fattah, Maurizio Palesi, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen
2014	J	`jnl`	Special issue on many-core embedded systems. Microprocess. Microsystems Masoud Daneshtalab, Maurizio Palesi, Juha Plosila, Ahmed Hemani
2013	C	`conf`	An Adaptive Output Selection Function Based on a Fuzzy Rule Base System for Network on Chip. DSD Giuseppe Ascia, Maurizio Palesi, Vincenzo Catania
2013	J	`jnl`	Efficient multicast schemes for 3-D Networks-on-Chip. J. Syst. Archit. Xiaohang Wang, Mei Yang, Yingtao Jiang, Maurizio Palesi, Peng Liu, Terrence S. T. Mak, Nader Bagherzadeh
2013	J	`jnl`	Energy Efficient Run-Time Incremental Mapping for 3-D Networks-on-Chip. J. Comput. Sci. Technol. Xiaohang Wang, Peng Liu, Mei Yang, Maurizio Palesi, Yingtao Jiang, Michael C. Huang
2013	J	`jnl`	Guest Editors' Introduction to the Special Issue on "Novel On-Chip Parallel Architectures and Software Support". Parallel Comput. Fangyang Shen, Mei Yang, Maurizio Palesi
2013	J	`jnl`	Introduction to the special section on ESTIMedia'12. ACM Trans. Embed. Comput. Syst. Jian-Jia Chen, Maurizio Palesi
2013	J	`jnl`	Introduction to the special section on on-chip and off-chip network architectures. ACM Trans. Embed. Comput. Syst. José Flich Cardo, Maurizio Palesi
2013	—	`conf`	Low Energy Mapping Techniques under Reliability and Bandwidth Constraints. HPCC/EUC Andrea Mineo, Marina Masi, Maurizio Palesi, Giuseppe Ascia, Vincenzo Catania
2013	—	`conf`	Message from the chairs. ESTIMedia Todor P. Stefanov, Maurizio Palesi, Jian-Jia Chen, Jörg Henkel
2013	—	`ed.`	Network on Chip Architectures, NoCArc '13, in conjunction with the 46th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-46, Davis, CA, USA, December 7, 2013 NoCArc@MICRO Maurizio Palesi, Terrence S. T. Mak, Masoud Daneshtalab
2013	—	`conf`	NoC links energy reduction through link voltage scaling. ICSAMOS Andrea Mineo, Maurizio Palesi, Giuseppe Ascia, Vincenzo Catania
2013	—	`conf`	On self-tuning networks-on-chip for dynamic network-flow dominance adaptation. NOCS Xiaohang Wang, Terrence S. T. Mak, Mei Yang, Yingtao Jiang, Masoud Daneshtalab, Maurizio Palesi
2013	—	`ed.`	Proceedings of the 1st International Workshop on Many-core Embedded Systems 2013, MES'2013, Held in conjunction with the 40th Annual IEEE/ACM International Symposium on Computer Architecture, ISCA 2013, June 24, 2013. MES Masoud Daneshtalab, Ahmed Hemani, Maurizio Palesi
2013	C	`conf`	Runtime Online Links Voltage Scaling for Low Energy Networks on Chip. DSD Andrea Mineo, Maurizio Palesi, Giuseppe Ascia, Vincenzo Catania
2012	J	`jnl`	A Topology-Independent Mapping Technique for Application-Specific Networks-on-Chip. Comput. Informatics Rafael Tornero, Maurizio Palesi, José Duato
2012	J	`jnl`	Designing Robust Routing Algorithms and Mapping Cores in Networks-on-Chip: A Multi-objective Evolutionary-based Approach. J. Univers. Comput. Sci. Maurizio Palesi, Rafael Tornero, Juan Manuel Orduña, Vincenzo Catania, Daniela Panno
2012	J	`jnl`	Embedded Transitive Closure Network for Runtime Deadlock Detection in Networks-on-Chip. IEEE Trans. Parallel Distributed Syst. Ra'ed Al-Dujaily, Terrence S. T. Mak, Fei Xia, Alex Yakovlev, Maurizio Palesi
2012	—	`ed.`	Fifth International Workshop on Network on Chip Architectures, NoCArc '12, Vancouver, BC, Canada, December 1, 2012 NoCArc@MICRO Maurizio Palesi, Terrence S. T. Mak
2012	J	`jnl`	Guest Editors' Introduction to the Special Issue on "Emerging Computing Architectures and Systems". Comput. Electr. Eng. Fangyang Shen, Mei Yang, Maurizio Palesi
2012	—	`conf`	HARAQ: Congestion-Aware Learning Model for Highly Adaptive Routing Algorithm in On-Chip Networks. NOCS Masoumeh Ebrahimi, Masoud Daneshtalab, Fahimeh Farahnakian, Juha Plosila, Pasi Liljeberg, Maurizio Palesi, Hannu Tenhunen
2012	J	`jnl`	Supporting Undergraduate Computer Architecture Students Using a Visual MIPS64 CPU Simulator. IEEE Trans. Educ. Davide Patti, Andrea Spadaccini, Maurizio Palesi, Fabrizio Fazzino, Vincenzo Catania
2011	—	`ed.`	4th International Workshop on Network on Chip Architectures, NoCArc '11, Porto Alegre, Brazil, December 4-5, 2011 NoCArc@MICRO Maurizio Palesi, Shashi Kumar
2011	—	`ch.`	Application-Specific Routing Algorithms for Low Power Network on Chip Design. Low Power Networks-on-Chip Maurizio Palesi, Rickard Holsmark, Shashi Kumar, Vincenzo Catania
2011	J	`jnl`	Data Encoding Schemes in Networks on Chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Maurizio Palesi, Giuseppe Ascia, Fabrizio Fazzino, Vincenzo Catania
2011	C	`conf`	Low latency and energy efficient multicasting schemes for 3D NoC-based SoCs. VLSI-SoC Xiaohang Wang, Maurizio Palesi, Mei Yang, Yingtao Jiang, Michael C. Huang, Peng Liu
2011	J	`jnl`	Network-on-chip architectures and design methodologies. Microprocess. Microsystems Maurizio Palesi, Shashi Kumar, Radu Marculescu
2011	J	`jnl`	Performance evaluation of efficient multi-objective evolutionary algorithms for design space exploration of embedded computer systems. Appl. Soft Comput. Giuseppe Ascia, Vincenzo Catania, Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti
2011	C	`conf`	Power-Aware Run-Time Incremental Mapping for 3-D Networks-on-Chip. NPC Xiaohang Wang, Maurizio Palesi, Mei Yang, Yingtao Jiang, Michael C. Huang, Peng Liu
2011	A	`conf`	Run-time deadlock detection in networks-on-chip using coupled transitive closure networks. DATE Ra'ed Al-Dujaily, Terrence S. T. Mak, Fei Xia, Alexandre Yakovlev, Maurizio Palesi
2010	—	`conf`	A Multi-level Routing Scheme and Router Architecture to Support Hierarchical Routing in Large Network on Chip Platforms. Euro-Par Workshops Rickard Holsmark, Shashi Kumar, Maurizio Palesi
2010	C	`conf`	An Efficient Technique for In-order Packet Delivery with Adaptive Routing Algorithms in Networks on Chip. DSD Maurizio Palesi, Rickard Holsmark, Xiaohang Wang, Shashi Kumar, Mei Yang, Yingtao Jiang, Vincenzo Catania
2010	J	`jnl`	Leveraging Partially Faulty Links Usage for Enhancing Yield and Performance in Networks-on-Chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Maurizio Palesi, Shashi Kumar, Vincenzo Catania
2010	—	`ed.`	Third International Workshop on Network on Chip Architectures, NoCArc'10, Atlanta, GA, USA, December 4, 2010 NoCArc@MICRO Maurizio Palesi, Shashi Kumar, Zhonghai Lu, Ümit Y. Ogras
2009	A	`conf`	A multi-objective strategy for concurrent mapping and routing in networks on chip. IPDPS Rafael Tornero, Valentino Sterrantino, Maurizio Palesi, Juan M. Orduña
2009	C	`conf`	An Effective Methodology to Multi-objective Design of Application Domain-specific Embedded Architectures. DSD Vincenzo Catania, Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti, Gianmarco De Francisci Morales
2009	J	`jnl`	Application Specific Routing Algorithms for Networks on Chip. IEEE Trans. Parallel Distributed Syst. Maurizio Palesi, Rickard Holsmark, Shashi Kumar, Vincenzo Catania
2009	J	`jnl`	Bandwidth-aware routing algorithms for networks-on-chip platforms. IET Comput. Digit. Tech. Maurizio Palesi, Shashi Kumar, Vincenzo Catania
2009	C	`conf`	Data Encoding for Low-Power in Wormhole-Switched Networks-on-Chip. DSD Maurizio Palesi, Fabrizio Fazzino, Giuseppe Ascia, Vincenzo Catania
2009	—	`conf`	HiRA: A methodology for deadlock free routing in hierarchical networks on chip. NOCS Rickard Holsmark, Shashi Kumar, Maurizio Palesi, Andres Mejia
2009	J	`jnl`	Region-Based Routing: A Mechanism to Support Efficient Routing Algorithms in NoCs. IEEE Trans. Very Large Scale Integr. Syst. Andres Mejia, Maurizio Palesi, José Flich, Shashi Kumar, Pedro López, Rickard Holsmark, José Duato
2009	—	`ed.`	Second International Workshop on Network on Chip Architectures, NoCArc 2009, In conjunction with the 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42), December 12, 2009, New York, NY, USA NoCArc@MICRO Maurizio Palesi, Shashi Kumar
2008	—	`conf`	A Communication-Aware Topological Mapping Technique for NoCs. Euro-Par Rafael Tornero, Juan M. Orduña, Maurizio Palesi, José Duato
2008	J	`jnl`	Deadlock free routing algorithms for irregular mesh topology NoC systems with rectangular regions. J. Syst. Archit. Rickard Holsmark, Maurizio Palesi, Shashi Kumar
2008	—	`conf`	Design of Bandwidth Aware and Congestion Avoiding Efficient Routing Algorithms for Networks-on-Chip Platforms. NOCS Maurizio Palesi, Giuseppe Longo, Salvatore Signorino, Rickard Holsmark, Shashi Kumar, Vincenzo Catania
2008	C	`conf`	Efficient Application Specific Routing Algorithms for NoC Systems utilizing Partially Faulty Links. DSD Dario Frazzetta, Giuseppe Dimartino, Maurizio Palesi, Shashi Kumar, Vincenzo Catania
2008	C	`conf`	High Performance Computing for Embedded System Design: A Case Study. DSD Vincenzo Catania, Gianmarco De Francisci Morales, Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti
2008	J	`jnl`	Implementation and Analysis of a New Selection Strategy for Adaptive Routing in Networks-on-Chip. IEEE Trans. Computers Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti
2008	J	`jnl`	Reducing complexity of multiobjective design space exploration in VLIW-based embedded systems. ACM Trans. Archit. Code Optim. Vincenzo Catania, Maurizio Palesi, Davide Patti
2007	J	`jnl`	Analysis and Tools for the Design of VLIW Embedded Systems in a Multi-Objective Scenario. J. Circuits Syst. Comput. Vincenzo Catania, Maurizio Palesi, Davide Patti
2007	J	`jnl`	Efficient design space exploration for application specific systems-on-a-chip. J. Syst. Archit. Giuseppe Ascia, Vincenzo Catania, Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti
2007	A	`conf`	Exploiting Communication Concurrency for Efficient Deadlock Free Routing in Reconfigurable NoC Platforms. IPDPS Maurizio Palesi, Shashi Kumar, Rickard Holsmark, Vincenzo Catania
2007	B	`conf`	Multi-Objective Evolutionary Fuzzy Clustering for High-Dimensional Problems. FUZZ-IEEE Alessandro G. Di Nuovo, Maurizio Palesi, Vincenzo Catania
2007	J	`jnl`	Networks-on-Chip: Emerging Research Topics and Novel Ideas. VLSI Design Davide Bertozzi, Shashi Kumar, Maurizio Palesi
2006	—	`conf`	A Method for Router Table Compression for Application Specific Routing in Mesh Topology NoC Architectures. SAMOS Maurizio Palesi, Shashi Kumar, Rickard Holsmark
2006	J	`jnl`	A Multi-objective Genetic Approach to Mapping Problem on Network-on-Chip. J. Univers. Comput. Sci. Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
2006	B	`conf`	A Multiobjective Genetic Fuzzy Approach for Intelligent System-level Exploration in Parameterized VLIW Processor Design. IEEE Congress on Evolutionary Computation Giuseppe Ascia, Vincenzo Catania, Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti
2006	Misc	`conf`	A methodology for design of application specific deadlock-free routing algorithms for NoC systems. CODES+ISSS Maurizio Palesi, Rickard Holsmark, Shashi Kumar, Vincenzo Catania
2006	—	`conf`	An Efficent Hierachical Fuzzy Approach for System Level System-on-a-Chip Design. ICSAMOS Giuseppe Ascia, Vincenzo Catania, Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti
2006	—	`conf`	An Hybrid Soft Computing Approach for Automated Computer Design. STAIRS Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti
2006	C	`conf`	Deadlock Free Routing Algorithms for Mesh Topology NoC Systems with Regions. DSD Rickard Holsmark, Maurizio Palesi, Shashi Kumar
2006	Misc	`conf`	Fuzzy decision making in embedded system design. CODES+ISSS Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti, Giuseppe Ascia, Vincenzo Catania
2006	—	`conf`	Neighbors-on-Path: A New Selection Strategy for On-Chip Networks. ESTIMedia Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti
2005	J	`jnl`	A multiobjective genetic approach for system-level exploration in parameterized systems-on-a-chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
2005	—	`conf`	A system-level framework for evaluating area/performance/power trade-offs of VLIW-based embedded systems. ASP-DAC Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti
2005	B	`conf`	An evolutionary approach to network-on-chip mapping problem. Congress on Evolutionary Computation Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
2005	—	`conf`	Exploring Design Space of VLIW Architectures. ASAP Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti
2005	—	`conf`	Hyperblock formation: a power/energy perspective for high performance VLIW architectures. ISCAS (4) Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti
2004	J	`jnl`	A GA-based design space exploration framework for parameterized system-on-a-chip platforms. IEEE Trans. Evol. Comput. Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
2004	—	`conf`	Multi-objective Optimization of a Parameterized VLIW Architecture. Evolvable Hardware Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti
2004	Misc	`conf`	Multi-objective mapping for mesh-based NoC architectures. CODES+ISSS Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
2003	C	`conf`	A Genetic Approach To Bus Encoding. VLSI-SOC Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
2003	—	`conf`	A Genetic Bus Encoding Technique for Power Optimization of Embedded Systems. PATMOS Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
2003	—	`conf`	An evolutionary approach for reducing the energy in address buses. ISICT Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Antonio Parlato
2003	B	`conf`	An evolutionary approach for reducing the switching activity in address buses. IEEE Congress on Evolutionary Computation Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Antonio Parlato
2003	—	`conf`	EPIC-Explorer: A Parameterized VLIW-based Platform Framework for Design Space Exploration. ESTIMedia Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti
2002	—	`conf`	A Framework for Design Space Exploration of Parameterized VLSI Systems. ASP-DAC/VLSI Design Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
2002	—	`conf`	Multi-objective design space exploration using genetic algorithms. CODES Maurizio Palesi, Tony Givargis
2001	C	`conf`	An Evolutionary Approach for Pareto-optimal Configurations in SOC Platforms. VLSI-SOC Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
2001	J	`jnl`	An Instruction-Level Power Analysis Model with Data Dependency. VLSI Design Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Sarta
2001	—	`conf`	Parameterised system design based on genetic algorithms. CODES Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi