Maurizio Damiani

32 papers A* 3A 5C 4Misc 3Journal 12Unranked 5

Year	Rank	Type	Title / Venue / Authors
2023	J	`jnl`	Partially unate Boolean functions: Properties of their sum-of-products representations. Discret. Appl. Math. Maurizio Damiani
2003	—	`conf`	Boolean Technology Mapping Based on Logic Decomposition. SBCCI Maurizio Damiani, Andrei Y. Selchenko
2000	J	`jnl`	Enabling testability of fault-tolerant circuits by means of I IEEE Trans. Very Large Scale Integr. Syst. Alessandro Bogliolo, Michele Favalli, Maurizio Damiani
1999	A*	`conf`	Cycle-Based Symbolic Simulation of Gate-Level Synchronous Circuits. DAC Valeria Bertacco, Maurizio Damiani, Stefano Quer
1997	A	`conf`	The disjunctive decomposition of logic functions. ICCAD Valeria Bertacco, Maurizio Damiani
1997	J	`jnl`	The state reduction of nondeterministic finite-state machines. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Maurizio Damiani
1996	C	`conf`	Boolean Function Representation Based on Disjoint-Support Decompositions. ICCD Valeria Bertacco, Maurizio Damiani
1996	—	`conf`	Boolean Function Representation Using Parallel-Access Diagrams. Great Lakes Symposium on VLSI Valeria Bertacco, Maurizio Damiani
1996	Misc	`conf`	On-line Testing of an Off-the-shelf Microprocessor Board for Safety-critical Applications. EDCC Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Maurizio Damiani, Leonardo Impagliazzo, G. Sartore
1996	J	`jnl`	Scheduling and control generation with environmental constraints based on automata representations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jerry Chih-Yuan Yang, Giovanni De Micheli, Maurizio Damiani
1996	A	`conf`	Synthesis of Self-Testing Finite State Machines from High-Level Specifications. ITC Vishwani D. Agrawal, Ronald D. Blanton, Maurizio Damiani
1995	J	`jnl`	Optimization of combinational logic circuits based on compatible gates. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Maurizio Damiani, Jerry Chih-Yuan Yang, Giovanni De Micheli
1995	Misc	`conf`	Reliability evaluation of combinational logic circuits by symbolic simulation. VTS Alessandro Bogliolo, Maurizio Damiani, Piero Olivo, Bruno Riccò
1995	Misc	`conf`	Synthesis of combinational circuits with special fault-handling capabilitie. VTS Alessandro Bogliolo, Maurizio Damiani
1995	—	`conf`	Synthesis of multilevel fault-tolerant combinational circuits. ED&TC Alessandro Bogliolo, Maurizio Damiani
1994	C	`conf`	A Synthesis Framework Based on Trace and Automata Theory. ISCAS Jérôme Fron, Jerry Chih-Yuan Yang, Maurizio Damiani, Giovanni De Micheli
1994	—	`conf`	Nondeterministic finite-state machines and sequential EDAC-ETC-EUROASIC Maurizio Damiani
1994	—	`conf`	Scheduling with Environmental Constraints based on Automata Representations. EDAC-ETC-EUROASIC Jerry Chih-Yuan Yang, Giovanni De Micheli, Maurizio Damiani
1993	J	`jnl`	Don't care set specifications in combinational and synchronous logic circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Maurizio Damiani, Giovanni De Micheli
1993	A*	`conf`	Optimization of Combinational Logic Circuits Based on Compatible Gates. DAC Maurizio Damiani, Jerry Chih-Yuan Yang, Giovanni De Micheli
1992	A*	`conf`	Recurrence Equations and the Optimization of Synchronous Logic Circuits. DAC Maurizio Damiani, Giovanni De Micheli
1992	J	`jnl`	Testability measures in pseudorandom testing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Silvia Ercolani, Michele Favalli, Maurizio Damiani, Piero Olivo, Bruno Riccò
1991	J	`jnl`	Analysis and Design of Linear Finite State Machines for Signature Analysis Testing. IEEE Trans. Computers Maurizio Damiani, Piero Olivo, Bruno Riccò
1991	J	`jnl`	Fault simulation of unconventional faults in CMOS circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Michele Favalli, Piero Olivo, Maurizio Damiani, Bruno Riccò
1990	J	`jnl`	Aliasing in signature analysis testing with multiple input shift registers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Maurizio Damiani, Piero Olivo, Michele Favalli, Silvia Ercolani, Bruno Riccò
1990	J	`jnl`	Novel design for testability schemes for CMOS ICs. IEEE J. Solid State Circuits Michele Favalli, Piero Olivo, Maurizio Damiani, Bruno Riccò
1990	A	`conf`	Observability Don't Care Sets and Boolean Relations. ICCAD Maurizio Damiani, Giovanni De Micheli
1989	J	`jnl`	An analytical model for the aliasing probability in signature analysis testing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Maurizio Damiani, Piero Olivo, Michele Favalli, Bruno Riccò
1989	A	`conf`	CMOS Design for Improved IC Testability. ITC Michele Favalli, Piero Olivo, Maurizio Damiani, Bruno Riccò
1989	C	`conf`	Improved testability evaluations in combinational logic networks. ICCD Silvia Ercolani, Michele Favalli, Maurizio Damiani, Piero Olivo, Bruno Riccò
1989	A	`conf`	On the Design of Multiple-Input Shift-Registers for Signature Analysis Testing. ITC Piero Olivo, Maurizio Damiani, Bruno Riccò
1988	C	`conf`	Aliasing errors in signature analysis testing of integrated circuits. ICCD Maurizio Damiani, Piero Olivo, Michele Favalli, Bruno Riccò