Maurice Meijer

29 papers A* 2A 3B 2C 1Misc 1Journal 10Unranked 10
YearRankTypeTitle / Venue / Authors
2025 J jnl
BitWave: Exploiting Column-Based Bit-Level Sparsity for Deep Learning Acceleration.
CoRR
Man Shi, Vikram Jain, Antony Joseph, Maurice Meijer, Marian Verhelst
2025 J jnl
Enhancing ECG Classification Robustness with Lightweight Unsupervised Anomaly Detection Filters.
CoRR
Mustafa Fuad Rifet Ibrahim, Maurice Meijer, Alexander Schlaefer, Peer Stelldinger
2025 J jnl
Prototyping an End-to-End Multi-Modal Tiny-CNN for Cardiovascular Sensor Patches.
CoRR
Mustafa Fuad Rifet Ibrahim, Tunç Alkanat, Maurice Meijer, Felix Manthey, Alexander Schlaefer, Peer Stelldinger
2024 — conf
Artifact: End-to-End Multi-Modal Tiny-CNN for Cardiovascular Monitoring on Sensor Patches.
PerCom Workshops
Mustafa Fuad Rifet Ibrahim, Tunç Alkanat, Maurice Meijer, Alexander Schlaefer, Peer Stelldinger
2024 A* conf
BitWave: Exploiting Column-Based Bit-Level Sparsity for Deep Learning Acceleration.
HPCA
Man Shi, Vikram Jain, Antony Joseph, Maurice Meijer, Marian Verhelst
2024 J jnl
CMDS: Cross-layer Dataflow Optimization for DNN Accelerators Exploiting Multi-bank Memories.
CoRR
Man Shi, Steven Colleman, Charlotte VanDeMieroop, Antony Joseph, Maurice Meijer, Wim Dehaene, Marian Verhelst
2024 A* conf
End-to-End Multi-Modal Tiny-CNN for Cardiovascular Monitoring on Sensor Patches.
PerCom
Mustafa Fuad Rifet Ibrahim, Tunç Alkanat, Maurice Meijer, Alexander Schlaefer, Peer Stelldinger
2023 — conf
CMDS: Cross-layer Dataflow Optimization for DNN Accelerators Exploiting Multi-bank Memories.
ISQED
Man Shi, Steven Colleman, Charlotte VanDeMieroop, Antony Joseph, Maurice Meijer, Wim Dehaene, Marian Verhelst
2014 J jnl
Digital Systems Power Management for High Performance Mixed Signal Platforms.
IEEE Trans. Circuits Syst. I Regul. Pap.
Ajay Kapoor, Cas Groot, Gerard Villar Pique, Hamed Fatemi, Juan Diego Echeverri, Leo Sevat, Maarten Vertregt, Maurice Meijer, Vibhu Sharma, Yu Pu, José Pineda de Gyvez
2014 A conf
Logic synthesis of low-power ICs with ultra-wide voltage and frequency scaling.
DATE
Yu Pu, Juan Diego Echeverri, Maurice Meijer, José Pineda de Gyvez
2012 J jnl
Body-Bias-Driven Design Strategy for Area- and Performance-Efficient CMOS Circuits.
IEEE Trans. Very Large Scale Integr. Syst.
Maurice Meijer, José Pineda de Gyvez
2011 — conf
A 350nA voltage regulator for 90nm CMOS digital circuits with Reverse-Body-Bias.
ESSCIRC
Gerard Villar Pique, Maurice Meijer
2010 C conf
A forward body bias generator for digital CMOS circuits with supply voltage scaling.
ISCAS
Maurice Meijer, José Pineda de Gyvez, Ben Kup, Bert van Uden, Peter Bastiaansen, Marco Lammers, Maarten Vertregt
2010 — conf
Body bias driven design synthesis for optimum performance per area.
ISQED
Maurice Meijer, José Pineda de Gyvez
2010 J jnl
Ultra-Low-Power Digital Design with Body Biasing for Low Area and Performance-Efficient Operation.
J. Low Power Electron.
Maurice Meijer, José Pineda de Gyvez, Ajay Kapoor
2009 B conf
A Voltage-Mode Testing Method to Detect IDDQ Defects in Digital Circuits.
ETS
Josep Rius, Luis Elvira Villagra, Maurice Meijer
2009 J jnl
Analysis of the Influence of Substrate on the Performance of On-Chip MOS Decoupling Capacitors.
IEEE J. Solid State Circuits
Josep Rius, Maurice Meijer
2007 J jnl
Efficient testing and diagnosis of faulty power switches in SOCs.
IET Comput. Digit. Tech.
Sandeep Kumar Goel, Maurice Meijer, José Pineda de Gyvez
2006 J jnl
An Activity Monitor for Power/Performance Tuning of CMOS Digital Circuits.
J. Low Power Electron.
Josep Rius, Maurice Meijer, José Pineda de Gyvez
2006 — conf
Energy-efficient FPGA interconnect design.
DATE Designers' Forum
Maurice Meijer, Rohini Krishnan, Martijn T. Bennebroek
2006 B conf
Testing and Diagnosis of Power Switches in SOCs.
ETS
Sandeep Kumar Goel, Maurice Meijer, José Pineda de Gyvez
2005 Misc conf
Active Noise Cancellation Using Aggressor-Aware Clamping Circuit for Robust On-Chip Communication.
VLSI Design
Atul Katoch, Maurice Meijer, Sanjeev K. Jain
2005 — conf
An Activity Monitor for Power/Performance Tuning of CMOS Digital Circuits.
PATMOS
Josep Rius, José Pineda de Gyvez, Maurice Meijer
2005 — conf
Glitch-free discretely programmable clock generation on chip.
ISCAS (2)
Maurice Meijer, Francesco Pessolano, José Pineda de Gyvez
2005 — conf
Limits to performance spread tuning using adaptive voltage and body biasing.
ISCAS (1)
Maurice Meijer, Francesco Pessolano, José Pineda de Gyvez
2005 A conf
On-chip digital power supply control for system-on-chip applications.
ISLPED
Maurice Meijer, José Pineda de Gyvez, Ralph Otten
2004 — conf
Reducing Cross-Talk Induced Power Consumption and Delay.
PATMOS
André K. Nieuwland, Atul Katoch, Maurice Meijer
2004 A conf
Technology exploration for adaptive power and frequency scaling in 90nm CMOS.
ISLPED
Maurice Meijer, Francesco Pessolano, José Pineda de Gyvez
2003 — conf
Aggressor aware repeater circuits for improving on-chip bus performance and robustness.
ESSCIRC
Atul Katoch, Sanjeev K. Jain, Maurice Meijer