Maurice Jamieson

25 papers A 1B 1Journal 13Unranked 10

Year	Rank	Type	Title / Venue / Authors
2026	A	`conf`	Towards Scheduling of Pipelined Dataflow Graphs in MLIR. FPGA Gabriel Rodriguez-Canal, Nicolas Bohm Agostini, Ankur Limaye, Vito Giovanni Castellana, Joseph B. Manzano, Antonino Tumeo, Maurice Jamieson, Nick Brown
2024	—	`conf`	A shared compilation stack for distributed-memory parallelism in stencil DSLs. ASPLOS (3) George Bisbas, Anton Lydike, Emilien Bauer, Nick Brown, Mathieu Fehr, Lawrence Mitchell, Gabriel Rodriguez-Canal, Maurice Jamieson, Paul H. J. Kelly, Michel Steuwer, Tobias Grosser
2024	J	`jnl`	A shared compilation stack for distributed-memory parallelism in stencil DSLs. CoRR George Bisbas, Anton Lydike, Emilien Bauer, Nick Brown, Mathieu Fehr, Lawrence Mitchell, Gabriel Rodriguez-Canal, Maurice Jamieson, Paul H. J. Kelly, Michel Steuwer, Tobias Grosser
2024	—	`conf`	Performance Characterisation of the 64-Core SG2042 RISC-V CPU for HPC. ISC Workshops Nick Brown, Maurice Jamieson
2024	J	`jnl`	Performance characterisation of the 64-core SG2042 RISC-V CPU for HPC. CoRR Nick Brown, Maurice Jamieson
2023	—	`conf`	Backporting RISC-V Vector Assembly. ISC Workshops Joseph K. L. Lee, Maurice Jamieson, Nick Brown
2023	J	`jnl`	Backporting RISC-V Vector assembly. CoRR Joseph K. L. Lee, Maurice Jamieson, Nick Brown
2023	J	`jnl`	Experiences of running an HPC RISC-V testbed. CoRR Nick Brown, Maurice Jamieson, Joseph K. L. Lee
2023	—	`conf`	Fortran performance optimisation and auto-parallelisation by leveraging MLIR-based domain specific abstractions in Flang. SC Workshops Nick Brown, Maurice Jamieson, Anton Lydike, Emilien Bauer, Tobias Grosser
2023	J	`jnl`	Fortran performance optimisation and auto-parallelisation by leveraging MLIR-based domain specific abstractions in Flang. CoRR Nick Brown, Maurice Jamieson, Anton Lydike, Emilien Bauer, Tobias Grosser
2023	—	`conf`	Is RISC-V ready for HPC prime-time: Evaluating the 64-core Sophon SG2042 RISC-V CPU. SC Workshops Nick Brown, Maurice Jamieson, Joseph K. L. Lee, Paul Wang
2023	J	`jnl`	Is RISC-V ready for HPC prime-time: Evaluating the 64-core Sophon SG2042 RISC-V CPU. CoRR Nick Brown, Maurice Jamieson, Joseph K. L. Lee, Paul Wang
2023	—	`conf`	Stencil-HMLS: A multi-layered approach to the automatic optimisation of stencil codes on FPGA. SC Workshops Gabriel Rodriguez-Canal, Nick Brown, Maurice Jamieson, Emilien Bauer, Anton Lydike, Tobias Grosser
2023	J	`jnl`	Stencil-HMLS: A multi-layered approach to the automatic optimisation of stencil codes on FPGA. CoRR Gabriel Rodriguez-Canal, Nick Brown, Maurice Jamieson, Emilien Bauer, Anton Lydike, Tobias Grosser
2023	—	`conf`	Test-Driving RISC-V Vector Hardware for HPC. ISC Workshops Joseph K. L. Lee, Maurice Jamieson, Nick Brown, Ricardo Jesus
2023	J	`jnl`	Test-driving RISC-V Vector hardware for HPC. CoRR Joseph K. L. Lee, Maurice Jamieson, Nick Brown, Ricardo Jesus
2022	—	`conf`	Performance of the Vipera Framework for DSLs on Micro-Core Architectures. Euro-Par Workshops Maurice Jamieson, Nick Brown
2022	J	`jnl`	Performance of the Vipera framework for DSLs on micro-core architectures. CoRR Maurice Jamieson, Nick Brown
2021	J	`jnl`	Compact Native Code Generation for Dynamic Languages on Micro-core Architectures. CoRR Maurice Jamieson, Nick Brown
2021	B	`conf`	Compact native code generation for dynamic languages on micro-core architectures. CC Maurice Jamieson, Nick Brown
2020	—	`conf`	Benchmarking micro-core architectures for detecting disasters at the edge. UrgentHPC@SC Maurice Jamieson, Nick Brown
2020	J	`jnl`	Benchmarking micro-core architectures for detecting disasters at the edge. CoRR Maurice Jamieson, Nick Brown
2020	—	`conf`	Having your cake and eating it: Exploiting Python for programmer productivity and performance on micro-core architectures using ePython. SciPy Maurice Jamieson, Nick Brown, Sihang Liu
2020	J	`jnl`	High level programming abstractions for leveraging hierarchical memories with micro-core architectures. CoRR Maurice Jamieson, Nick Brown
2020	J	`jnl`	High level programming abstractions for leveraging hierarchical memories with micro-core architectures. J. Parallel Distributed Comput. Maurice Jamieson, Nick Brown