Matthias Sauer

84 papers A 16B 20C 6Misc 10Journal 13Unranked 18

Year	Rank	Type	Title / Venue / Authors
2025	B	`conf`	Automated Test Equipment Drift Characterization Based on Gauge Repeatability and Reproducibility. ETS Anand Venkatachalam, Ernst Aderholz, Matthias Sauer, Simon Schweizer, Matthias Werner, Ilia Polian
2025	—	`conf`	Exploring the Limits of LLMs for System-Level Test Program Generation: Can LLaMas Outrun Darwin? ATS Denis Schwachhofer, Steffen Becker, Stefan Wagner, Matthias Sauer, Ilia Polian
2025	A	`conf`	Influence of Automated Test Equipment Drift on Process Capability Studies. ITC Anand Venkatachalam, Ernst Aderholz, Matthias Sauer, Simon Schweizer, Matthias Werner, Ilia Polian
2025	B	`conf`	Towards Understanding of System-Level Test Unique Fails. ETS Nourhan Elhamawy, Jens Anders, Ilia Polian, Matthias Sauer
2024	—	`conf`	Large Language Model-Based Optimization for System-Level Test Program Generation. DFT Denis Schwachhofer, Peter Domanski, Steffen Becker, Stefan Wagner, Matthias Sauer, Dirk Pflüger, Ilia Polian
2024	J	`jnl`	Large Language Models to Generate System-Level Test Programs Targeting Non-functional Properties. CoRR Denis Schwachhofer, Peter Domanski, Steffen Becker, Stefan Wagner, Matthias Sauer, Dirk Pflüger, Ilia Polian
2024	B	`conf`	Optimizing System-Level Test Program Generation via Genetic Programming. ETS Denis Schwachhofer, Francesco Angione, Steffen Becker, Stefan Wagner, Matthias Sauer, Paolo Bernardi, Ilia Polian
2024	Misc	`conf`	Scenario-based Test Content Optimization: Scan Test vs. System-Level Test. VTS Nourhan Elhamawy, Jens Anders, Ilia Polian, Matthias Sauer
2024	B	`conf`	Training Large Language Models for System-Level Test Program Generation Targeting Non-functional Properties. ETS Denis Schwachhofer, Peter Domanski, Steffen Becker, Stefan Wagner, Matthias Sauer, Dirk Pflüger, Ilia Polian
2023	B	`conf`	A Survey of Recent Developments in Testability, Safety and Security of RISC-V Processors. ETS Jens Anders, Pablo Andreu, Bernd Becker, Steffen Becker, Riccardo Cantoro, Nikolaos Ioannis Deligiannis, Nourhan Elhamawy, Tobias Faller, Carles Hernández, Nele Mentens, Mahnaz Namazi Rizi, Ilia Polian, Abolfazl Sajadi, Matthias Sauer, Denis Schwachhofer, Matteo Sonza Reorda, Todor Stefanov, Ilya Tuzov, Stefan Wagner, Nusa Zidaric
2023	B	`conf`	Automating Greybox System-Level Test Generation. ETS Denis Schwachhofer, Maik Betka, Steffen Becker, Stefan Wagner, Matthias Sauer, Ilia Polian
2022	A	`conf`	Intelligent Methods for Test and Reliability. DATE Hussam Amrouch, Jens Anders, Steffen Becker, Maik Betka, Gerd Bleher, Peter Domanski, Nourhan Elhamawy, Thomas Ertl, Athanasios Gatzastras, Paul R. Genssler, Sebastian Hasler, Martin Heinrich, André van Hoorn, Hanieh Jafarzadeh, Ingmar Kallfass, Florian Klemme, Steffen Koch, Ralf Küsters, Andrés Lalama, Raphaël Latty, Yiwen Liao, Natalia Lylina, Zahra Paria Najafi-Haghi, Dirk Pflüger, Ilia Polian, Jochen Rivoir, Matthias Sauer, Denis Schwachhofer, Steffen Templin, Christian Volmer, Stefan Wagner, Daniel Weiskopf, Hans-Joachim Wunderlich, Bin Yang, Martin Zimmermann
2022	B	`conf`	Machine Learning for Test, Diagnosis, Post-Silicon Validation and Yield Optimization. ETS Hussam Amrouch, Krishnendu Chakrabarty, Dirk Pflüger, Ilia Polian, Matthias Sauer, Matteo Sonza Reorda
2021	J	`jnl`	Exploring the Mysteries of System-Level Test. CoRR Ilia Polian, Jens Anders, Steffen Becker, Paolo Bernardi, Krishnendu Chakrabarty, Nourhan Elhamawy, Matthias Sauer, Adit D. Singh, Matteo Sonza Reorda, Stefan Wagner
2021	Misc	`conf`	New Techniques for the Automatic Identification of Uncontrollable Lines in a CPU Core. VTS Nikolaos Ioannis Deligiannis, Riccardo Cantoro, Matthias Sauer, Bernd Becker, Matteo Sonza Reorda
2021	B	`conf`	Security, Reliability and Test Aspects of the RISC-V Ecosystem. ETS Jaume Abella, Sergi Alcaide, Jens Anders, Francisco Bas, Steffen Becker, Elke De Mulder, Nourhan Elhamawy, Frank K. Gürkaynak, Helena Handschuh, Carles Hernández, Michael Hutter, Leonidas Kosmidis, Ilia Polian, Matthias Sauer, Stefan Wagner, Francesco Regazzoni
2021	C	`conf`	System-Level Test: State of the Art and Challenges. IOLTS Davide Appello, H. H. Chen, Matthias Sauer, Ilia Polian, Paolo Bernardi, Matteo Sonza Reorda
2020	—	`conf`	Exploring the Mysteries of System-Level Test. ATS Ilia Polian, Jens Anders, Steffen Becker, Paolo Bernardi, Krishnendu Chakrabarty, Nourhan Elhamawy, Matthias Sauer, Adit D. Singh, Matteo Sonza Reorda, Stefan Wagner
2019	B	`conf`	On Integrating Lightweight Encryption in Reconfigurable Scan Networks. ETS Benjamin Thiemann, Linus Feiten, Pascal Raiola, Bernd Becker, Matthias Sauer
2019	A	`conf`	On Secure Data Flow in Reconfigurable Scan Networks. DATE Pascal Raiola, Benjamin Thiemann, Jan Burchard, Ahmed Atteya, Natalia Lylina, Hans-Joachim Wunderlich, Bernd Becker, Matthias Sauer
2019	A	`conf`	Security Compliance Analysis of Reconfigurable Scan Networks. ITC Natalia Lylina, Ahmed Atteya, Pascal Raiola, Matthias Sauer, Bernd Becker, Hans-Joachim Wunderlich
2018	C	`conf`	Detecting and Resolving Security Violations in Reconfigurable Scan Networks. IOLTS Pascal Raiola, Michael A. Kochte, Ahmed Atteya, Laura Rodríguez Gómez, Hans-Joachim Wunderlich, Bernd Becker, Matthias Sauer
2018	Misc	`conf`	Efficient generation of parametric test conditions for AMS chips with an interval constraint solver. VTS Felix Neubauer, Jan Burchard, Pascal Raiola, Jochen Rivoir, Bernd Becker, Matthias Sauer
2018	B	`conf`	Online prevention of security violations in reconfigurable scan networks. ETS Ahmed Atteya, Michael A. Kochte, Matthias Sauer, Pascal Raiola, Bernd Becker, Hans-Joachim Wunderlich
2018	B	`conf`	Towards the formal verification of security properties of a Network-on-Chip router. ETS Johanna Sepúlveda, Damian Aboul-Hassan, Georg Sigl, Bernd Becker, Matthias Sauer
2017	A	`conf`	Sensitized path PUF: A lightweight embedded physical unclonable function. DATE Matthias Sauer, Pascal Raiola, Linus Feiten, Bernd Becker, Ulrich Rührmair, Ilia Polian
2017	B	`conf`	Specification and verification of security in reconfigurable scan networks. ETS Michael A. Kochte, Matthias Sauer, Laura Rodríguez Gómez, Pascal Raiola, Bernd Becker, Hans-Joachim Wunderlich
2016	J	`jnl`	A Flexible Framework for the Automatic Generation of SBST Programs. IEEE Trans. Very Large Scale Integr. Syst. Andreas Riefert, Riccardo Cantoro, Matthias Sauer, Matteo Sonza Reorda, Bernd Becker
2016	Misc	`conf`	Effective generation and evaluation of diagnostic SBST programs. VTS Andreas Riefert, Riccardo Cantoro, Matthias Sauer, Matteo Sonza Reorda, Bernd Becker
2016	J	`jnl`	Extracting the RC4 secret key of the Open Smart Grid Protocol. IACR Cryptol. ePrint Arch. Linus Feiten, Matthias Sauer
2016	B	`conf`	Formal verification of secure reconfigurable scan network infrastructure. ETS Michael A. Kochte, Rafal Baranowski, Matthias Sauer, Bernd Becker, Hans-Joachim Wunderlich
2016	—	`conf`	Mixed 01X-RSL-Encoding for fast and accurate ATPG with unknowns. ASP-DAC Dominik Erb, Karsten Scheibler, Michael A. Kochte, Matthias Sauer, Hans-Joachim Wunderlich, Bernd Becker
2016	J	`jnl`	On Metrics to Quantify the Inter-Device Uniqueness of PUFs. IACR Cryptol. ePrint Arch. Linus Feiten, Matthias Sauer, Bernd Becker
2016	—	`conf`	On Optimal Power-Aware Path Sensitization. ATS Matthias Sauer, Jie Jiang, Sven Reimer, Kohei Miyase, Xiaoqing Wen, Bernd Becker, Ilia Polian
2016	J	`jnl`	PHAETON: A SAT-Based Framework for Timing-Aware Path Sensitization. IEEE Trans. Computers Matthias Sauer, Bernd Becker, Ilia Polian
2016	—	`conf`	SAT-Based Combinational and Sequential Dependency Computation. Haifa Verification Conference Mathias Soeken, Pascal Raiola, Baruch Sterin, Bernd Becker, Giovanni De Micheli, Matthias Sauer
2016	J	`jnl`	Systemic Frequency Biases in Ring Oscillator PUFs on FPGAs. IEEE Trans. Multi Scale Comput. Syst. Linus Feiten, Jonathan Oesterle, Tobias Martin, Matthias Sauer, Bernd Becker
2015	J	`jnl`	Accurate QBF-Based Test Pattern Generation in Presence of Unknown Values. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Dominik Erb, Michael A. Kochte, Sven Reimer, Matthias Sauer, Hans-Joachim Wunderlich, Bernd Becker
2015	J	`jnl`	Formal Vulnerability Analysis of Security Components. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Linus Feiten, Matthias Sauer, Tobias Schubert, Victor Tomashevich, Ilia Polian, Bernd Becker
2015	B	`conf`	Identification of high power consuming areas with gate type and logic level information. ETS Kohei Miyase, Matthias Sauer, Bernd Becker, Xiaoqing Wen, Seiji Kajihara
2015	B	`conf`	Improving RO-PUF quality on FPGAs by incorporating design-dependent frequency biases. ETS Linus Feiten, Tobias Martin, Matthias Sauer, Bernd Becker
2015	Misc	`conf`	Improving diagnosis resolution of a fault detection test set. VTS Andreas Riefert, Matthias Sauer, Sudhakar M. Reddy, Bernd Becker
2015	—	`conf`	Modeling Unknown Values in Test and Verification. SyDe Summer School Bernd Becker, Matthias Sauer, Christoph Scholl, Ralf Wimmer
2015	Misc	`conf`	Multi-cycle Circuit Parameter Independent ATPG for interconnect open defects. VTS Dominik Erb, Karsten Scheibler, Matthias Sauer, Sudhakar M. Reddy, Bernd Becker
2015	A	`conf`	On the automatic generation of SBST test programs for in-field test. DATE Andreas Riefert, Riccardo Cantoro, Matthias Sauer, Matteo Sonza Reorda, Bernd Becker
2015	A	`conf`	Solving DQBF through quantifier elimination. DATE Karina Gitina, Ralf Wimmer, Sven Reimer, Matthias Sauer, Christoph Scholl, Bernd Becker
2014	—	`conf`	A Formal Approach to the Traveling Professor Problem. Aspekte der Technischen Informatik Matthias Sauer, Stefan Kupferschmid
2014	A	`conf`	An effective approach to automatic functional processor test generation for small-delay faults. DATE Andreas Riefert, Lyl M. Ciganda, Matthias Sauer, Paolo Bernardi, Matteo Sonza Reorda, Bernd Becker
2014	—	`conf`	Circuit Parameter Independent Test Pattern Generation for Interconnect Open Defects. ATS Dominik Erb, Karsten Scheibler, Matthias Sauer, Sudhakar M. Reddy, Bernd Becker
2014	Misc	`conf`	Efficient SAT-Based Circuit Initialization for Larger Designs. VLSID Matthias Sauer, Sven Reimer, Sudhakar M. Reddy, Bernd Becker
2014	A	`conf`	Efficient SMT-based ATPG for interconnect open defects. DATE Dominik Erb, Karsten Scheibler, Matthias Sauer, Bernd Becker
2014	J	`jnl`	Exact Logic and Fault Simulation in Presence of Unknowns. ACM Trans. Design Autom. Electr. Syst. Dominik Erb, Michael A. Kochte, Matthias Sauer, Stefan Hillebrecht, Tobias Schubert, Hans-Joachim Wunderlich, Bernd Becker
2014	B	`conf`	Incremental Encoding and Solving of Cardinality Constraints. ATVA Sven Reimer, Matthias Sauer, Tobias Schubert, Bernd Becker
2014	J	`jnl`	QBF with Soft Variables. Electron. Commun. Eur. Assoc. Softw. Sci. Technol. Sven Reimer, Matthias Sauer, Paolo Marin, Bernd Becker
2014	—	`conf`	Recent advances in SAT-based ATPG: Non-standard fault models, multi constraints and optimization. DTIS Bernd Becker, Rolf Drechsler, Stephan Eggersglüß, Matthias Sauer
2014	A	`conf`	Test pattern generation in presence of unknown values based on restricted symbolic logic. ITC Dominik Erb, Karsten Scheibler, Michael A. Kochte, Matthias Sauer, Hans-Joachim Wunderlich, Bernd Becker
2014	—	`—`	Testing time - time to test?: using formal methods for the timing analysis of digital circuits. Matthias Sauer
2014	A	`conf`	Using MaxBMC for Pareto-optimal circuit initialization. DATE Sven Reimer, Matthias Sauer, Tobias Schubert, Bernd Becker
2014	B	`conf`	Variation-aware deterministic ATPG. ETS Matthias Sauer, Ilia Polian, Michael E. Imhof, Abdullah Mumtaz, Eric Schneider, Alexander Czutro, Hans-Joachim Wunderlich, Bernd Becker
2013	B	`conf`	Accurate Computation of Sensitizable Paths Using Answer Set Programming. LPNMR Benjamin Andres, Matthias Sauer, Martin Gebser, Tobias Schubert, Bernd Becker, Torsten Schaub
2013	—	`conf`	Accurate Multi-cycle ATPG in Presence of X-Values. Asian Test Symposium Dominik Erb, Michael A. Kochte, Matthias Sauer, Hans-Joachim Wunderlich, Bernd Becker
2013	—	`conf`	Detection of early-life failures in high-K metal-gate transistors and ultra low-K inter-metal dielectrics. CICC Young Moon Kim, Jun Seomun, Hyung-Ock Kim, Kyung Tae Do, Jung Yun Choi, Kee Sup Kim, Matthias Sauer, Bernd Becker, Subhasish Mitra
2013	A	`conf`	Early-life-failure detection using SAT-based ATPG. ITC Matthias Sauer, Young Moon Kim, Jun Seomun, Hyung-Ock Kim, Kyung Tae Do, Jung Yun Choi, Kee Sup Kim, Subhasish Mitra, Bernd Becker
2013	A	`conf`	Efficient SAT-based dynamic compaction and relaxation for longest sensitizable paths. DATE Matthias Sauer, Sven Reimer, Tobias Schubert, Ilia Polian, Bernd Becker
2013	—	`conf`	Equivalence Checking for Partial Implementations Revisited. MBMV Karina Gitina, Sven Reimer, Matthias Sauer, Ralf Wimmer, Christoph Scholl, Bernd Becker
2013	C	`conf`	Equivalence checking of partial designs using dependency quantified Boolean formulae. ICCD Karina Gitina, Sven Reimer, Matthias Sauer, Ralf Wimmer, Christoph Scholl, Bernd Becker
2013	Misc	`conf`	Identification of critical variables using an FPGA-based fault injection framework. VTS Andreas Riefert, Jörg Müller, Matthias Sauer, Wolfram Burgard, Bernd Becker
2013	J	`jnl`	Implementation and Analysis of Ring Oscillator PUFs on 60 nm Altera Cyclone FPGAs. Inf. Secur. J. A Glob. Perspect. Linus Feiten, Andreas Spilla, Matthias Sauer, Tobias Schubert, Bernd Becker
2013	—	`conf`	Provably optimal test cube generation using quantified boolean formula solving. ASP-DAC Matthias Sauer, Sven Reimer, Ilia Polian, Tobias Schubert, Bernd Becker
2013	J	`jnl`	SAT-Based Analysis of Sensitizable Paths. IEEE Des. Test Matthias Sauer, Alexander Czutro, Tobias Schubert, Stefan Hillebrecht, Ilia Polian, Bernd Becker
2013	—	`conf`	Search Space Reduction for Low-Power Test Generation. Asian Test Symposium Kohei Miyase, Matthias Sauer, Bernd Becker, Xiaoqing Wen, Seiji Kajihara
2012	—	`conf`	#SAT-based vulnerability analysis of security components - A case study. DFT Linus Feiten, Matthias Sauer, Tobias Schubert, Alexander Czutro, Eberhard Böhl, Ilia Polian, Bernd Becker
2012	Misc	`conf`	Analysis of Reachable Sensitisable Paths in Sequential Circuits with SAT and Craig Interpolation. VLSI Design Matthias Sauer, Stefan Kupferschmid, Alejandro Czutro, Sudhakar M. Reddy, Bernd Becker
2012	A	`conf`	Functional test of small-delay faults using SAT and Craig interpolation. ITC Matthias Sauer, Stefan Kupferschmid, Alexander Czutro, Ilia Polian, Sudhakar M. Reddy, Bernd Becker
2012	B	`conf`	Multi-conditional SAT-ATPG for power-droop testing. ETS Alexander Czutro, Matthias Sauer, Ilia Polian, Bernd Becker
2012	A	`conf`	On the optimality of K longest path generation algorithm under memory constraints. DATE Jie Jiang, Matthias Sauer, Alexander Czutro, Bernd Becker, Ilia Polian
2012	B	`conf`	On the quality of test vectors for post-silicon characterization. ETS Matthias Sauer, Alexander Czutro, Bernd Becker, Ilia Polian
2012	Misc	`conf`	SAT-ATPG using preferences for improved detection of complex defect mechanisms. VTS Alexander Czutro, Matthias Sauer, Tobias Schubert, Ilia Polian, Bernd Becker
2012	A	`conf`	Small-delay-fault ATPG with waveform accuracy. ICCAD Matthias Sauer, Alexander Czutro, Ilia Polian, Bernd Becker
2012	—	`conf`	Variation-Aware Fault Grading. Asian Test Symposium Alexander Czutro, Michael E. Imhof, J. Jiang, Abdullah Mumtaz, Matthias Sauer, Bernd Becker, Ilia Polian, Hans-Joachim Wunderlich
2011	C	`conf`	An FPGA-based framework for run-time injection and analysis of soft errors in microprocessors. IOLTS Matthias Sauer, Victor Tomashevich, Jörg Müller, Matthew Lewis, Andreas Spilla, Ilia Polian, Bernd Becker, Wolfram Burgard
2011	—	`conf`	Efficient SAT-Based Search for Longest Sensitisable Paths. Asian Test Symposium Matthias Sauer, Jie Jiang, Alejandro Czutro, Ilia Polian, Bernd Becker
2011	C	`conf`	Estimation of component criticality in early design steps. IOLTS Matthias Sauer, Alejandro Czutro, Ilia Polian, Bernd Becker
2011	C	`conf`	SAT-based analysis of sensitisable paths. DDECS Matthias Sauer, Alexander Czutro, Tobias Schubert, Stefan Hillebrecht, Ilia Polian, Bernd Becker