Matthias Gries

30 papers A* 3A 2B 2C 2Misc 3Journal 6Unranked 11
YearRankTypeTitle / Venue / Authors
2015 J jnl
Time Series Characterization of Gaming Workload for Runtime Power Management.
IEEE Trans. Computers
Benedikt Dietrich, Dip Goswami, Samarjit Chakraborty, Apratim Guha, Matthias Gries
2011 J jnl
A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling.
IEEE J. Solid State Circuits
Jason Howard, Saurabh Dighe, Sriram R. Vangal, Gregory Ruhl, Nitin Borkar, Shailendra Jain, Vasantha Erraguntla, Michael Konow, Michael Riepen, Matthias Gries, Guido Droege, Tor Lund-Larsen, Sebastian Steibl, Shekhar Borkar, Vivek K. De, Rob F. Van der Wijngaart
2011 B conf
Phase-Based Application-Driven Hierarchical Power Management on the Single-chip Cloud Computer.
PACT
Nikolas Ioannou, Michael Kauschke, Matthias Gries, Marcelo Cintra
2011 J jnl
SCC: A Flexible Architecture for Many-Core Platform Research.
Comput. Sci. Eng.
Matthias Gries, Ulrich Hoffmann, Michael Konow, Michael Riepen
2010 — conf
A 48-Core IA-32 message-passing processor with DVFS in 45nm CMOS.
ISSCC
Jason Howard, Saurabh Dighe, Yatin Vasant Hoskote, Sriram R. Vangal, David Finan, Gregory Ruhl, David Jenkins, Howard Wilson, Nitin Borkar, Gerhard Schrom, Fabric Pailet, Shailendra Jain, Tiju Jacob, Satish Yada, Sraven Marella, Praveen Salihundam, Vasantha Erraguntla, Michael Konow, Michael Riepen, Guido Droege, Joerg Lindemann, Matthias Gries, Thomas Apel, Kersten Henriss, Tor Lund-Larsen, Sebastian Steibl, Shekhar Borkar, Vivek De, Rob F. Van der Wijngaart, Timothy G. Mattson
2010 — conf
A virtual platform environment for exploring power, thermal and reliability management control strategies in high-performance multicores.
ACM Great Lakes Symposium on VLSI
Andrea Bartolini, Matteo Cacciari, Andrea Tilli, Luca Benini, Matthias Gries
2010 C conf
LMS-based low-complexity game workload prediction for DVFS.
ICCD
Benedikt Dietrich, Swaroop Nunna, Dip Goswami, Samarjit Chakraborty, Matthias Gries
2009 — conf
Implementing a Software-Based 802.11 MAC on a Customized Platform.
CCNC
Hans-Peter Loeb, Matthias Gries, Christian Sauer
2008 A* conf
SystemClick: a domain-specific framework for early exploration using functional performance models.
DAC
Christian Sauer, Matthias Gries, Hans-Peter Löb
2007 A conf
Interactive presentation: Hard- and software modularity of the NOVA MPSoC platform.
DATE
Christian Sauer, Matthias Gries, Sebastian Dirk
2007 J jnl
SystemQ: Bridging the gap between queuing-based performance evaluation and SystemC.
Des. Autom. Embed. Syst.
Sören Sonntag, Matthias Gries, Christian Sauer
2006 — conf
Application-Driven Development of Concurrent Packet Processing Platforms.
PARELEC
Christian Sauer, Matthias Gries, Jörg-Christian Niemann, Mario Porrmann, Michael Thies
2006 — conf
Performance Evaluation of Packet Processing Architectures Using Multiclass Queuing Networks.
Annual Simulation Symposium
Sören Sonntag, Matthias Gries, Christian Sauer
2005 — conf
Application-Driven Design of Cost-Efficient Communications Platforms.
GI Jahrestagung (1)
Hans-Martin Blüthgen, Christian Sauer, Dominik Langen, Matthias Gries, Wolfgang Raab
2005 C conf
Modular Reference Implementation of an IP-DSLAM.
ISCC
Christian Sauer, Matthias Gries, Sören Sonntag
2005 A* conf
Modular domain-specific implementation and exploration framework for embedded software platforms.
DAC
Christian Sauer, Matthias Gries, Sören Sonntag
2005 — conf
Performance Evaluation of VLSI platforms using SystemQ.
GI Jahrestagung (1)
Sören Sonntag, Matthias Gries, Christian Sauer
2005 — conf
SystemQ: A Queuing-Based Approach to Architecture Performance Evaluation with SystemC.
SAMOS
Sören Sonntag, Matthias Gries, Christian Sauer
2005 B conf
Trends in Access Networks and their Implementation in DSLAMs.
LCN
Christian Sauer, Matthias Gries, Sören Sonntag, Dietmar Toelle, Bo Wu, Rudi Knorr
2004 — conf
Developing a Flexible Interface for RapidIO, Hypertransport, and PCI-Express.
PARELEC
Christian Sauer, Matthias Gries, José Ignacio Gómez, Scott J. Weber, Kurt Keutzer
2004 Misc conf
Fast cycle-accurate simulation and instruction set generation for constraint-based descriptions of programmable architectures.
CODES+ISSS
Scott J. Weber, Matthew W. Moskewicz, Matthias Gries, Christian Sauer, Kurt Keutzer
2004 J jnl
Methods for evaluating and covering the design space during early design development.
Integr.
Matthias Gries
2003 A conf
Comparing Analytical Modeling with Simulation for Network Processors: A Case Study.
DATE
Matthias Gries, Chidamber Kulkarni, Christian Sauer, Kurt Keutzer
2003 Misc conf
Programming challenges in network processor deployment.
CASES
Chidamber Kulkarni, Matthias Gries, Christian Sauer, Kurt Keutzer
2002 A* conf
A framework for evaluating design tradeoffs in packet processing architectures.
DAC
Lothar Thiele, Samarjit Chakraborty, Matthias Gries, Simon Künzli
2002 — conf
Supporting a Low Delay Best-Effort Class in the Presence of Real-Time Traffic.
IEEE Real Time Technology and Applications Symposium
Samarjit Chakraborty, Matthias Gries, Lothar Thiele
2001 — —
Algorithm architecture trade offs in network processor design.
Matthias Gries
2001 Misc conf
Embedded Software in Network Processors - Models and Algorithms.
EMSOFT
Lothar Thiele, Samarjit Chakraborty, Matthias Gries, Alexander Maxiaguine, Jonas Greutert
2001 J jnl
FunState-an internal design representation for codesign.
IEEE Trans. Very Large Scale Integr. Syst.
Karsten Strehl, Lothar Thiele, Matthias Gries, Dirk Ziegenbein, Rolf Ernst, Jürgen Teich
2000 — conf
The Impact of Recent DRAM Architectures on Embedded Systems Performance.
EUROMICRO
Matthias Gries