Matthias Brändli

15 papers Journal 4Unranked 10

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	7.5 A 353mW 112Gb/s Discrete Multitone Wireline Receiver Datapath with Time-Based ADC in 5nm FinFET. ISSCC Jaewon Lee, Pier Andrea Francese, Matthias Brändli, Thomas Morf, Marcel A. Kossel, Seoyoung Jang, Gain Kim
2024	—	`conf`	A 0.88pJ/bit 112Gb/s PAM4 Transmitter with $1\mathrm{V}_{\text{ppd}}$ Output Swing and 5-Tap Analog FFE in 7nm FinFET CMOS. VLSI Technology and Circuits Zeynep Toprak Deniz, Timothy O. Dickson, Martin Cochet, Jonathan E. Proesel, John F. Bulzacchelli, Herschel A. Ainspan, Matthias Brändli, Thomas Morf, Michael P. Beakes, Mounir Meghelli
2024	—	`conf`	Digital-to-Analog Converters for 100+ Gb/s Wireline Transmitters: Architectures, Circuits, and Calibration. CICC Timothy O. Dickson, Zeynep Toprak Deniz, Martin Cochet, John F. Bulzacchelli, Marcel A. Kossel, Pier Andrea Francese, Thomas Morf, Jonathan E. Proesel, Herschel A. Ainspan, Matthias Brändli, Mounir Meghelli
2023	J	`jnl`	A 72-GS/s, 8-Bit DAC-Based Wireline Transmitter in 4-nm FinFET CMOS for 200+ Gb/s Serial Links. IEEE J. Solid State Circuits Timothy O. Dickson, Zeynep Toprak Deniz, Martin Cochet, Troy J. Beukema, Marcel A. Kossel, Thomas Morf, Young-Ho Choi, Pier Andrea Francese, Matthias Brändli, Christian W. Baks, Jonathan E. Proesel, John F. Bulzacchelli, Michael P. Beakes, Byoung-Joo Yoo, Hyoungbae Ahn, Dong-Hyuk Lim, Gunil Kang, Sang-Hune Park, Mounir Meghelli, Hyo Gyuem Rhew, Daniel J. Friedman, Michael Choi, Mehmet Soyuer, Jongshin Shin
2023	—	`conf`	An 8b 1.0-to-1.25GS/s 0.7-to-0.8V Single-Stage Time-Based Gated-Ring-Oscillator ADC with $2\times$ Interpolating Sense-Amplifier-Latches. ISSCC Serdar A. Yonar, Pier Andrea Francese, Matthias Brändli, Marcel A. Kossel, Mridula Prathapan, Thomas Morf, Andrea Ruffino, Taekwang Jang
2023	J	`jnl`	Design of Time-Encoded Spiking Neural Networks in 7-nm CMOS Technology. IEEE Trans. Circuits Syst. II Express Briefs Sandro Widmer, Marcel A. Kossel, Giovanni Cherubini, Stanislaw Wozniak, Pier Andrea Francese, Ana Stanojevic, Matthias Brändli, Klaus Frick, Angeliki Pantazi
2022	—	`conf`	A 72GS/s, 8-bit DAC-based Wireline Transmitter in 4nm FinFET CMOS for 200+Gb/s Serial Links. VLSI Technology and Circuits Timothy O. Dickson, Zeynep Toprak Deniz, Martin Cochet, Marcel A. Kossel, Thomas Morf, Young-Ho Choi, Pier Andrea Francese, Matthias Brändli, Troy J. Beukema, Christian W. Baks, Jonathan E. Proesel, John F. Bulzacchelli, Michael P. Beakes, Byoung-Joo Yoo, Hyoungbae Ahn, Dong-Hyuk Lim, Gunil Kang, Sang-Hune Park, Mounir Meghelli, Hyo-Gyuem Rhew, Daniel J. Friedman, Michael Choi, Mehmet Soyuer, Jongshin Shin
2022	—	`conf`	A cryogenic SRAM based arbitrary waveform generator in 14 nm for spin qubit control. ESSCIRC Mridula Prathapan, Peter Mueller, Christian Menolfi, Matthias Brändli, Marcel A. Kossel, Pier Andrea Francese, David Heim, Maria Vittoria Oropallo, Andrea Ruffino, Cezar B. Zota, Thomas Morf
2022	—	`conf`	An 8-bit 56GS/s 64x Time-Interleaved ADC with Bootstrapped Sampler and Class-AB Buffer in 4nm CMOS. VLSI Technology and Circuits Serdar S. Yonar, Pier Andrea Francese, Matthias Brändli, Marcel A. Kossel, Thomas Morf, Jonathan E. Proesel, Sergey V. Rylov, Herschel A. Ainspan, Martin Cochet, Zeynep Toprak Deniz, Timothy O. Dickson, Troy J. Beukema, Christian W. Baks, Michael P. Beakes, John F. Bulzacchelli, Young-Ho Choi, Byoung-Joo Yoo, Hyoungbae Ahn, Dong-Hyuk Lim, Gunil Kang, Sang-Hune Park, Mounir Meghelli, Hyo-Gyuem Rhew, Daniel J. Friedman, Michael Choi, Mehmet Soyuer, Jongshin Shin
2022	J	`jnl`	HERMES-Core - A 1.59-TOPS/mm IEEE J. Solid State Circuits Riduan Khaddam-Aljameh, Milos Stanisavljevic, Jordi Fornt Mas, Geethan Karunaratne, Matthias Brändli, Feng Liu, Abhairaj Singh, Silvia M. Müller, Urs Egger, Anastasios Petropoulos, Theodore Antonakopoulos, Kevin Brew, Samuel Choi, Injo Ok, Fee Li Lie, Nicole Saulnier, Victor Chan, Ishtiaq Ahsan, Vijay Narayanan, S. R. Nandakumar, Manuel Le Gallo, Pier Andrea Francese, Abu Sebastian, Evangelos Eleftheriou
2019	—	`conf`	A 100Gb/s 1.1pJ/b PAM-4 RX with Dual-Mode 1-Tap PAM-4 / 3-Tap NRZ Speculative DFE in 14nm CMOS FinFET. ISSCC Alessandro Cevrero, Ilter Özkaya, Pier Andrea Francese, Matthias Brändli, Christian Menolfi, Thomas Morf, Marcel A. Kossel, Lukas Kull, Danny Luu, Martino Dazzi, Thomas Toifl
2018	—	`conf`	A 0.3PJ/Bit 112GB/S PAM4 1+0.5D TX-DFE Precoder and 8-Tap FFE in 14NM CMOS. VLSI Circuits Thomas Toifl, Christian Menolfi, Matthias Brändli, Alessandro Cevrero, Pier Andrea Francese, Marcel A. Kossel, Lukas Kull, Danny Luu, Thomas Morf, Ilter Özkaya
2018	J	`jnl`	A 24-72-GS/s 8-b Time-Interleaved SAR ADC With 2.0-3.3-pJ/Conversion and >30 dB SNDR at Nyquist in 14-nm CMOS FinFET. IEEE J. Solid State Circuits Lukas Kull, Danny Luu, Christian Menolfi, Matthias Brändli, Pier Andrea Francese, Thomas Morf, Marcel A. Kossel, Alessandro Cevrero, Ilter Özkaya, Thomas Toifl
2018	—	`conf`	A 50GB/S 1.6PJ/B RX Data-Path with Quarter-Rate 3-Tap Speculative DFE. VLSI Circuits Pier Andrea Francese, Alessandro Cevrero, Ilter Özkaya, Matthias Brändli, Christian Menolfi, Thomas Morf, Marcel A. Kossel, Lukas Kull, Danny Luu, Thomas Toifl
2015	—	`—`	Die Online-Kommunikation von politischen Interessengruppen in der Schweiz: Bedeutung, Einsatz und Veränderung der Organisationsstrukturen. Matthias Brändli