Matthew R. Guthaus

64 papers A* 7A 7C 19Misc 1Journal 12Unranked 16

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	Effective Capacitance Modeling Using Graph Neural Networks. CoRR Eren Dogan, Matthew R. Guthaus
2024	A	`conf`	GAT-Steiner: Rectilinear Steiner Minimal Tree Prediction Using GNNs. ICCAD Bugra Onal, Eren Dogan, Muhammad Hadir Khan, Matthew R. Guthaus
2024	J	`jnl`	GAT-Steiner: Rectilinear Steiner Minimal Tree Prediction Using GNNs. CoRR Bugra Onal, Eren Dogan, Muhammad Hadir Khan, Matthew R. Guthaus
2024	J	`jnl`	VLSI Hypergraph Partitioning with Deep Learning. CoRR Muhammad Hadir Khan, Bugra Onal, Eren Dogan, Matthew R. Guthaus
2023	C	`conf`	SRAM Design with OpenRAM in SkyWater 130nm. ISCAS Jesse Cirimelli-Low, Muhammad Hadir Khan, Samuel Crow, Amogh Lonkar, Bugra Onal, Andrew D. Zonenberg, Matthew R. Guthaus
2019	C	`conf`	Automated Synthesis of Multi-Port Memories and Control. VLSI-SoC Hunter Nichols, Michael Grimes, Jennifer Sowash, Jesse Cirimelli-Low, Matthew R. Guthaus
2019	C	`conf`	Bottom-Up Approach for High Speed SRAM Word-line Buffer Insertion Optimization. VLSI-SoC Bin Wu, Matthew R. Guthaus
2019	C	`conf`	Fast and Area-Efficient SRAM Word-Line Optimization. ISCAS Bin Wu, James E. Stine, Matthew R. Guthaus
2019	J	`jnl`	HCDN: Hybrid-Mode Clock Distribution Networks. IEEE Trans. Circuits Syst. I Regul. Pap. Riadul Islam, Matthew R. Guthaus
2018	J	`jnl`	DCMCS: Highly Robust Low-Power Differential Current-Mode Clocking and Synthesis. IEEE Trans. Very Large Scale Integr. Syst. Riadul Islam, Hany Ahmed Fahmy, Ping-Yao Lin, Matthew R. Guthaus
2017	A*	`conf`	Architectural opportunities for novel dynamic EMI shifting (DEMIS). MICRO Daphne I. Gorman, Matthew R. Guthaus, Jose Renau
2017	J	`jnl`	CMCS: Current-Mode Clock Synthesis. IEEE Trans. Very Large Scale Integr. Syst. Riadul Islam, Matthew R. Guthaus
2017	—	`conf`	Energy Savings and Performance Improvement in Subthreshold Using Adaptive Body Bias. ACM Great Lakes Symposium on VLSI Rajsaktish Sankaranarayanan, Matthew R. Guthaus
2017	C	`conf`	Timing speculative SRAM. ISCAS Elnaz Ebrahimi, Matthew R. Guthaus, Jose Renau
2016	C	`conf`	A 64 kb differential single-port 12T SRAM design with a bit-interleaving scheme for low-voltage operation in 32 nm SOI CMOS. ICCD Samira Ataei, James E. Stine, Matthew R. Guthaus
2016	A	`conf`	OpenRAM: an open-source memory compiler. ICCAD Matthew R. Guthaus, James E. Stine, Samira Ataei, Brian Chen, Bin Wu, Mehedi Sarwar
2015	—	`conf`	Differential current-mode clock distribution. MWSCAS Riadul Islam, Hany Ahmed Fahmy, Ping-Yao Lin, Matthew R. Guthaus
2015	C	`conf`	LC resonant clock resource minimization using compensation capacitance. ISCAS Ping-Yao Lin, Hany Ahmed Fahmy, Riadul Islam, Matthew R. Guthaus
2015	J	`jnl`	Low-Power Clock Distribution Using a Current-Pulsed Clocked Flip-Flop. IEEE Trans. Circuits Syst. I Regul. Pap. Riadul Islam, Matthew R. Guthaus
2015	C	`conf`	Multi-frequency resonant clocks. ISCAS Benjamin M. LaCara, Ping-Yao Lin, Matthew R. Guthaus
2015	C	`conf`	Switched capacitor quasi-adiabatic clocks. ISCAS Hany Ahmed Fahmy, Ping-Yao Lin, Riadul Islam, Matthew R. Guthaus
2014	J	`jnl`	Confronting the Variability Issues Affecting the Performance of Next-Generation SRAM Design to Optimize and Predict the Speed and Yield. IEEE Access Jeren Samandari-Rad, Matthew R. Guthaus, Richard Hughey
2014	C	`conf`	Current-mode clock distribution. ISCAS Riadul Islam, Matthew R. Guthaus
2013	—	`conf`	A decap placement methodology for reducing joule heating and temperature in PSN interconnect. MWSCAS Sheldon Logan, Matthew R. Guthaus
2013	C	`conf`	Embedded tutorials: Embedded tutorial 1: Cell-aware test-from gates to transistors. VLSI-SoC Janusz Rajski, Miodrag Potkonjak, Adit D. Singh, Abhijit Chatterjee, Zain Navabi, Matthew R. Guthaus, Sezer Gören
2013	—	`conf`	Redundant C4 power pin placement to ensure robust power grid delivery. MWSCAS Sheldon Logan, Matthew R. Guthaus
2013	J	`jnl`	Revisiting automated physical synthesis of high-performance clock networks. ACM Trans. Design Autom. Electr. Syst. Matthew R. Guthaus, Gustavo Wilke, Ricardo Reis
2013	—	`ed.`	VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design - 20th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012, Revised Selected Papers VLSI-SoC (Selected Papers) Andreas Burg, Ayse K. Coskun, Matthew R. Guthaus, Srinivas Katkoori, Ricardo Reis
2012	C	`ed.`	20th IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012 VLSI-SoC Srinivas Katkoori, Matthew R. Guthaus, Ayse K. Coskun, Andreas Burg, Ricardo Reis
2012	C	`conf`	A single-VDD ultra-low energy sub-threshold FPGA. VLSI-SoC Rajsaktish Sankaranarayanan, Matthew R. Guthaus
2012	J	`jnl`	Distributed LC Resonant Clock Grid Synthesis. IEEE Trans. Circuits Syst. I Regul. Pap. Xuchu Hu, Matthew R. Guthaus
2012	C	`conf`	Dynamic voltage scaling for SEU-tolerance in low-power memories. VLSI-SoC Seokjoong Kim, Matthew R. Guthaus
2012	C	`conf`	Harmonic resonant clocking. VLSI-SoC Haven Blake Skinner, Xuchu Hu, Matthew R. Guthaus
2012	A	`conf`	High-Performance, Low-Power Resonant Clocking: Embedded tutorial. ICCAD Matthew R. Guthaus, Baris Taskin
2012	J	`jnl`	High-performance clock mesh optimization. ACM Trans. Design Autom. Electr. Syst. Matthew R. Guthaus, Xuchu Hu, Gustavo Wilke, Guilherme Flach, Ricardo Reis
2012	A*	`conf`	Library-aware resonant clock synthesis (LARCS). DAC Xuchu Hu, Walter James Condley, Matthew R. Guthaus
2012	—	`conf`	Lithography-aware layout compaction. ACM Great Lakes Symposium on VLSI Curtis Andrus, Matthew R. Guthaus
2012	—	`conf`	SEU-Aware Low-Power Memories Using a Multiple Supply Voltage Array Architecture. VLSI-SoC (Selected Papers) Seokjoong Kim, Matthew R. Guthaus
2012	—	`conf`	VAR-TX: A variability-aware SRAM model for predicting the optimum architecture to achieve minimum access-time for yield enhancement in nano-scaled CMOS. ISQED Jeren Samandari-Rad, Matthew R. Guthaus, Richard Hughey
2012	C	`conf`	Welcome from the general chair. VLSI-SoC Matthew R. Guthaus
2011	A	`conf`	A methodology for local resonant clock synthesis using LC-assisted local clock buffers. ICCAD Walter James Condley, Xuchu Hu, Matthew R. Guthaus
2011	—	`conf`	Advanced logic design through hands-on digital music synthesis. MSE Walter James Condley, Andrew W. Hill, Matthew R. Guthaus
2011	—	`conf`	Clock tree optimization for Electromagnetic Compatibility (EMC). ASP-DAC Xuchu Hu, Matthew R. Guthaus
2011	C	`conf`	Distributed LC resonant clock tree synthesis. ISCAS Matthew R. Guthaus
2011	A*	`conf`	Distributed Resonant clOCK grid Synthesis (ROCKS). DAC Xuchu Hu, Matthew R. Guthaus
2011	A*	`conf`	Leakage-aware redundancy for reliable sub-threshold memories. DAC Seokjoong Kim, Matthew R. Guthaus
2011	A	`conf`	Low-power multiple-bit upset tolerant memory optimization. ICCAD Seokjoong Kim, Matthew R. Guthaus
2011	—	`conf`	Package-chip co-design to increase flip-chip C4 reliability. ISQED Sheldon Logan, Matthew R. Guthaus
2011	C	`conf`	SNM-aware power reduction and reliability improvement in 45nm SRAMs. VLSI-SoC Seokjoong Kim, Matthew R. Guthaus
2010	—	`conf`	Analysis of high-performance clock networks with RLC and transmission line effects. SLIP Walter James Condley, Xuchu Hu, Matthew R. Guthaus
2010	—	`conf`	Analysis of power supply induced jitter in actively de-skewed multi-core systems. ISQED Derek Chan, Matthew R. Guthaus
2010	A*	`conf`	Non-uniform clock mesh optimization with linear programming buffer insertion. DAC Matthew R. Guthaus, Gustavo Wilke, Ricardo Reis
2009	C	`conf`	Fault-tolerant synthesis using non-uniform redundancy. ICCD Keven L. Woo, Matthew R. Guthaus
2009	A	`conf`	Measuring and modeling variabilityusing low-cost FPGAs. FPGA Michael Brown, Cyrus Bazeghi, Matthew R. Guthaus, Jose Renau
2009	—	`conf`	Teaching VLSI design in 10 weeks. MSE Matthew R. Guthaus
2008	—	`conf`	Clock tree synthesis with data-path sensitivity matching. ASP-DAC Matthew R. Guthaus, Dennis Sylvester, Richard B. Brown
2006	A*	`conf`	Clock buffer and wire sizing using sequential programming. DAC Matthew R. Guthaus, Dennis Sylvester, Richard B. Brown
2006	—	`—`	Clock tree analysis and synthesis considering process parameters and variability. Matthew R. Guthaus
2006	—	`conf`	Process-induced skew reduction in nominal zero-skew clock trees. ASP-DAC Matthew R. Guthaus, Dennis Sylvester, Richard B. Brown
2005	A	`conf`	Gate sizing using incremental parameterized statistical timing analysis. ICCAD Matthew R. Guthaus, Natesan Venkateswaran, Chandu Visweswariah, Vladimir Zolotov
2005	—	`conf`	Optimization objectives and models of variation for statistical gate sizing. ACM Great Lakes Symposium on VLSI Matthew R. Guthaus, Natesan Venkateswaran, Vladimir Zolotov, Dennis Sylvester, Richard B. Brown
2005	J	`jnl`	Partitioning Variables across Register Windows to Reduce Spill Code in a Low-Power Processor. IEEE Trans. Computers Rajiv A. Ravindran, Robert M. Senger, Eric D. Marsman, Ganesh S. Dasika, Matthew R. Guthaus, Scott A. Mahlke, Richard B. Brown
2003	A*	`conf`	A 16-bit mixed-signal microsystem with integrated CMOS-MEMS clock reference. DAC Robert M. Senger, Eric D. Marsman, Michael S. McCorquodale, Fadi H. Gebara, Keith L. Kraver, Matthew R. Guthaus, Richard B. Brown
2003	Misc	`conf`	Increasing the number of effective registers in a low-power processor using a windowed register file. CASES Rajiv A. Ravindran, Robert M. Senger, Eric D. Marsman, Ganesh S. Dasika, Matthew R. Guthaus, Scott A. Mahlke, Richard B. Brown