Matthew Naylor

20 papers A* 3B 5C 3Journal 4Unranked 5
YearRankTypeTitle / Venue / Authors
2026 — conf
CHERI-SIMT: Implementing Capability Memory Protection in GPUs.
ASPLOS (1)
Matthew Naylor, Alexandre Joannou, A. Theodore Markettos, Paul Metzger, Simon W. Moore, Timothy M. Jones
2025 A* conf
Adaptive CHERI Compartmentalization for Heterogeneous Accelerators.
ISCA
Jianyi Cheng, A. Theodore Markettos, Alexandre Joannou, Paul Metzger, Matthew Naylor, Peter Rugg, Timothy M. Jones
2025 A* conf
Deprivileging Low-Level GPU Drivers Efficiently with User-Space Processes and CHERI Compartments.
CCS
Paul Metzger, A. Theodore Markettos, Edward Tomasz Napierala, Matthew Naylor, Robert N. M. Watson, Timothy M. Jones
2024 C conf
Advanced Dynamic Scalarisation for RISC-V GPGPUs.
ICCD
Matthew Naylor, Alexandre Joannou, A. Theodore Markettos, Paul Metzger, Simon W. Moore, Timothy M. Jones
2024 J jnl
Randomized Testing of RISC-V CPUs Using Direct Instruction Injection.
IEEE Des. Test
Alexandre Joannou, Peter Rugg, Jonathan Woodruff, Franz A. Fuchs, Marno van der Maas, Matthew Naylor, Michael Roe, Robert N. M. Watson, Peter G. Neumann, Simon W. Moore
2023 J jnl
POETS: An Event-driven Approach to Dissipative Particle Dynamics: Implementing a Massively Compute-intensive Problem on a Novel Hard/Software Architecture.
ACM Trans. Parallel Comput.
Andrew D. Brown, Jonathan R. Beaumont, David B. Thomas, Julian C. Shillcock, Matthew Naylor, Graeme M. Bragg, Mark Vousden, Simon W. Moore, Shane T. Fleming
2022 J jnl
Practical Distributed Implementation of Very Large Scale Petri Net Simulations.
Trans. Petri Nets Other Model. Concurr.
Ashur Rafiev, Jordan Morris, Fei Xia, Alex Yakovlev, Matthew Naylor, Simon W. Moore, David B. Thomas, Graeme M. Bragg, Mark Vousden, Andrew Brown
2022 J jnl
Synchronization in graph analysis algorithms on the Partially Ordered Event-Triggered Systems many-core architecture.
IET Comput. Digit. Tech.
Ashur Rafiev, Alex Yakovlev, Ghaith Tarawneh, Matthew Naylor, Simon W. Moore, David B. Thomas, Graeme M. Bragg, Mark Vousden, Andrew D. Brown
2021 C conf
General hardware multicasting for fine-grained message-passing architectures.
PDP
Matthew Naylor, Simon W. Moore, David B. Thomas, Jonathan R. Beaumont, Shane T. Fleming, Mark Vousden, A. Theodore Markettos, Thomas Bytheway, Andrew D. Brown
2020 A* conf
Rigorous engineering for hardware security: Formal modelling and proof in the CHERI design and implementation process.
SP
Kyndylan Nienhuis, Alexandre Joannou, Thomas Bauereiss, Anthony C. J. Fox, Michael Roe, Brian Campbell, Matthew Naylor, Robert M. Norton, Simon W. Moore, Peter G. Neumann, Ian Stark, Robert N. M. Watson, Peter Sewell
2020 — conf
Termination detection for fine-grained message-passing architectures.
ASAP
Matthew Naylor, Simon W. Moore, Andrey Mokhov, David B. Thomas, Jonathan R. Beaumont, Shane T. Fleming, A. Theodore Markettos, Thomas Bytheway, Andrew D. Brown
2019 — conf
POETS: Distributed Event-Based Computing - Scaling Behaviour.
PARCO
Andrew D. Brown, Mark Vousden, Alex Rast, Graeme M. Bragg, David B. Thomas, Jonny Beaumont, Matthew Naylor, Andrey Mokhov
2019 B conf
Tinsel: A Manythread Overlay for FPGA Clusters.
FPL
Matthew Naylor, Simon W. Moore, David B. Thomas
2017 — conf
Distributed Event-Based Computing.
PARCO
Andrew D. Brown, David B. Thomas, Jeff Reeve, Ghaith Tarawneh, Alessandro de Gennaro, Andrey Mokhov, Matthew Naylor, Tom Kazmierski
2017 — conf
Programming Model to Develop Supercomputer Combinatorial Solvers.
ICPP Workshops
Ghaith Tarawneh, Andrey Mokhov, Matthew Naylor, Alex Rast, Simon W. Moore, David B. Thomas, Alex Yakovlev, Andrew D. Brown
2016 B conf
A consistency checker for memory subsystem traces.
FMCAD
Matthew Naylor, Simon W. Moore, Alan Mujumdar
2015 C conf
A generic synthesisable test bench.
MEMOCODE
Matthew Naylor, Simon W. Moore
2014 B conf
Rapid codesign of a soft vector processor and its compiler.
FPL
Matthew Naylor, Simon W. Moore
2013 B conf
A spiking neural network on a portable FPGA tablet.
FPL
Matthew Naylor, Paul James Fox, A. Theodore Markettos, Simon W. Moore
2013 B conf
Managing the FPGA memory wall: Custom computing or vector processing?
FPL
Matthew Naylor, Paul James Fox, A. Theodore Markettos, Simon W. Moore