Matteo Sonza Reorda

562 papers A* 2A 58B 42C 100Misc 36Journal 107Unranked 214

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Benchmark Suite for Resilience Assessment of Deep Learning Models. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Cristiana Bolchini, Alberto Bosio, Luca Cassano, Antonio Miele, Salvatore Pappalardo, Dario Passarello, Annachiara Ruospo, Ernesto Sánchez, Matteo Sonza Reorda, Vittorio Turco
2026	—	`conf`	Investigating the Impact of Soft Errors in GPU-Accelerated Sparse DNNs. LASCAS Mohammad Hasan Ahmadilivani, Josie E. Rodriguez Condia, Maksim Jenihhin, Matteo Sonza Reorda
2026	—	`conf`	Reliability Assessment of Deep Neural Networks and Accelerators Across Design Stages. LATS Mohammad Hasan Ahmadilivani, Natalia Cherezova, Michael Glaß, Juan-David Guerrero-Balaguera, Maksim Jenihhin, Angeliki Kritikakou, Robert Limas Sierra, Letícia Maria Veiras Bolzani Poehls, Jaan Raik, Lucas Roquet, Fernando Fernandes dos Santos, Felipe Augusto da Silva, Matteo Sonza Reorda, Alessandro Veronesi, Ernesto Cristopher Villegas Castillo, Josie E. Rodriguez Condia
2025	A	`conf`	A Benchmark Suite to Evaluate DNN's Resilience. ITC Cristiana Bolchini, Alberto Bosio, Luca Cassano, Antonio Miele, Salvatore Pappalardo, Dario Passariello, Annachiara Ruospo, Ernesto Sánchez, Matteo Sonza Reorda, Vittorio Turco
2025	—	`conf`	A New Online Fault Detection Mechanism for Neural Network Applications. ICECS Luca De Paola, Giuseppe Esposito, Juan-David Guerrero-Balaguera, Matteo Sonza Reorda
2025	J	`jnl`	A Reliability Evaluation Flow for Assessing the Impact of Permanent Hardware Faults on Integer Arithmetic Circuits. IEEE Access Nikolaos Ioannis Deligiannis, Juan-David Guerrero-Balaguera, Riccardo Cantoro, Serag E.-D. Habib, Matteo Sonza Reorda
2025	C	`conf`	AI-Based Classification of Adversarial Attacks vs. Hardware Fault Corruptions in the Split Computing Context. IOLTS Giuseppe Esposito, Enrico Magliano, Nicola Scarano, Tamer Ahmed Eltaras, Juan-David Guerrero-Balaguera, Luca Mannella, Josie E. Rodriguez Condia, Annachiara Ruospo, Stefano Di Carlo, Marco Levorato, Alessandro Savino, Matteo Sonza Reorda
2025	—	`conf`	APSS Metrics for Fault Detection: Area, Position, Symmetry, and Shape in Image Segmentation. DFT Vittorio Turco, L. Fezza, Annachiara Ruospo, E. Sanchez, Matteo Sonza Reorda
2025	—	`conf`	About the Functional In-Field Self-Testing of AI Accelerators. LATS Juan-David Guerrero-Balaguera, Josie E. Rodriguez Condia, Robert Limas Sierra, Matteo Sonza Reorda
2025	J	`jnl`	An Effective Iterative Statistical Fault Injection Methodology for Deep Neural Networks. IEEE Trans. Computers Annachiara Ruospo, Matteo Sonza Reorda, Riccardo Mariani, Ernesto Sánchez
2025	C	`conf`	Analysis and Mitigation of Soft-errors in GPU-accelerated Hyperspectral Image Classifiers. DDECS Sergiu-Mohamed Abed, Juan-David Guerrero-Balaguera, Josie E. Rodriguez Condia, Gianluca De Lucia, Marco Lapegna, Matteo Sonza Reorda
2025	J	`jnl`	Effective Fault Effects Evaluation for Permanent Faults in GPUs executing DNNs. ACM Trans. Design Autom. Electr. Syst. Juan-David Guerrero-Balaguera, Josie Esteban Rodriguez Condia, Matteo Sonza Reorda
2025	J	`jnl`	Enhancing the Effectiveness of STLs for GPUs via Bounded Model Checking. ACM Trans. Design Autom. Electr. Syst. Nikolaos Ioannis Deligiannis, Tobias Faller, Josie Esteban Rodriguez Condia, Riccardo Cantoro, Bernd Becker, Matteo Sonza Reorda
2025	—	`conf`	Estimating the Impact of Soft Errors on AI-Based Perception in Automotive. LATS Shailesh Hegde, Dinesh Cyril Selvaraj, Josie E. Rodriguez Condia, Nicola Amati, Carla-Fabiana Chiasserini, Francesco Deflorio, Matteo Sonza Reorda
2025	B	`conf`	European Test Symposium Teams: an Anniversary Snapshot. ETS Maksim Jenihhin, Jaan Raik, Artur Jutman, Natalia Cherezova, Raimund Ubar, Liviu Miclea, Szilárd Enyedi, I. Stefan, Ovidiu Stan, Cosmina Corches, Z. Peng, Petru Eles, Rolf Drechsler, S. Eggersglüß, Görschwin Fey, Andreas Glowatz, Daniel Tille, Georges G. E. Gielen, Anthony Coyette, Wim Dobbelaere, Ronny Vanhooren, P.-Y. Chuang, Erik Jan Marinissen, Giorgio Di Natale, M. Barragan, Paolo Maistri, S. Mir, Vatajelu I. Vatajelu, Paolo Bernardi, S. Di Carlo, Paolo Prinetto, Matteo Sonza Reorda, Massimo Violante, Haralampos-G. Stratigopoulos, M. K. Michael, Stelios Neophytou, Stavros Hadjitheophanous, Kyriakos Christou, M. Skitsas, Alberto Bosio, Bastien Deveautour, P. Girard, Marcello Traiola, Arnaud Virazel, F. Fernandes Dos Santos, Angeliki Kritikakou, Gioele Casagranda, Marzio Vallero, Flavio Vella, Paolo Rech, Letícia Maria Bolzani Poehls, Milos Krstic, Marko S. Andjelkovic, F. Vargas, Grigor Tshagharyan, Gurgen Harutyunyan, Valery A. Vardanian, Samvel K. Shoukourian, Yervant Zorian, Jennifer Dworak, Kundan Nepal, Theodore W. Manikas, Mottaqiallah Taouil, Moritz Fieback, Anteneh Gebregiorgis, Rajendra Bishnoi, Said Hamdioui, Abhijit Chatterjee, A. Saha, Suhasini Komarraju, K. Ma, Chandramouli N. Amarnath, Mehdi Baradaran Tahoori, Mahta Mayahinia, Maryam Rajabalipanah, Katayoon Basharkhah, N. Nosrati, Zahra Jahanpeima, Zain Navabi, Hans-Joachim Wunderlich, Sybille Hellebrand
2025	A	`conf`	Exploiting the correlation with traditional fault models to speed-up cell-aware fault simulation. ITC Reza Khoshzaban, Iacopo Guglielminetti, Michelangelo Grosso, Matteo Sonza Reorda, Riccardo Cantoro
2025	C	`conf`	GPD: Predictive Control Flow Error Detection Leveraging Data Flow Error Detection Methods. IOLTS Raghunandana K. K, Yogesh Prasad K. R, Matteo Sonza Reorda, Virendra Singh
2025	J	`jnl`	GPU Under Pressure: Estimating Application's Stress via Telemetry and Performance Counters. CoRR Giuseppe Esposito, Juan-David Guerrero-Balaguera, Josie Esteban Rodriguez Condia, Matteo Sonza Reorda, Marco Barbiero, Rossella Fortuna
2025	—	`conf`	Improving CNN Runtime Robustness Against Soft Errors by Dropout Layer Optimization. LATS Robert Limas Sierra, Giuseppe Esposito, Juan-David Guerrero-Balaguera, Josie E. Rodriguez Condia, Matteo Sonza Reorda
2025	J	`jnl`	Investigating and Mitigating Critical Faults in Floating-Point and Posit Arithmetic Hardware. IEEE Trans. Emerg. Top. Comput. Josie E. Rodriguez Condia, Juan-David Guerrero-Balaguera, Robert Limas Sierra, Matteo Sonza Reorda
2025	C	`conf`	Non-Functional Properties in HPC Systems: Design Exploration of Energy, Power, and Reliability. DSD Giovanni Agosta, Enrico Bini, Davide Baroffio, Carlo Brandolese, Michele Castrovilli, Daniele Cattaneo, Daniele Cesarini, William Fornaciari, Andrea Galimberti, Alberto Garfagnini, Arsenii Gavrikov, Francesco Iannone, Marco Lapegna, Tomas Antonio Lopez, Gabriele Magnani, Gabriele Mencagli, Cecilia Metra, Martin Eugenio Omana, Filippo Palombi, Federico Reghenzani, Josie E. Rodriguez Condia, A. Serafini, Matteo Sonza Reorda, Davide Zoni, Giuseppe Zummo
2025	J	`jnl`	SHADOWFI: An Open-Source Framework for Fault Evaluation of Complex IC Designs Using Hyperscale Computing. IEEE Access Juan-David Guerrero-Balaguera, Robert Limas Sierra, Oguz Sensoz, Josie E. Rodriguez Condia, Maynor Giovanni Ballina Escobar, Maria Liz Crespo, Sergio Carrato, Matteo Sonza Reorda
2025	C	`conf`	Towards RISC-V-based HPC: The Italian Pathfinding Activities in the DARE-SGA1 Project. DSD Giovanni Agosta, Marco Aldinucci, Andrea Bartolini, Laura Bellentani, Andrea Biagioni, Daniele Cesarini, Carlotta Chiarini, Iacopo Colonnelli, Pietro Delugas, Lev Denisov, Ottorino Frezza, Marco Grangetto, Francesca Lo Cicero, Alessandro Lonardo, Michele Martinelli, Andrea Maslov, Mauro Olivieri, Pierpaolo Perticaroli, Luca Pontisso, Cristian Rossi, Davide Rossi, Sergio Saponara, Antonio Sciarappa, Francesco Simula, Matteo Sonza Reorda, Massimo Torquati, Piero Vicini
2024	Misc	`conf`	Analyzing the Impact of Scheduling Policies on the Reliability of GPUs Running CNN Operations. VTS Robert Limas Sierra, Juan-David Guerrero-Balaguera, Francesco Pessia, Josie E. Rodriguez Condia, Matteo Sonza Reorda
2024	B	`conf`	Analyzing the Structural and Operational Impact of Faults in Floating-Point and Posit Arithmetic Cores for CNN Operations. ETS Josie E. Rodriguez Condia, Juan-David Guerrero-Balaguera, Robert Limas Sierra, Matteo Sonza Reorda
2024	B	`conf`	Assessing the Effectiveness of Software-Based Self-Test Programs for Static Cell-Aware Test. ETS Riccardo Cantoro, Michelangelo Grosso, Iacopo Guglielminetti, Reza Khoshzaban, Matteo Sonza Reorda
2024	—	`conf`	Assessing the Reliability of Different Split Computing Neural Network Applications. LATS Giuseppe Esposito, Juan-David Guerrero-Balaguera, Josie E. Rodriguez Condia, Marco Levorato, Matteo Sonza Reorda
2024	C	`conf`	Early Detection of Permanent Faults in DNNs Through the Application of Tensor-Related Metrics. DDECS Vittorio Turco, Annachiara Ruospo, Ernesto Sánchez, Matteo Sonza Reorda
2024	C	`conf`	Effective Application-level Error Modeling of Permanent Faults on AI Accelerators. IOLTS Francesco Pessia, Juan-David Guerrero-Balaguera, Robert Limas Sierra, Josie E. Rodriguez Condia, Marco Levorato, Matteo Sonza Reorda
2024	C	`conf`	Enhancing the Reliability of Split Computing Deep Neural Networks. IOLTS Giuseppe Esposito, Juan-David Guerrero-Balaguera, Josie E. Rodriguez Condia, Marco Levorato, Matteo Sonza Reorda
2024	—	`conf`	Evaluating Different Fault Injection Abstractions on the Assessment of DNN SW Hardening Strategies. ATS Giuseppe Esposito, Juan-David Guerrero-Balaguera, Josie E. Rodriguez Condia, Matteo Sonza Reorda
2024	J	`jnl`	Evaluating Different Fault Injection Abstractions on the Assessment of DNN SW Hardening Strategies. CoRR Giuseppe Esposito, Juan-David Guerrero-Balaguera, Josie Esteban Rodriguez Condia, Matteo Sonza Reorda
2024	C	`conf`	Evaluating the Reliability of Integer Multipliers With Respect to Permanent Faults. DDECS Nikolaos Ioannis Deligiannis, Riccardo Cantoro, Matteo Sonza Reorda, Serag E.-D. Habib
2024	Misc	`conf`	Evaluating the Reliability of Supervised Compression for Split Computing. VTS Juan-David Guerrero-Balaguera, Josie E. Rodriguez Condia, Marco Levorato, Matteo Sonza Reorda
2024	C	`conf`	Fault Grading Techniques for Evaluating Software-Based Self-Test with Respect to Small Delay Defects. IOLTS Michelangelo Bartolomucci, Nikolaos Ioannis Deligiannis, Riccardo Cantoro, Matteo Sonza Reorda
2024	J	`jnl`	Investigating and Reducing the Architectural Impact of Transient Faults in Special Function Units for GPUs. J. Electron. Test. Josie E. Rodriguez Condia, Juan-David Guerrero-Balaguera, Edward Javier Patiño Nuñez, Robert Limas Sierra, Matteo Sonza Reorda
2024	C	`conf`	Reliability Assessment of Large DNN Models: Trading Off Performance and Accuracy. VLSI-SoC Junchao Chen, Giuseppe Esposito, Fernando Fernandes dos Santos, Juan-David Guerrero-Balaguera, Angeliki Kritikakou, Milos Krstic, Robert Limas Sierra, Josie E. Rodriguez Condia, Matteo Sonza Reorda, Marcello Traiola, Alessandro Veronesi
2024	Misc	`conf`	Special Session: Reliability Assessment Recipes for DNN Accelerators. VTS Mohammad Hasan Ahmadilivani, Alberto Bosio, Bastien Deveautour, Fernando Fernandes dos Santos, Juan-David Guerrero-Balaguera, Maksim Jenihhin, Angeliki Kritikakou, Robert Limas Sierra, Salvatore Pappalardo, Jaan Raik, Josie E. Rodriguez Condia, Matteo Sonza Reorda, Mahdi Taheri, Marcello Traiola
2024	—	`conf`	Special Session: Software-Based Self-Test Generation for RISC-V - Stuck-At Generation, Functional Cell-Aware Untestability, and FPGA Demonstration -. DFT Tobias Faller, Nikolaos Ioannis Deligiannis, Riccardo Cantoro, Matteo Sonza Reorda, Bernd Becker
2024	C	`conf`	TCC: GPGPU Architecture for Instruction Decoder and Control Flow Error Detection. DDECS Raghunandana K. K, Yogesh Prasad K. R, Matteo Sonza Reorda, Virendra Singh
2024	—	`conf`	TRRR: Accelerated Online Error Detecting and Correcting Fault Tolerant Architecture. EWDTS Raghunandana K. K, Yogesh Prasad K. R, Matteo Sonza Reorda, Virendra Singh
2023	J	`jnl`	A Low-Cost Burn-In Tester Architecture to Supply Effective Electrical Stress. IEEE Trans. Computers Francesco Angione, Davide Appello, Paolo Bernardi, Claudia Bertani, Giovambattista Gallo, Stefano Littardi, Giorgio Pollaccia, Walter Ruggeri, Matteo Sonza Reorda, Vincenzo Tancorre, Roberto Ugioli
2023	C	`conf`	A Reliability-aware Environment for Design Exploration for GPU Devices. DDECS Robert Limas Sierra, Juan-David Guerrero-Balaguera, Josie E. Rodriguez Condia, Matteo Sonza Reorda
2023	B	`conf`	A Survey of Recent Developments in Testability, Safety and Security of RISC-V Processors. ETS Jens Anders, Pablo Andreu, Bernd Becker, Steffen Becker, Riccardo Cantoro, Nikolaos Ioannis Deligiannis, Nourhan Elhamawy, Tobias Faller, Carles Hernández, Nele Mentens, Mahnaz Namazi Rizi, Ilia Polian, Abolfazl Sajadi, Matthias Sauer, Denis Schwachhofer, Matteo Sonza Reorda, Todor Stefanov, Ilya Tuzov, Stefan Wagner, Nusa Zidaric
2023	J	`jnl`	A Toolchain to Quantify Burn-In Stress Effectiveness on Large Automotive System-on-Chips. IEEE Access Francesco Angione, Davide Appello, Paolo Bernardi, Andrea Calabrese, Stefano Quer, Matteo Sonza Reorda, Vincenzo Tancorre, Roberto Ugioli
2023	—	`conf`	Analyzing the Architectural Impact of Transient Fault Effects in SFUs of GPUs. LATS Josie E. Rodriguez Condia, Juan-David Guerrero-Balaguera, Edward Javier Patiño Nuñez, Robert Limas Sierra, Matteo Sonza Reorda
2023	C	`conf`	Analyzing the Impact of Different Real Number Formats on the Structural Reliability of TCUs in GPUs. VLSI-SoC Robert Limas Sierra, Juan-David Guerrero-Balaguera, Josie E. Rodriguez Condia, Matteo Sonza Reorda
2023	—	`conf`	Analyzing the Reliability of TCUs Through Micro-architecture and Structural Evaluations for Two Real Number Formats. VLSI-SoC (Selected Papers) Robert Limas Sierra, Juan-David Guerrero-Balaguera, Josie E. Rodriguez Condia, Matteo Sonza Reorda
2023	A	`conf`	Assessing Convolutional Neural Networks Reliability through Statistical Fault Injections. DATE Annachiara Ruospo, Gabriele Gavarini, Corrado De Sio, Juan-David Guerrero-Balaguera, Luca Sterpone, Matteo Sonza Reorda, Ernesto Sánchez, Riccardo Mariani, Joseph Aribido, Jyotika Athavale
2023	—	`conf`	Automatic Identification of Functionally Untestable Cell-Aware Faults in Microprocessors. ATS Nikolaos Ioannis Deligiannis, Tobias Faller, Iacopo Guglielminetti, Riccardo Cantoro, Bernd Becker, Matteo Sonza Reorda
2023	B	`conf`	Automating the Generation of Functional Stress Inducing Stimuli for Burn-In Testing. ETS Nikolaos Ioannis Deligiannis, Tobias Faller, Chenghan Zhou, Riccardo Cantoro, Bernd Becker, Matteo Sonza Reorda
2023	J	`jnl`	Automating the Generation of Programs Maximizing the Repeatable Constant Switching Activity in Microprocessor Units via MaxSAT. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Nikolaos Ioannis Deligiannis, Tobias Faller, Riccardo Cantoro, Tobias Paxian, Bernd Becker, Matteo Sonza Reorda
2023	J	`jnl`	Automating the Generation of Programs Maximizing the Sustained Switching Activity in Microprocessor units via Evolutionary Techniques. Microprocess. Microsystems Nikolaos Ioannis Deligiannis, Riccardo Cantoro, Matteo Sonza Reorda
2023	C	`conf`	Collecting diagnostic information through dichotomic search from Logic BIST of failing in-field automotive SoCs with delay faults. DDECS Paolo Bernardi, Gabriele Filipponi, Matteo Sonza Reorda, Davide Appello, Claudia Bertani, Vincenzo Tancorre
2023	B	`conf`	Constraint-Based Automatic SBST Generation for RISC-V Processor Families. ETS Tobias Faller, Nikolaos Ioannis Deligiannis, Markus Schwörer, Matteo Sonza Reorda, Bernd Becker
2023	—	`conf`	DDSR: An Online GPGPU Instruction Decoder Error Detecting and Correcting Architecture. DFT Raghunandana K. K, Yogesh Prasad K. R, Matteo Sonza Reorda, Virendra Singh
2023	—	`conf`	Evaluating the Impact of Aging on Path-Delay Self-Test Libraries. DFT Riccardo Cantoro, Sandro Sartoni, Matteo Sonza Reorda, Lorena Anghel, Michele Portolan
2023	Misc	`conf`	Evaluating the Impact of Transition Delay Faults in GPUs. VLSID Josie E. Rodriguez Condia, Matteo Sonza Reorda
2023	B	`conf`	Evaluating the Prevalence of SFUs in the Reliability of GPUs. ETS Josie E. Rodriguez Condia, Juan-David Guerrero-Balaguera, Edward Javier Patiño Nuñez, Robert Limas Sierra, Matteo Sonza Reorda
2023	—	`conf`	Functional Testing with STLs: A Step Towards Reliable RISC-V-based HPC Commodity Clusters. ISC Workshops Josie E. Rodriguez Condia, Nikolaos Ioannis Deligiannis, Jacopo Sini, Riccardo Cantoro, Matteo Sonza Reorda
2023	B	`conf`	Image Test Libraries for the on-line self-test of functional units in GPUs running CNNs. ETS Annachiara Ruospo, Gabriele Gavarini, A. Porsia, Matteo Sonza Reorda, Ernesto Sánchez, Riccardo Mariani, Joseph Aribido, Jyotika Athavale
2023	—	`conf`	On the integration and hardening of Software Test Libraries in Real-Time Operating Systems. LATS Francesco Angione, Paolo Bernardi, Riccardo Cantoro, Nicola Di Gruttola Giardino, Davide Piumatti, Matteo Sonza Reorda, Davide Appello, Vincenzo Tancorre
2023	—	`conf`	RISC-V-Based Platforms for HPC: Analyzing Non-functional Properties for Future HPC and Big-Data Clusters. SAMOS William Fornaciari, Federico Reghenzani, Federico Terraneo, Davide Baroffio, Cecilia Metra, Martin Omaña, Josie E. Rodriguez Condia, Matteo Sonza Reorda, Robert Birke, Iacopo Colonnelli, Gianluca Mittone, Marco Aldinucci, Gabriele Mencagli, Francesco Iannone, Filippo Palombi, Giuseppe Zummo, Daniele Cesarini, Federico Tesser
2023	—	`conf`	Reliability Estimation of Split DNN Models for Distributed Computing in IoT Systems. ISIE Juan-David Guerrero-Balaguera, Ian Harshbarger, Josie E. Rodriguez Condia, Marco Levorato, Matteo Sonza Reorda
2023	J	`jnl`	STLs for GPUs: Using High-Level Language Approaches. IEEE Des. Test Juan-David Guerrero-Balaguera, Josie E. Rodriguez Condia, Matteo Sonza Reorda
2023	J	`jnl`	Self-Test Library Generation for In-Field Test of Path Delay Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Lorena Anghel, Riccardo Cantoro, Riccardo Masante, Michele Portolan, Sandro Sartoni, Matteo Sonza Reorda
2023	C	`conf`	TREFU: An Online Error Detecting and Correcting Fault Tolerant GPGPU Architecture. IOLTS Raghunandana K. K, B. K. S. V. L. Varaprasad, Matteo Sonza Reorda, Virendra Singh
2023	C	`conf`	Targeting different defect-oriented fault models in IC testing: an experimental approach. DSD Nunzio Mirabella, Andrea Floridia, Riccardo Cantoro, Michelangelo Grosso, Matteo Sonza Reorda
2023	—	`conf`	Uncovering hidden vulnerabilities in CNNs through evolutionary-based Image Test Libraries. DFT Vittorio Turco, Annachiara Ruospo, Gabriele Gavarini, Ernesto Sánchez, Matteo Sonza Reorda
2023	A	`conf`	Understanding the Effects of Permanent Faults in GPU's Parallelism Management and Control Units. SC Juan-David Guerrero-Balaguera, Josie Esteban Rodriguez Condia, Fernando Fernandes dos Santos, Matteo Sonza Reorda, Paolo Rech
2023	J	`jnl`	Understanding the Effects of Permanent Faults in GPU's Parallelism Management and Control Units. CoRR Juan-David Guerrero-Balaguera, Josie E. Rodriguez Condia, Fernando Fernandes dos Santos, Matteo Sonza Reorda, Paolo Rech
2023	J	`jnl`	Using STLs for Effective In-Field Test of GPUs. IEEE Des. Test Josie E. Rodriguez Condia, Felipe Augusto da Silva, Ahmet Çagri Bagbaga, Juan-David Guerrero-Balaguera, Said Hamdioui, Christian Sauer, Matteo Sonza Reorda
2022	A	`conf`	A Compaction Method for STLs for GPU in-field test. DATE Juan-David Guerrero-Balaguera, Josie E. Rodriguez Condia, Matteo Sonza Reorda
2022	A	`conf`	A Multi-level Approach to Evaluate the Impact of GPU Permanent Faults on CNN's Reliability. ITC Josie E. Rodriguez Condia, Juan-David Guerrero-Balaguera, Fernando Fernandes dos Santos, Matteo Sonza Reorda, Paolo Rech
2022	Misc	`conf`	A New Method to Generate Software Test Libraries for In-Field GPU Testing Resorting to High-Level Languages. VTS Juan-David Guerrero-Balaguera, Josie E. Rodriguez Condia, Matteo Sonza Reorda
2022	—	`conf`	A comparative overview of ATPG flows targeting traditional and cell-aware fault models. ICECS 2022 Nunzio Mirabella, Andrea Floridia, Riccardo Cantoro, Michelangelo Grosso, Matteo Sonza Reorda
2022	—	`conf`	A novel Pattern Selection Algorithm to reduce the Test Cost of large Automotive Systems-on-Chip. LATS Giusy Iaria, Francesco Angione, Paolo Bernardi, Matteo Sonza Reorda, Davide Appello, Giuseppe Garozzo, Vincenzo Tancorre
2022	—	`conf`	A novel SEU injection setup for Automotive SoC. ISIE Giusy Iaria, Tommaso Foscale, Paolo Bernardi, Luca Presicce, Matteo Sonza Reorda, Davide Appello, Vincenzo Tancorre, Roberto Ugioli
2022	B	`conf`	An Optimized Burn-In Stress Flow targeting Interconnections logic to Embedded Memories in Automotive Systems-on-Chip. ETS Francesco Angione, Paolo Bernardi, Gabriele Filipponi, Matteo Sonza Reorda, Davide Appello, Vincenzo Tancorre, Roberto Ugioli
2022	J	`jnl`	Characterizing a Neutron-Induced Fault Model for Deep Neural Networks. CoRR Fernando Fernandes dos Santos, Angeliki Kritikakou, Josie Esteban Rodriguez Condia, Juan-David Guerrero-Balaguera, Matteo Sonza Reorda, Olivier Sentieys, Paolo Rech
2022	C	`conf`	Effective fault simulation of GPU's permanent faults for reliability estimation of CNNs. IOLTS Juan-David Guerrero-Balaguera, Robert Limas Sierra, Matteo Sonza Reorda
2022	B	`conf`	Effective techniques for automatically improving the transition delay fault coverage of Self-Test Libraries. ETS Riccardo Cantoro, Francesco Garau, Patrick Girard, Nima Kolahimahmoudi, Sandro Sartoni, Matteo Sonza Reorda, Arnaud Virazel
2022	J	`jnl`	Evaluating low-level software-based hardening techniques for configurable GPU architectures. J. Supercomput. Marcio M. Gonçalves, Josie E. Rodriguez Condia, Matteo Sonza Reorda, Luca Sterpone, José Rodrigo Azambuja
2022	—	`conf`	Evaluating the impact of Permanent Faults in a GPU running a Deep Neural Network. ITC-Asia Juan-David Guerrero-Balaguera, Luigi Galasso, Robert Limas Sierra, Ernesto Sánchez, Matteo Sonza Reorda
2022	Misc	`conf`	Exploiting post-silicon debug hardware to improve the fault coverage of Software Test Libraries. VTS Riccardo Cantoro, Francesco Garau, Riccardo Masante, Sandro Sartoni, Virendra Singh, Matteo Sonza Reorda
2022	—	`conf`	Improving the Fault Resilience of Neural Network Applications Through Security Mechanisms. DSN (Supplements) Nikolaos Ioannis Deligiannis, Riccardo Cantoro, Matteo Sonza Reorda, Marcello Traiola, Emanuele Valea
2022	A	`conf`	In-field Data Collection System through Logic BIST for large Automotive Systems-on-Chip. ITC Gabriele Filipponi, Giusy Iaria, Matteo Sonza Reorda, Davide Appello, Giuseppe Garozzo, Vincenzo Tancorre
2022	B	`conf`	Machine Learning for Test, Diagnosis, Post-Silicon Validation and Yield Optimization. ETS Hussam Amrouch, Krishnendu Chakrabarty, Dirk Pflüger, Ilia Polian, Matthias Sauer, Matteo Sonza Reorda
2022	—	`conf`	Microarchitectural Reliability Evaluation of a Block Scheduling Controller in GPUs. ISVLSI Josie E. Rodriguez Condia, Riccardo Faggiano, Matteo Sonza Reorda
2022	—	`conf`	Neural Network's Reliability to Permanent Faults: Analyzing the Impact of Performance Optimizations in GPUs. ICECS 2022 Juan-David Guerrero-Balaguera, Josie E. Rodriguez Condia, Matteo Sonza Reorda
2022	—	`conf`	Online scheduling of concurrent Memory BISTs execution at Real-Time Operating-System level. DFT Francesco Angione, Paolo Bernardi, Gabriele Filipponi, Claudia Tempesta, Matteo Sonza Reorda, Davide Appello, Vincenzo Tancorre, Roberto Ugioli
2022	—	`conf`	REFU: Redundant Execution with Idle Functional Units, Fault Tolerant GPGPU architecture. ISVLSI Raghunandana K. K, B. K. S. V. L. Varaprasad, Matteo Sonza Reorda, Virendra Singh
2022	C	`conf`	Recent Trends and Perspectives on Defect-Oriented Testing. IOLTS Paolo Bernardi, Riccardo Cantoro, Anthony Coyette, W. Dobbeleare, Moritz Fieback, Andrea Floridia, G. Gielenk, Jhon Gomez, Michelangelo Grosso, Andrea Guerriero, Iacopo Guglielminetti, Said Hamdioui, Giorgio Insinga, N. Mautone, Nunzio Mirabella, Sandro Sartoni, Matteo Sonza Reorda, Rudolf Ullmann, Ronny Vanhooren, N. Xamak, Lizhou Wu
2022	—	`conf`	Reliability Assessment of Neural Networks in GPUs: A Framework For Permanent Faults Injections. ISIE Juan-David Guerrero-Balaguera, Luigi Galasso, Robert Limas Sierra, Matteo Sonza Reorda
2022	J	`jnl`	Reliability Assessment of Neural Networks in GPUs: A Framework For Permanent Faults Injections. CoRR Juan-David Guerrero-Balaguera, Luigi Galasso, Robert Limas Sierra, Matteo Sonza Reorda
2022	B	`conf`	Test, Reliability and Functional Safety Trends for Automotive System-on-Chip. ETS Francesco Angione, Davide Appello, Joseph Aribido, Jyotika Athavale, Nicolò Bellarmino, Paolo Bernardi, Riccardo Cantoro, Corrado De Sio, Tommaso Foscale, Gabriele Gavarini, Juan-David Guerrero-Balaguera, Martin Huch, Giusy Iaria, Tobias Kilian, Riccardo Mariani, Raffaele Martone, Annachiara Ruospo, Ernesto Sánchez, Ulf Schlichtmann, Giovanni Squillero, Matteo Sonza Reorda, Luca Sterpone, Vincenzo Tancorre, Roberto Ugioli
2022	—	`conf`	Using Formal Methods to Support the Development of STLs for GPUs. ATS Nikolaos Ioannis Deligiannis, Tobias Faller, Josie E. Rodriguez Condia, Riccardo Cantoro, Bernd Becker, Matteo Sonza Reorda
2021	—	`conf`	A Novel Compaction Approach for SBST Test Programs. ATS Juan-David Guerrero-Balaguera, Josie E. Rodriguez Condia, Matteo Sonza Reorda
2021	J	`jnl`	A Novel Compaction Approach for SBST Test Programs. CoRR Juan-David Guerrero-Balaguera, Josie E. Rodriguez Condia, Matteo Sonza Reorda
2021	Misc	`conf`	Combining Architectural Simulation and Software Fault Injection for a Fast and Accurate CNNs Reliability Evaluation on GPUs. VTS Josie E. Rodriguez Condia, Fernando Fernandes dos Santos, Matteo Sonza Reorda, Paolo Rech
2021	—	`conf`	Comparing different solutions for testing resistive defects in low-power SRAMs. LATS Nunzio Mirabella, Michelangelo Grosso, Giovanna Franchino, Salvatore Rinaudo, Ioannis Deretzis, Antonino La Magna, Matteo Sonza Reorda
2021	J	`jnl`	Comparing different solutions for testing resistive defects in low-power SRAMs. CoRR Nunzio Mirabella, Michelangelo Grosso, Giovanna Franchino, Salvatore Rinaudo, Ioannis Deretzis, Antonino La Magna, Matteo Sonza Reorda
2021	J	`jnl`	DYRE: a DYnamic REconfigurable solution to increase GPGPU's reliability. J. Supercomput. Josie E. Rodriguez Condia, Pierpaolo Narducci, Matteo Sonza Reorda, Luca Sterpone
2021	—	`conf`	Effective SAT-based Solutions for Generating Functional Sequences Maximizing the Sustained Switching Activity in a Pipelined Processor. ATS Nikolaos Ioannis Deligiannis, Riccardo Cantoro, Tobias Faller, Tobias Paxian, Bernd Becker, Matteo Sonza Reorda
2021	J	`jnl`	Exploring the Mysteries of System-Level Test. CoRR Ilia Polian, Jens Anders, Steffen Becker, Paolo Bernardi, Krishnendu Chakrabarty, Nourhan Elhamawy, Matthias Sauer, Adit D. Singh, Matteo Sonza Reorda, Stefan Wagner
2021	J	`jnl`	Guest Editors' Introduction: SBCCI 2019. IEEE Des. Test Marcelo Lubaszewki, Matteo Sonza Reorda
2021	—	`conf`	Innovative methods for Burn-In related Stress Metrics Computation. DTIS Walter Ruggeri, Paolo Bernardi, Stefano Littardi, Matteo Sonza Reorda, Davide Appello, Claudia Bertani, Giorgio Pollaccia, Vincenzo Tancorre, Roberto Ugioli
2021	C	`conf`	Maximizing the Switching Activity of Different Modules Within a Processor Core via Evolutionary Techniques. DSD Nikolaos Ioannis Deligiannis, Riccardo Cantoro, Matteo Sonza Reorda
2021	Misc	`conf`	New Techniques for the Automatic Identification of Uncontrollable Lines in a CPU Core. VTS Nikolaos Ioannis Deligiannis, Riccardo Cantoro, Matthias Sauer, Bernd Becker, Matteo Sonza Reorda
2021	C	`conf`	On the Functional Test of Special Function Units in GPUs. DDECS Juan-David Guerrero-Balaguera, Josie E. Rodriguez Condia, Matteo Sonza Reorda
2021	C	`conf`	Protecting GPU's Microarchitectural Vulnerabilities via Effective Selective Hardening. IOLTS Josie E. Rodriguez Condia, Paolo Rech, Fernando Fernandes dos Santos, Luigi Carro, Matteo Sonza Reorda
2021	A	`conf`	Revealing GPUs Vulnerabilities by Combining Register-Transfer and Software-Level Fault Injection. DSN Fernando Fernandes dos Santos, Josie E. Rodriguez Condia, Luigi Carro, Matteo Sonza Reorda, Paolo Rech
2021	C	`conf`	Self-Test Libraries Analysis for Pipelined Processors Transition Fault Coverage Improvement. IOLTS Riccardo Cantoro, Patrick Girard, Riccardo Masante, Sandro Sartoni, Matteo Sonza Reorda, Arnaud Virazel
2021	C	`conf`	System-Level Test: State of the Art and Challenges. IOLTS Davide Appello, H. H. Chen, Matthias Sauer, Ilia Polian, Paolo Bernardi, Matteo Sonza Reorda
2021	J	`jnl`	Towards the Integration of Reliability and Security Mechanisms to Enhance the Fault Resilience of Neural Networks. IEEE Access Nikolaos Ioannis Deligiannis, Riccardo Cantoro, Matteo Sonza Reorda, Marcello Traiola, Emanuele Valea
2021	—	`conf`	Using Hardware Performance Counters to support infield GPU Testing. ICECS Juan-David Guerrero-Balaguera, Josie E. Rodriguez Condia, Matteo Sonza Reorda
2020	J	`jnl`	A Novel Sequence Generation Approach to Diagnose Faults in Reconfigurable Scan Networks. IEEE Trans. Computers Riccardo Cantoro, Aleksa Damljanovic, Matteo Sonza Reorda, Giovanni Squillero
2020	C	`conf`	A dynamic hardware redundancy mechanism for the in-field fault detection in cores of GPGPUs. DDECS Josie E. Rodriguez Condia, Pierpaolo Narducci, Matteo Sonza Reorda, Luca Sterpone
2020	Misc	`conf`	A dynamic reconfiguration mechanism to increase the reliability of GPGPUs. VTS Josie E. Rodriguez Condia, Pierpaolo Narducci, Matteo Sonza Reorda, Luca Sterpone
2020	J	`jnl`	An On-Line Testing Technique for the Scheduler Memory of a GPGPU. IEEE Access Stefano Di Carlo, Josie E. Rodriguez Condia, Matteo Sonza Reorda
2020	—	`conf`	Analyzing the Sensitivity of GPU Pipeline Registers to Single Events Upsets. ISVLSI Josie E. Rodriguez Condia, Marcio Gonçalves, José Rodrigo Azambuja, Matteo Sonza Reorda, Luca Sterpone
2020	C	`conf`	Applicative System Level Test introduction to Increase Confidence on Screening Quality. DDECS Paolo Bernardi, Marco Restifo, Matteo Sonza Reorda, Davide Appello, Claudia Bertani, D. Petrali
2020	B	`conf`	Determined-Safe Faults Identification: A step towards ISO26262 hardware compliant designs. ETS Felipe Augusto da Silva, Ahmet Cagri Bagbaba, Sandro Sartoni, Riccardo Cantoro, Matteo Sonza Reorda, Said Hamdioui, Christian Sauer
2020	—	`conf`	Evaluating Data Encryption Effects on the Resilience of an Artificial Neural Network. DFT Riccardo Cantoro, Nikolaos Ioannis Deligiannis, Matteo Sonza Reorda, Marcello Traiola, Emanuele Valea
2020	—	`conf`	Evaluating Software-based Hardening Techniques for General-Purpose Registers on a GPGPU. LATS Marcio Gonçalves, José Rodrigo Azambuja, Josie E. Rodriguez Condia, Matteo Sonza Reorda, Luca Sterpone
2020	—	`conf`	Evaluating the Code Encryption Effects on Memory Fault Resilience. LATS Riccardo Cantoro, Nikolaos Ioannis Deligiannis, Matteo Sonza Reorda, Marcello Traiola, Emanuele Valea
2020	—	`conf`	Exploring the Mysteries of System-Level Test. ATS Ilia Polian, Jens Anders, Steffen Becker, Paolo Bernardi, Krishnendu Chakrabarty, Nourhan Elhamawy, Matthias Sauer, Adit D. Singh, Matteo Sonza Reorda, Stefan Wagner
2020	J	`jnl`	Guest Editor's Introduction: Special Section on High Dependability Systems. IEEE Trans. Emerg. Top. Comput. Cecilia Metra, Matteo Sonza Reorda
2020	Misc	`conf`	In-field Functional Test of CAN Bus Controllers. VTS Riccardo Cantoro, Sandro Sartoni, Matteo Sonza Reorda
2020	—	`conf`	Modular Functional Testing: Targeting the Small Embedded Memories in GPUs. VLSI-SoC (Selected Papers) Josie Esteban Rodriguez Condia, Matteo Sonza Reorda
2020	A	`conf`	New Perspectives on Core In-field Path Delay Test. ITC Riccardo Cantoro, Dario Foti, Sandro Sartoni, Matteo Sonza Reorda, Lorena Anghel, Michele Portolan
2020	J	`jnl`	New categories of Safe Faults in a processor-based Embedded System. CoRR Cemil Cem Gürsoy, Maksim Jenihhin, Adeboye Stephen Oyeniran, Davide Piumatti, Jaan Raik, Matteo Sonza Reorda, Raimund Ubar
2020	C	`conf`	On the testing of special memories in GPGPUs. IOLTS Josie E. Rodriguez Condia, Matteo Sonza Reorda
2020	A	`conf`	RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems. DATE Maksim Jenihhin, Said Hamdioui, Matteo Sonza Reorda, Milos Krstic, Peter Langendörfer, Christian Sauer, Anton Klotz, Michael Hübner, Jörg Nolte, Heinrich Theodor Vierhaus, Georgios N. Selimis, Dan Alexandrescu, Mottaqiallah Taouil, Geert Jan Schrijen, Jaan Raik, Luca Sterpone, Giovanni Squillero, Zoya Dyka
2020	Misc	`conf`	Special Session: AutoSoC - A Suite of Open-Source Automotive SoC Benchmarks. VTS Felipe Augusto da Silva, Ahmet Cagri Bagbaba, Annachiara Ruospo, Riccardo Mariani, Ghani Kanawati, Ernesto Sánchez, Matteo Sonza Reorda, Maksim Jenihhin, Said Hamdioui, Christian Sauer
2020	—	`conf`	Testing Heatsink Faults in Power Transistors by means of Thermal Model. LATS Davide Piumatti, Matteo Vincenzo Quitadamo, Matteo Sonza Reorda, Franco Fiori
2020	C	`conf`	Testing the Divergence Stack Memory on GPGPUs: A Modular in-Field Test Strategy. VLSI-SOC Josie E. Rodriguez Condia, Matteo Sonza Reorda
2019	B	`conf`	A Dynamic Greedy Test Scheduler for Optimizing Probe Motion in In-Circuit Testers. ETS Luciano Bonaria, Maurizio Raganato, Matteo Sonza Reorda, Giovanni Squillero
2019	—	`conf`	About Performance Faults in Microprocessor Core in-field Testing. LASCAS Julio Pérez Acle, Ernesto Sánchez, Matteo Sonza Reorda
2019	J	`jnl`	An Enhanced Evolutionary Technique for the Generation of Compact Reconfigurable Scan-Network Tests. J. Circuits Syst. Comput. Riccardo Cantoro, Aleksa Damljanovic, Matteo Sonza Reorda, Giovanni Squillero
2019	—	`conf`	An extended model to support detailed GPGPU reliability analysis. DTIS Boyang Du, Josie E. Rodriguez Condia, Matteo Sonza Reorda
2019	—	`conf`	Assessing the Effectiveness of the Test of Power Devices at the Board Level. DCIS Davide Piumatti, Stefano Borlo, Fabio Mandrile, Matteo Sonza Reorda, Radu Bojoi
2019	—	`conf`	Challenges of Reliability Assessment and Enhancement in Autonomous Systems. DFT Maksim Jenihhin, Matteo Sonza Reorda, Aneesh Balakrishnan, Dan Alexandrescu
2019	J	`jnl`	Challenges of Reliability Assessment and Enhancement in Autonomous Systems. CoRR Maksim Jenihhin, Matteo Sonza Reorda, Aneesh Balakrishnan, Dan Alexandrescu
2019	C	`conf`	Effective Screening of Automotive SoCs by Combining Burn-In and System Level Test. DDECS F. Almeida, Paolo Bernardi, D. Calabrese, Marco Restifo, Matteo Sonza Reorda, Davide Appello, Giorgio Pollaccia, Vincenzo Tancorre, Roberto Ugioli, Gulio Zoppi
2019	J	`jnl`	Fault Grading Techniques of Software Test Libraries for Safety-Critical Applications. IEEE Access Andrea Floridia, Ernesto Sánchez, Matteo Sonza Reorda
2019	A	`conf`	IEEE European Test Symposium (ETS). ITC Stephan Eggersglüß, Said Hamdioui, Artur Jutman, Maria K. Michael, Jaan Raik, Matteo Sonza Reorda, Mehdi Baradaran Tahoori, Elena-Ioana Vatajelu
2019	C	`conf`	New categories of Safe Faults in a processor-based Embedded System. DDECS Cemil Cem Gürsoy, Maksim Jenihhin, Adeboye Stephen Oyeniran, Davide Piumatti, Jaan Raik, Matteo Sonza Reorda, Raimund Ubar
2019	—	`conf`	On the evaluation of SEU effects in GPGPUs. LATS Boyang Du, Josie E. Rodriguez Condia, Matteo Sonza Reorda, Luca Sterpone
2019	C	`conf`	On the in-field test of the GPGPU scheduler memory. DDECS Stefano Di Carlo, Josie E. Rodriguez Condia, Matteo Sonza Reorda
2019	—	`ed.`	Proceedings of the 32nd Symposium on Integrated Circuits and Systems Design, SBCCI 2019, Sao Paulo, Brazil, August 26-30, 2019. SBCCI João Antonio Martino, Marcelo Lubaszewski, Matteo Sonza Reorda
2019	J	`jnl`	RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems. CoRR Maksim Jenihhin, Said Hamdioui, Matteo Sonza Reorda, Milos Krstic, Peter Langendörfer, Christian Sauer, Anton Klotz, Michael Hübner, Jörg Nolte, Heinrich Theodor Vierhaus, Georgios N. Selimis, Dan Alexandrescu, Mottaqiallah Taouil, Geert Jan Schrijen, Jaan Raik, Luca Sterpone, Giovanni Squillero, Zoya Dyka
2019	—	`conf`	Software-Based Self-Test for Delay Faults. VLSI-SoC (Selected Papers) Michelangelo Grosso, Matteo Sonza Reorda, Salvatore Rinaudo
2019	C	`conf`	Software-Based Self-Test for Transition Faults: a Case Study. VLSI-SoC Michelangelo Grosso, Salvatore Rinaudo, Andrea Casalino, Matteo Sonza Reorda
2019	—	`conf`	Test-Plan Optimization for Flying-Probes In-Circuit Testers. ITC-Asia Luciano Bonaria, Maurizio Raganato, Giovanni Squillero, Matteo Sonza Reorda
2019	C	`conf`	Testing permanent faults in pipeline registers of GPGPUs: A multi-kernel approach. IOLTS Josie E. Rodriguez Condia, Matteo Sonza Reorda
2019	—	`conf`	Untestable faults identification in GPGPUs for safety-critical applications. ICECS Josie E. Rodriguez Condia, Felipe Augusto da Silva, Said Hamdioui, Christian Sauer, Matteo Sonza Reorda
2019	—	`ed.`	VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things - 25th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, October 23-25, 2017, Revised and Extended Selected Papers VLSI-SoC (Selected Papers) Michail Maniatakos, Ibrahim Abe M. Elfadel, Matteo Sonza Reorda, H. Fatih Ugurdag, José Monteiro, Ricardo Reis
2018	A	`conf`	A New Technique to Generate Test Sequences for Reconfigurable Scan Networks. ITC Riccardo Cantoro, Aleksa Damljanovic, Matteo Sonza Reorda, Giovanni Squillero
2018	—	`conf`	A Semi-Formal Technique to Generate Effective Test Sequences for Reconfigurable Scan Networks. ITC-Asia Riccardo Cantoro, Aleksa Damljanovic, Matteo Sonza Reorda, Giovanni Squillero
2018	—	`conf`	About on-line functionally untestable fault identification in microprocessor cores for safety-critical applications. LATS Riccardo Cantoro, Andrea Firrincieli, Davide Piumatti, Marco Restifo, Ernesto Sánchez, Matteo Sonza Reorda
2018	C	`conf`	About the functional test of the GPGPU scheduler. IOLTS Boyang Du, Josie E. Rodriguez Condia, Matteo Sonza Reorda, Luca Sterpone
2018	C	`conf`	An Evolutionary Technique for Reducing the Duration of Reconfigurable Scan Network Test. DDECS Riccardo Cantoro, Luigi San Paolo, Matteo Sonza Reorda, Giovanni Squillero
2018	C	`conf`	An analysis of test solutions for COTS-based systems in space applications. VLSI-SoC Riccardo Cantoro, Sara Carbonara, Andrea Floridia, Ernesto Sánchez, Matteo Sonza Reorda, Jan-Gerd Mess
2018	—	`conf`	Assessing Test Procedure Effectiveness for Power Devices. DCIS Davide Piumatti, Matteo Sonza Reorda
2018	C	`conf`	Fault-Independent Test-Generation for Software-Based Self-Testing. IOLTS Panagiotis Georgiou, Xrysovalantis Kavousianos, Riccardo Cantoro, Matteo Sonza Reorda
2018	—	`conf`	Improved Test Solutions for COTS-Based Systems in Space Applications. VLSI-SoC (Selected Papers) Riccardo Cantoro, Sara Carbonara, Andrea Floridia, Ernesto Sánchez, Matteo Sonza Reorda, Jan-Gerd Mess
2018	C	`conf`	On the test of a COTS-based system for space applications. IOLTS Sara Carbonara, Andrea Firrincieli, Matteo Sonza Reorda, Jan-Gerd Mess
2018	—	`conf`	RESCUE: Cross-Sectoral PhD Training Concept for Interdependent Reliability, Security and Quality. EWME Heinrich Theodor Vierhaus, Maksim Jenihhin, Matteo Sonza Reorda
2018	J	`jnl`	Scan-Chain Intra-Cell Aware Testing. IEEE Trans. Emerg. Top. Comput. Aymen Touati, Alberto Bosio, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda, Etienne Auvray
2018	J	`jnl`	Test of Reconfigurable Modules in Scan Networks. IEEE Trans. Computers Riccardo Cantoro, Farrokh Ghani Zadegan, Marco Palena, Paolo Pasini, Erik Larsson, Matteo Sonza Reorda
2018	C	`conf`	Towards an automatic approach for hardware verification according to ISO 26262 functional safety standard. IOLTS Jacopo Sini, Matteo Sonza Reorda, Massimo Violante, Peter Sarson
2017	J	`jnl`	A High-Level Approach to Analyze the Effects of Soft Errors on Lossless Compression Algorithms. J. Electron. Test. Serhiy Avramenko, Matteo Sonza Reorda, Massimo Violante, Görschwin Fey
2017	J	`jnl`	A Low-Cost Reliability vs. Cost Trade-Off Methodology to Selectively Harden Logic Circuits. J. Electron. Test. Imran Wali, Bastien Deveautour, Arnaud Virazel, Alberto Bosio, Patrick Girard, Matteo Sonza Reorda
2017	J	`jnl`	An Error-Detection and Self-Repairing Method for Dynamically and Partially Reconfigurable Systems. IEEE Trans. Computers Matteo Sonza Reorda, Luca Sterpone, Anees Ullah
2017	—	`conf`	An automatic approach to perform the verification of hardware designs according to the ISO26262 functional safety standard. LATS Enea Bagalini, Jacopo Sini, Matteo Sonza Reorda, Massimo Violante, H. Klimesch, Peter Sarson
2017	A	`conf`	BASTION: Board and SoC test instrumentation for ageing and no failure found. DATE Artur Jutman, Christophe Lotz, Erik Larsson, Matteo Sonza Reorda, Maksim Jenihhin, Jaan Raik, Hans G. Kerkhoff, Rene Krenz-Baath, Piet Engelke
2017	J	`jnl`	Microprocessor Testing: Functional Meets Structural Test. J. Circuits Syst. Comput. Aymen Touati, Alberto Bosio, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda
2017	J	`jnl`	New Techniques to Reduce the Execution Time of Functional Test Programs. IEEE Trans. Computers Marco Gaudesi, Irith Pomeranz, Matteo Sonza Reorda, Giovanni Squillero
2017	—	`conf`	On the detection of board delay faults through the execution of functional programs. LATS Gaiping An, Riccardo Cantoro, Ernesto Sánchez, Matteo Sonza Reorda
2017	C	`conf`	On the in-field test of embedded memories. IOLTS Paolo Bernardi, Marco Restifo, Ernesto Sánchez, Matteo Sonza Reorda
2017	—	`conf`	On the optimization of SBST test program compaction. DFT R. Cantora, Ernesto Sánchez, Matteo Sonza Reorda, Giovanni Squillero, Emanuele Valea
2017	—	`conf`	Towards Making Fault Injection on Abstract Models a More Accurate Tool for Predicting RT-Level Effects. ISVLSI Tino Flenker, Jan Malburg, Görschwin Fey, Serhiy Avramenko, Massimo Violante, Matteo Sonza Reorda
2016	J	`jnl`	A Fault-Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors. ACM J. Emerg. Technol. Comput. Syst. Hassan Ghasemzadeh Mohammadi, Pierre-Emmanuel Gaillardon, Jian Zhang, Giovanni De Micheli, Ernesto Sánchez, Matteo Sonza Reorda
2016	J	`jnl`	A Flexible Framework for the Automatic Generation of SBST Programs. IEEE Trans. Very Large Scale Integr. Syst. Andreas Riefert, Riccardo Cantoro, Matthias Sauer, Matteo Sonza Reorda, Bernd Becker
2016	J	`jnl`	A Hybrid Fault-Tolerant Architecture for Highly Reliable Processing Cores. J. Electron. Test. Imran Wali, Arnaud Virazel, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Matteo Sonza Reorda
2016	B	`conf`	A low-cost susceptibility analysis methodology to selectively harden logic circuits. ETS Imran Wali, Bastien Deveautour, Arnaud Virazel, Alberto Bosio, Patrick Girard, Matteo Sonza Reorda
2016	A	`conf`	A suite of IEEE 1687 benchmark networks. ITC Anton Tsertov, Artur Jutman, Sergei Devadze, Matteo Sonza Reorda, Erik Larsson, Farrokh Ghani Zadegan, Riccardo Cantoro, Mehrdad Montazeri, Rene Krenz-Baath
2016	C	`conf`	An effective approach for functional test programs compaction. DDECS Aymen Touati, Alberto Bosio, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda
2016	—	`conf`	Analysis of the effects of soft errors on compression algorithms through fault injection inside program variables. LATS Serhiy Avramenko, Matteo Sonza Reorda, Massimo Violante, Görschwin Fey
2016	C	`conf`	Automatic generation of stimuli for fault diagnosis in IEEE 1687 networks. IOLTS Riccardo Cantoro, Mehrdad Montazeri, Matteo Sonza Reorda, Farrokh Ghani Zadegan, Erik Larsson
2016	Misc	`conf`	Effective generation and evaluation of diagnostic SBST programs. VTS Andreas Riefert, Riccardo Cantoro, Matthias Sauer, Matteo Sonza Reorda, Bernd Becker
2016	C	`conf`	FPGA-controlled PCBA power-on self-test using processor's debug features. DDECS Boyang Du, Ernesto Sánchez, Matteo Sonza Reorda, Julio Pérez Acle, Anton Tsertov
2016	—	`conf`	Hybrid soft error mitigation techniques for COTS processor-based systems. LATS Eduardo Chielle, Boyang Du, Fernanda Lima Kastensmidt, Sergio Cuenca-Asensi, Luca Sterpone, Matteo Sonza Reorda
2016	J	`jnl`	Identification and Rejuvenation of NBTI-Critical Logic Paths in Nanoscale Circuits. J. Electron. Test. Maksim Jenihhin, Giovanni Squillero, Thiago Santos Copetti, Valentin Tihhomirov, Sergei Kostin, Marco Gaudesi, Fabian Vargas, Jaan Raik, Matteo Sonza Reorda, Leticia Bolzani Poehls, Raimund Ubar, Guilherme Cardoso Medeiros
2016	—	`conf`	Improving the Functional Test Delay Fault Coverage: A Microprocessor Case Study. ISVLSI Aymen Touati, Alberto Bosio, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda
2016	J	`jnl`	Observability solutions for in-field functional test of processor-based systems: A survey and quantitative test case evaluation. Microprocess. Microsystems Julio Pérez Acle, Riccardo Cantoro, Ernesto Sánchez, Matteo Sonza Reorda, Giovanni Squillero
2016	B	`conf`	On the diagnostic analysis of IEEE 1687 networks. ETS Riccardo Cantoro, Mehrdad Montazeri, Matteo Sonza Reorda, Farrokh Ghani Zadegan, Erik Larsson
2016	C	`conf`	On the robustness of DCT-based compression algorithms for space applications. IOLTS Serhiy Avramenko, Matteo Sonza Reorda, Massimo Violante, Görschwin Fey, Jan-Gerd Mess, Robert Schmidt
2016	J	`jnl`	Online Test of Control Flow Errors: A New Debug Interface-Based Approach. IEEE Trans. Computers Boyang Du, Matteo Sonza Reorda, Luca Sterpone, Luis Parra, Marta Portela-García, Almudena Lindoso, Luis Entrena
2016	—	`conf`	Rejuvenation of NBTI-Impacted Processors Using Evolutionary Generation of Assembler Programs. ATS Francesco Pellerey, Maksim Jenihhin, Giovanni Squillero, Jaan Raik, Matteo Sonza Reorda, Valentin Tihhomirov, Raimund Ubar
2016	—	`conf`	Test Time Minimization in Reconfigurable Scan Networks. ATS Riccardo Cantoro, Marco Palena, Paolo Pasini, Matteo Sonza Reorda
2015	—	`conf`	An effective ATPG flow for Gate Delay Faults. DTIS Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda
2015	C	`conf`	Design space exploration and optimization of a Hybrid Fault-Tolerant Architecture. IOLTS Imran Wali, Arnaud Virazel, Alberto Bosio, Patrick Girard, Matteo Sonza Reorda
2015	A	`conf`	Exploring the impact of functional test programs re-used for power-aware testing. DATE Aymen Touati, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda
2015	—	`conf`	In-field test of safety-critical systems: is functional test a feasible solution? LATS Matteo Sonza Reorda
2015	B	`conf`	On test program compaction. ETS Marco Gaudesi, Matteo Sonza Reorda, Irith Pomeranz
2015	—	`conf`	On the Design of a Fault Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors. ISVLSI Hassan Ghasemzadeh, Pierre-Emmanuel Gaillardon, J. Zhang, Giovanni De Micheli, Ernesto Sánchez, Matteo Sonza Reorda
2015	J	`jnl`	On the Functional Test of Branch Prediction Units. IEEE Trans. Very Large Scale Integr. Syst. Ernesto Sánchez, Matteo Sonza Reorda
2015	A	`conf`	On the automatic generation of SBST test programs for in-field test. DATE Andreas Riefert, Riccardo Cantoro, Matthias Sauer, Matteo Sonza Reorda, Bernd Becker
2015	—	`conf`	On the functional test of the cache coherency logic in multi-core systems. LASCAS Julio Pérez Acle, Riccardo Cantoro, Ernesto Sánchez, Matteo Sonza Reorda
2015	C	`conf`	On the maximization of the sustained switching activity in a processor. IOLTS Riccardo Cantoro, Matteo Sonza Reorda, Alireza Rohani, Hans G. Kerkhoff
2015	—	`conf`	On the testability of IEEE 1687 networks. ATS Riccardo Cantoro, Mehrdad Montazeri, Matteo Sonza Reorda, Farrokh Ghani Zadegan, Erik Larsson
2015	—	`conf`	Permanent fault detection and diagnosis in the lightweight dual modular redundancy architecture. LATS Ronaldo Rodrigues Ferreira, Ernesto Sánchez, Jean da Rolt, Gabriel L. Nazar, Álvaro F. Moreira, Luigi Carro, Matteo Sonza Reorda
2015	—	`conf`	Rejuvenation of nanoscale logic at NBTI-critical paths using evolutionary TPG. LATS N. Palermo, Valentin Tihhomirov, Thiago Santos Copetti, Maksim Jenihhin, Jaan Raik, Sergei Kostin, Marco Gaudesi, Giovanni Squillero, Matteo Sonza Reorda, Fabian Vargas, Letícia Maria Bolzani Pöhls
2015	—	`conf`	SW-based transparent in-field memory testing. LATS Paolo Bernardi, Lyl M. Ciganda Brasca, Matteo Sonza Reorda, Said Hamdioui
2015	—	`conf`	Scan-chain intra-cell defects grading. DTIS Aymen Touati, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda
2014	J	`jnl`	A Functional Approach for Testing the Reorder Buffer Memory. J. Electron. Test. Stefano Di Carlo, Marco Gaudesi, Edgar E. Sánchez, Matteo Sonza Reorda
2014	C	`conf`	A new solution to on-line detection of Control Flow Errors. IOLTS Boyang Du, Matteo Sonza Reorda, Luca Sterpone, Luis Parra, Marta Portela-García, Almudena Lindoso, Luis Entrena
2014	A	`conf`	An effective approach to automatic functional processor test generation for small-delay faults. DATE Andreas Riefert, Lyl M. Ciganda, Matthias Sauer, Paolo Bernardi, Matteo Sonza Reorda, Bernd Becker
2014	—	`conf`	Early reliability evaluation of a biomédical system. IDT Hakob Hakobyan, Paolo Rech, Matteo Sonza Reorda, Massimo Violante
2014	J	`jnl`	Evaluating the radiation sensitivity of GPGPU caches: New algorithms and experimental results. Microelectron. Reliab. Davide Sabena, Matteo Sonza Reorda, Luca Sterpone, Paolo Rech, Luigi Carro
2014	C	`conf`	Fault injection in GPGPU cores to validate and debug robust parallel applications. IOLTS M. De Carvalho, Davide Sabena, Matteo Sonza Reorda, Luca Sterpone, Paolo Rech, Luigi Carro
2014	A	`conf`	GPGPUs: How to combine high computational power with high reliability. DATE Leonardo Arturo Bautista-Gomez, Franck Cappello, Luigi Carro, Nathan DeBardeleben, Bo Fang, Sudhanva Gurumurthi, Karthik Pattabiraman, Paolo Rech, Matteo Sonza Reorda
2014	—	`conf`	High Quality System Level Test and Diagnosis. ATS Artur Jutman, Matteo Sonza Reorda, Hans-Joachim Wunderlich
2014	J	`jnl`	Increasing the Fault Coverage of Processor Devices during the Operational Phase Functional Test. J. Electron. Test. Mauricio de Carvalho, Paolo Bernardi, Ernesto Sánchez, Matteo Sonza Reorda, Oscar Ballan
2014	J	`jnl`	MIHST: A Hardware Technique for Embedded Microprocessor Functional On-Line Self-Test. IEEE Trans. Computers Paolo Bernardi, Lyl Mercedes Ciganda, Ernesto Sánchez, Matteo Sonza Reorda
2014	J	`jnl`	On the Automatic Generation of Optimized Software-Based Self-Test Programs for VLIW Processors. IEEE Trans. Very Large Scale Integr. Syst. Davide Sabena, Matteo Sonza Reorda, Luca Sterpone
2014	—	`conf`	On the in-field functional testing of decode units in pipelined RISC processors. DFT Paolo Bernardi, Riccardo Cantoro, Lyl M. Ciganda Brasca, Ernesto Sánchez, Matteo Sonza Reorda, Sergio de Luca, Renato Meregalli, Alessandro Sansonetti
2014	C	`conf`	On the in-field test of Branch Prediction Units using the correlated predictor mechanism. DDECS Marco Gaudesi, S. Saleem, Ernesto Sánchez, Matteo Sonza Reorda, E. Tanowe
2014	C	`conf`	Permanent faults on LIN networks: On-line test generation. IOLTS Anna Vaskova, Marta Portela-García, Mario García-Valderas, Celia López-Ongil, Matteo Sonza Reorda
2014	—	`conf`	Reducing SEU sensitivity in LIN networks: Selective and collaborative hardening techniques. LATW Anna Vaskova, A. Fabregat, Marta Portela-García, Mario García-Valderas, Celia López-Ongil, Matteo Sonza Reorda
2014	J	`jnl`	Selected Peer-Reviewed Articles from the 14th IEEE Latin-American Test Workshop, Cordoba, Argentina, April 3-5, 2013. J. Low Power Electron. Letícia Maria Bolzani Poehls, Matteo Sonza Reorda
2014	C	`conf`	Soft error effects analysis and mitigation in VLIW safety-critical applications. VLSI-SoC Davide Sabena, Matteo Sonza Reorda, Luca Sterpone
2014	Misc	`conf`	Special session 8B - Panel: In-field testing of SoC devices: Which solutions by which players? VTS Jacob A. Abraham, Xinli Gu, Teresa MacLaurin, Janusz Rajski, Paul G. Ryan, Dimitris Gizopoulos, Matteo Sonza Reorda
2013	—	`conf`	A functional test algorithm for the register forwarding and pipeline interlocking unit in pipelined microprocessors. IDT Paolo Bernardi, D. Boyang, Lyl M. Ciganda, Ernesto Sánchez, Matteo Sonza Reorda, Michelangelo Grosso, Oscar Ballan
2013	—	`conf`	An Efficient Method for the Test of Embedded Memory Cores during the Operational Phase. Asian Test Symposium Paolo Bernardi, Lyl M. Ciganda, Matteo Sonza Reorda, Said Hamdioui
2013	B	`conf`	An error-detection and self-repairing method for dynamically and partially reconfigurable systems. ETS Matteo Sonza Reorda, Luca Sterpone, Anees Ullah
2013	C	`conf`	Exploiting the debug interface to support on-line test of control flow errors. IOLTS Boyang Du, Matteo Sonza Reorda, Luca Sterpone, Luis Parra, Marta Portela-García, Almudena Lindoso, Luis Entrena
2013	J	`jnl`	Fast Power Evaluation for Effective Generation of Test Programs Maximizing Peak Power Consumption. J. Low Power Electron. Paolo Bernardi, Mauricio de Carvalho, Ernesto Sánchez, Matteo Sonza Reorda, Alberto Bosio, Luigi Dilillo, Miroslav Valka, Patrick Girard
2013	C	`conf`	Hardening of serial communication protocols for potentially critical systems in automotive applications: LIN bus. IOLTS Anna Vaskova, Marta Portela-García, Matteo Sonza Reorda
2013	C	`conf`	Increasing fault coverage during functional test in the operational phase. IOLTS Mauricio de Carvalho, Paolo Bernardi, Ernesto Sánchez, Matteo Sonza Reorda, Oscar Ballan
2013	—	`conf`	On the Functional Test of the Register Forwarding and Pipeline Interlocking Unit in Pipelined Processors. MTV Paolo Bernardi, Riccardo Cantoro, Lyl M. Ciganda Brasca, Boyang Du, Ernesto Sánchez, Matteo Sonza Reorda, Michelangelo Grosso, Oscar Ballan
2013	C	`conf`	On the development of diagnostic test programs for VLIW processors. VLSI-SoC Davide Sabena, Matteo Sonza Reorda, Luca Sterpone
2013	—	`conf`	On the evaluation of soft-errors detection techniques for GPGPUs. IDT Davide Sabena, Matteo Sonza Reorda, Luca Sterpone, Paolo Rech, Luigi Carro
2013	—	`conf`	On the functional test of the BTB logic in pipelined and superscalar processors. LATW D. Changdao, Mariagrazia Graziano, Ernesto Sánchez, Matteo Sonza Reorda, Maurizio Zamboni, N. Zhifan
2013	C	`conf`	On the on-line functional test of the Reorder Buffer memory in superscalar processors. DDECS Stefano Di Carlo, Ernesto Sánchez, Matteo Sonza Reorda
2013	A	`conf`	On-line functionally untestable fault identification in embedded processor cores. DATE Paolo Bernardi, Michele Bonazza, Ernesto Sánchez, Matteo Sonza Reorda, Oscar Ballan
2013	—	`conf`	Partition-Based Faults Diagnosis of a VLIW Processor. VLSI-SoC (Selected Papers) Davide Sabena, Matteo Sonza Reorda, Luca Sterpone
2013	A	`conf`	Reliability analysis reloaded: how will we survive? DATE Robert C. Aitken, Görschwin Fey, Zbigniew T. Kalbarczyk, Frank Reichenbach, Matteo Sonza Reorda
2013	—	`conf`	Validation and robustness assessment of an automotive system. IDT Marco Desogus, Matteo Sonza Reorda, Luca Sterpone, V. A. Avantaggiati, G. Audisio, Marco Sabatini
2012	C	`conf`	A New Fault Injection Approach for Testing Network-on-Chips. PDP Luca Sterpone, Davide Sabena, Matteo Sonza Reorda
2012	C	`conf`	A SBST strategy to test microprocessors' Branch Target Buffer. DDECS Paolo Bernardi, Lyl M. Ciganda, Michelangelo Grosso, Ernesto Sánchez, Matteo Sonza Reorda
2012	A	`conf`	A new SBST algorithm for testing the register file of VLIW processors. DATE Davide Sabena, Matteo Sonza Reorda, Luca Sterpone
2012	—	`conf`	High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies. DFT Cristiana Bolchini, Antonio Miele, Chiara Sandionigi, Marco Ottavi, Salvatore Pontarelli, Adelio Salsano, Cecilia Metra, Martin Omaña, Daniele Rossi, Matteo Sonza Reorda, Luca Sterpone, Massimo Violante, Simone Gerardin, Marta Bagatin, Alessandro Paccagnella
2012	—	`conf`	On the Automatic Generation of Software-Based Self-Test Programs for Functional Test and Diagnosis of VLIW Processors. VLSI-SoC (Selected Papers) Davide Sabena, Luca Sterpone, Matteo Sonza Reorda
2012	—	`conf`	On the development of Software-Based Self-Test methods for VLIW processors. DFT Davide Sabena, Matteo Sonza Reorda, Luca Sterpone
2012	C	`conf`	On the functional test of L2 caches. IOLTS Michele Riga, Ernesto Sánchez, Matteo Sonza Reorda
2012	C	`conf`	On the optimized generation of Software-Based Self-Test programs for VLIW processors. VLSI-SoC Davide Sabena, Matteo Sonza Reorda, Luca Sterpone
2012	J	`jnl`	On the use of embedded debug features for permanent and transient fault resilience in microprocessors. Microprocess. Microsystems Marta Portela-García, Michelangelo Grosso, M. Gallardo-Campos, Matteo Sonza Reorda, Luis Entrena, Mario García-Valderas, Celia López-Ongil
2012	B	`conf`	On-line software-based self-test of the Address Calculation Unit in RISC processors. ETS Paolo Bernardi, Lyl M. Ciganda, Mauricio de Carvalho, Michelangelo Grosso, Jorge Luis Lagos-Benites, Ernesto Sánchez, Matteo Sonza Reorda, Oscar Ballan
2012	C	`conf`	On-line test of embedded systems: Which role for functional test? DDECS Matteo Sonza Reorda
2012	—	`conf`	Peak Power Estimation: A Case Study on CPU Cores. Asian Test Symposium Paolo Bernardi, Mauricio de Carvalho, Ernesto Sánchez, Matteo Sonza Reorda, Alberto Bosio, Luigi Dilillo, Patrick Girard, Miroslav Valka
2012	J	`jnl`	Software-Based Testing for System Peripherals. J. Electron. Test. Michelangelo Grosso, Wilson-Javier Pérez-Holguín, Ernesto Sánchez, Matteo Sonza Reorda, Alberto Paolo Tonda, Jaime Velasco-Medina
2012	J	`jnl`	Verifying Reliability (Dagstuhl Seminar 12341). Dagstuhl Reports Görschwin Fey, Masahiro Fujita, Natasa Miskov-Zivanov, Kaushik Roy, Matteo Sonza Reorda
2011	B	`conf`	A Functional Power Evaluation Flow for Defining Test Power Limits during At-Speed Delay Testing. ETS Miroslav Valka, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Ernesto Sánchez, Mauricio de Carvalho, Matteo Sonza Reorda
2011	B	`conf`	A Low-Cost Emulation System for Fast Co-verification and Debug. ETS Jorge Luis Lagos-Benites, Michelangelo Grosso, Luca Sterpone, Matteo Sonza Reorda, G. Audisio, M. Pipponzi, Marco Sabatini
2011	J	`jnl`	A Low-Cost Solution for Deploying Processor Cores in Harsh Environments. IEEE Trans. Ind. Electron. Massimo Violante, Cristina Meinhardt, Ricardo Reis, Matteo Sonza Reorda
2011	—	`conf`	A New Architecture to Cross-Fertilize On-Line and Manufacturing Testing. Asian Test Symposium Paolo Bernardi, Matteo Sonza Reorda
2011	J	`jnl`	A Parallel Tester Architecture for Accelerometer and Gyroscope MEMS Calibration and Test. J. Electron. Test. Lyl M. Ciganda Brasca, Paolo Bernardi, Matteo Sonza Reorda, Dimitri Barbieri, Luciano Bonaria, Roberto Losco, Luciano Marcigot, Maurizio Straiotto
2011	—	`conf`	An FPGA-Emulation-Based Platform for Characterization of Digital Baseband Communication Systems. DFT Jorge Luis Lagos-Benites, Michelangelo Grosso, Matteo Sonza Reorda, G. Audisio, M. Pipponzi, Marco Sabatini, V. A. Avantaggiati
2011	C	`conf`	An effective methodology for on-line testing of embedded microprocessors. IOLTS Paolo Bernardi, Lyl M. Ciganda, Ernesto Sánchez, Matteo Sonza Reorda
2011	C	`conf`	Fault injection analysis of transient faults in clustered VLIW processors. DDECS Luca Sterpone, Davide Sabena, Salvatore Campagna, Matteo Sonza Reorda
2011	J	`jnl`	Functional Verification of DMA Controllers. J. Electron. Test. Michelangelo Grosso, Wilson-Javier Pérez-Holguín, Danilo Ravotto, Ernesto Sánchez, Matteo Sonza Reorda, Alberto Paolo Tonda, Jaime Velasco-Medina
2011	—	`conf`	Functional test generation for the pLRU replacement mechanism of embedded cache memories. LATW Wilson J. Pérez H., Ernesto Sánchez, Matteo Sonza Reorda, Alberto Tonda, Jaime Velasco-Medina
2011	—	`conf`	On the Functional Test of Branch Prediction Units Based on the Branch History Table Architecture. VLSI-SoC (Selected Papers) Ernesto Sánchez, Matteo Sonza Reorda, Alberto Paolo Tonda
2011	—	`conf`	On the Modeling of Gate Delay Faults by Means of Transition Delay Faults. DFT Paolo Bernardi, Matteo Sonza Reorda, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch
2011	C	`conf`	On the functional test of Branch Prediction Units based on Branch History Table. VLSI-SoC Ernesto Sánchez, Matteo Sonza Reorda, Alberto Paolo Tonda
2011	—	`conf`	On the functional test of MESI controllers. LATW Ernesto Sánchez, Matteo Sonza Reorda
2011	C	`conf`	Optimized embedded memory diagnosis. DDECS Mauricio de Carvalho, Paolo Bernardi, Matteo Sonza Reorda, Nicola Campanelli, Tamas Kerekes, Davide Appello, Mario Barone, Vincenzo Tancorre, Marco Terzi
2010	J	`jnl`	A Hybrid Approach for Detection and Correction of Transient Faults in SoCs. IEEE Trans. Dependable Secur. Comput. Paolo Bernardi, Letícia Maria Veiras Bolzani Poehls, Michelangelo Grosso, Matteo Sonza Reorda
2010	C	`conf`	A hardware accelerated framework for the generation of design validation programs for SMT processors. DDECS Danilo Ravotto, Ernesto Sánchez, Matteo Sonza Reorda
2010	C	`conf`	A novel scalable and reconfigurable emulation platform for embedded systems verification. ISCAS M. Di Marzio, Michelangelo Grosso, Matteo Sonza Reorda, Luca Sterpone, G. Audisio, Marco Sabatini
2010	A	`conf`	A programmable BIST for DRAM testing and diagnosis. ITC Paolo Bernardi, Michelangelo Grosso, Matteo Sonza Reorda, Y. Zhang
2010	B	`conf`	A software-based self-test methodology for system peripherals. ETS Michelangelo Grosso, Wilson J. Pérez H., Danilo Ravotto, Edgar E. Sánchez, Matteo Sonza Reorda, Jaime Velasco-Medina
2010	A	`conf`	A tester architecture suitable for MEMS calibration and testing. ITC Lyl M. Ciganda Brasca, Paolo Bernardi, Matteo Sonza Reorda, Dimitri Barbieri, Maurizio Straiotto, Luciano Bonaria
2010	—	`conf`	An Enhanced Strategy for Functional Stress Pattern Generation for System-on-Chip Reliability Characterization. MTV Mauricio de Carvalho, Paolo Bernardi, Ernesto Sánchez, Matteo Sonza Reorda
2010	—	`conf`	An Exact and Efficient Critical Path Tracing Algorithm. DELTA Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Paolo Bernardi, Matteo Sonza Reorda
2010	B	`conf`	An adaptive tester architecture for volume diagnosis. ETS Paolo Bernardi, Michelangelo Grosso, Matteo Sonza Reorda
2010	C	`conf`	An on-line fault detection technique based on embedded debug features. IOLTS Michelangelo Grosso, Matteo Sonza Reorda, Marta Portela-García, Mario García-Valderas, Celia López-Ongil, Luis Entrena
2010	C	`conf`	Analysis of root causes of alpha sensitivity variations on microprocessors manufactured using different cell layouts. IOLTS Paolo Rech, Michelangelo Grosso, Fabio Melchiori, Domenico Loparco, Davide Appello, Luigi Dilillo, Alessandro Paccagnella, Matteo Sonza Reorda
2010	C	`conf`	Cumulative embedded memory failure bitmap display & analysis. DDECS Nicola Campanelli, Tamas Kerekes, Paolo Bernardi, Mauricio de Carvalho, Alessandro Panariti, Matteo Sonza Reorda, Davide Appello, Mario Barone
2010	J	`jnl`	Exploiting an infrastructure-intellectual property for systems-on-chip test, diagnosis and silicon debug. IET Comput. Digit. Tech. Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda
2010	—	`conf`	Functional test generation for DMA controllers. LATW Michelangelo Grosso, Wilson J. Pérez H., Danilo Ravotto, Ernesto Sánchez, Matteo Sonza Reorda, Jaime Velasco-Medina
2010	—	`conf`	Generating power-hungry test programs for power-aware validation of pipelined processors. SBCCI Andrea Calimera, Enrico Macii, Danilo Ravotto, Ernesto Sánchez, Matteo Sonza Reorda
2010	J	`jnl`	Microprocessor Software-Based Self-Testing. IEEE Des. Test Comput. Mihalis Psarakis, Dimitris Gizopoulos, Edgar E. Sánchez, Matteo Sonza Reorda
2009	A	`conf`	A low-cost SEE mitigation solution for soft-processors embedded in Systems on Pogrammable Chips. DATE Matteo Sonza Reorda, Massimo Violante, Cristina Meinhardt, Ricardo Reis
2009	—	`conf`	An On-board Data-Handling Computer for Deep-Space Exploration Built Using Commercial-Off-the-Shelf SRAM-Based FPGAs. DFT Matteo Sonza Reorda, Massimo Violante, Cristina Meinhardt, Ricardo Reis
2009	C	`conf`	An efficient fault simulation technique for transition faults in non-scan sequential circuits. DDECS Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Paolo Bernardi, Matteo Sonza Reorda
2009	C	`conf`	An enhanced FPGA-based low-cost tester platform exploiting effective test data compression for SoCs. DDECS Lyl M. Ciganda, Francesco Abate, Paolo Bernardi, M. Bruno, Matteo Sonza Reorda
2009	B	`conf`	Automatic Functional Stress Pattern Generation for SoC Reliability Characterization. ETS Davide Appello, Paolo Bernardi, R. Cagliesi, M. Giancarlini, Michelangelo Grosso, Edgar E. Sánchez, Matteo Sonza Reorda
2009	—	`conf`	Design validation of multithreaded architectures using concurrent threads evolution. SBCCI Danilo Ravotto, Edgar E. Sánchez, Matteo Sonza Reorda, Giovanni Squillero
2009	Misc	`conf`	DfT Reuse for Low-Cost Radiation Testing of SoCs: A Case Study. VTS Davide Appello, Paolo Bernardi, Simone Gerardin, Michelangelo Grosso, Alessandro Paccagnella, Paolo Rech, Matteo Sonza Reorda
2009	J	`jnl`	Effective Diagnostic Pattern Generation Strategy for Transition-Delay Faults in Full-Scan SOCs. IEEE Trans. Very Large Scale Integr. Syst. Davide Appello, Paolo Bernardi, Michelangelo Grosso, Ernesto Sánchez, Matteo Sonza Reorda
2009	C	`conf`	Evaluating Alpha-induced soft errors in embedded microprocessors. IOLTS Paolo Rech, Simone Gerardin, Alessandro Paccagnella, Paolo Bernardi, Michelangelo Grosso, Matteo Sonza Reorda, Davide Appello
2009	C	`conf`	Exploiting embedded FPGA in on-line software-based test strategies for microprocessor cores. IOLTS Michelangelo Grosso, Matteo Sonza Reorda
2009	—	`conf`	On the Generation of Functional Test Programs for the Cache Replacement Logic. Asian Test Symposium Wilson J. Pérez H., Danilo Ravotto, Edgar E. Sánchez, Matteo Sonza Reorda, Alberto Paolo Tonda
2009	—	`conf`	Recovery scheme for hardening system on programmable chips. LATW Cristina Meinhardt, Ricardo Reis, Massimo Violante, Matteo Sonza Reorda
2009	J	`jnl`	Test Program Generation for Communication Peripherals in Processor-Based SoC Devices. IEEE Des. Test Comput. Andreas Apostolakis, Dimitris Gizopoulos, Mihalis Psarakis, Danilo Ravotto, Matteo Sonza Reorda
2008	—	`conf`	A Deterministic Methodology for Identifying Functionally Untestable Path-Delay Faults in Microprocessor Cores. MTV Paolo Bernardi, Michelangelo Grosso, Ernesto Sánchez, Matteo Sonza Reorda
2008	C	`conf`	A Hybrid Approach to the Test of Cache Memory Controllers Embedded in SoCs. IOLTS Wilson J. Pérez H., Jaime Velasco-Medina, Danilo Ravotto, Edgar E. Sánchez, Matteo Sonza Reorda
2008	Misc	`conf`	A Novel SBST Generation Technique for Path-Delay Faults in Microprocessors Exploiting Gate- and RT-Level Descriptions. VTS Kyriakos Christou, Maria K. Michael, Paolo Bernardi, Michelangelo Grosso, Ernesto Sánchez, Matteo Sonza Reorda
2008	J	`jnl`	An Effective Technique for the Automatic Generation of Diagnosis-Oriented Programs for Processor Cores. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Paolo Bernardi, Ernesto Sánchez, Massimiliano Schillaci, Giovanni Squillero, Matteo Sonza Reorda
2008	A	`conf`	An novel Methodology for Reducing SoC Test Data Volume on FPGA-based Testers. DATE Paolo Bernardi, Matteo Sonza Reorda
2008	—	`conf`	Exploiting MOEA to Automatically Geneate Test Programs for Path-Delay Faults in Microprocessors. EvoWorkshops Paolo Bernardi, Kyriakos Christou, Michelangelo Grosso, Maria K. Michael, Ernesto Sánchez, Matteo Sonza Reorda
2008	J	`jnl`	Hardware and Software Transparency in the Protection of Programs Against SEUs and SETs. J. Electron. Test. Eduardo Luis Rhod, Carlos Arthur Lang Lisbôa, Luigi Carro, Matteo Sonza Reorda, Massimo Violante
2008	C	`conf`	Software-Based Self-Test Strategy for Data Cache Memories Embedded in SoCs. DDECS Wilson J. Pérez H., Jaime Velasco-Medina, Danilo Ravotto, Edgar E. Sánchez, Matteo Sonza Reorda
2007	C	`conf`	A Hybrid Approach to Fault Detection and Correction in SoCs. IOLTS Paolo Bernardi, Letícia Maria Veiras Bolzani, Matteo Sonza Reorda
2007	J	`jnl`	A System-layer Infrastructure for SoC Diagnosis. J. Electron. Test. Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda
2007	—	`conf`	A software-based methodology for the generation of peripheral test sets based on high-level descriptions. SBCCI Letícia Maria Veiras Bolzani, Edgar E. Sánchez, Matteo Sonza Reorda
2007	C	`conf`	An Automated Methodology for Cogeneration of Test Blocks for Peripheral Cores. IOLTS Letícia Maria Veiras Bolzani, Ernesto Sánchez, Massimiliano Schillaci, Matteo Sonza Reorda, Giovanni Squillero
2007	—	`conf`	An Effective Approach for the Diagnosis of Transition-Delay Faults in SoCs, based on SBST and Scan Chains. DFT Jorge Luis Lagos-Benites, Davide Appello, Paolo Bernardi, Michelangelo Grosso, Danilo Ravotto, Edgar E. Sánchez, Matteo Sonza Reorda
2007	—	`conf`	An optimized hybrid approach to provide fault detection and correction in SoCs. SBCCI Letícia Maria Veiras Bolzani, Paolo Bernardi, Matteo Sonza Reorda
2007	—	`conf`	Automotive Microcontroller End-of-Line Test via Software-Based Methodologies. MTV W. Di Palma, Danilo Ravotto, Edgar E. Sánchez, Massimiliano Schillaci, Matteo Sonza Reorda, Giovanni Squillero
2007	J	`jnl`	Evaluating Different Solutions to Design Fault Tolerant Systems with SRAM-based FPGAs. J. Electron. Test. Luca Sterpone, Matteo Sonza Reorda, Massimo Violante, Fernanda Lima Kastensmidt, Luigi Carro
2007	C	`conf`	Extended Fault Detection Techniques for Systems-on-Chip. DDECS Paolo Bernardi, Letícia Maria Veiras Bolzani, Matteo Sonza Reorda
2007	—	`conf`	Hardware-accelerated path-delay fault grading of functional test programs for processor-based systems. ACM Great Lakes Symposium on VLSI Paolo Bernardi, Michelangelo Grosso, Matteo Sonza Reorda
2007	A	`conf`	Interactive presentation: An enhanced technique for the automatic generation of effective diagnosis-oriented test programs for processor. DATE Ernesto Sánchez, Massimiliano Schillaci, Giovanni Squillero, Matteo Sonza Reorda
2007	—	`conf`	On Automatic Test Block Generation for Peripheral Testing in SoCs via Dynamic FSMs Extraction. MTV Danilo Ravotto, Edgar E. Sánchez, Massimiliano Schillaci, Matteo Sonza Reorda, Giovanni Squillero
2007	B	`conf`	On the Automatic Generation of Test Programs for Path-Delay Faults in Microprocessor Cores. ETS Paolo Bernardi, Michelangelo Grosso, Ernesto Sánchez, Matteo Sonza Reorda
2007	J	`jnl`	On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs CoRR Fernanda Lima Kastensmidt, Luca Sterpone, Luigi Carro, Matteo Sonza Reorda
2007	—	`conf`	Optimization of Self Checking FIR filters by means of Fault Injection Analysis. DFT Salvatore Pontarelli, Luca Sterpone, Gian Carlo Cardarilli, Marco Re, Matteo Sonza Reorda, Adelio Salsano, Massimo Violante
2007	—	`conf`	Safety Evaluation of NanoFabrics. DFT Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda
2007	C	`conf`	Self Checking Circuit Optimization by means of Fault Injection Analysis: A Case Study on Reed Solomon Decoders. IOLTS Salvatore Pontarelli, Luca Sterpone, Gian Carlo Cardarilli, Marco Re, Matteo Sonza Reorda, Adelio Salsano, Massimo Violante
2007	J	`jnl`	Testing Logic Cores using a BIST P1500 Compliant Approach: A Case of Study CoRR Paolo Bernardi, Guido Masera, Federico Quaglio, Matteo Sonza Reorda
2006	—	`conf`	A Fault Injection Environment for SoPC's Embedded Microprocessors. LATW Marta Portela-García, Luca Sterpone, Celia López-Ongil, Matteo Sonza Reorda, Massimo Violante
2006	—	`conf`	A New Approach to Cope with Single Event Upsets in Processor-based Systems. LATW Massimiliano Schillaci, Matteo Sonza Reorda, Massimo Violante
2006	J	`jnl`	A New Hybrid Fault Detection Technique for Systems-on-a-Chip. IEEE Trans. Computers Paolo Bernardi, Letícia Maria Veiras Bolzani, Maurizio Rebaudengo, Matteo Sonza Reorda, Fabian Vargas, Massimo Violante
2006	Misc	`conf`	A Pattern Ordering Algorithm for Reducing the Size of Fault Dictionaries. VTS Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda
2006	B	`conf`	An Evolutionary Methodology to Enhance Processor Software-Based Diagnosis. IEEE Congress on Evolutionary Computation Paolo Bernardi, Ernesto Sánchez, Massimiliano Schillaci, Giovanni Squillero, Matteo Sonza Reorda
2006	A	`conf`	An effective technique for minimizing the cost of processor software-based diagnosis in SoCs. DATE Paolo Bernardi, Ernesto Sánchez, Massimiliano Schillaci, Giovanni Squillero, Matteo Sonza Reorda
2006	J	`jnl`	Early, Accurate Dependability Analysis of CAN-Based Networked Systems. IEEE Des. Test Comput. Julio Pérez Acle, Matteo Sonza Reorda, Massimo Violante
2006	J	`jnl`	Efficient Techniques for Automatic Verification-Oriented Test Set Optimization. Int. J. Parallel Program. Ernesto Sánchez, Matteo Sonza Reorda, Giovanni Squillero
2006	A	`conf`	Embedded Memory Diagnosis: An Industrial Workflow. ITC Davide Appello, Vincenzo Tancorre, Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda
2006	B	`conf`	Fault Injection-based Reliability Evaluation of SoPCs. ETS Matteo Sonza Reorda, Luca Sterpone, Massimo Violante, Marta Portela-García, Celia López-Ongil, Luis Entrena
2006	C	`conf`	Hardware-in-the-Loop-Based Dependability Analysis of Automotive Systems. IOLTS Matteo Sonza Reorda, Massimo Violante
2006	Misc	`conf`	On the Automation of the Test Flow of Complex SoCs. VTS Davide Appello, Vincenzo Tancorre, Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda
2006	—	`conf`	Online hardening of programs against SEUs and SETs. DFT Carlos Arthur Lang Lisbôa, Luigi Carro, Matteo Sonza Reorda, Massimo Violante
2006	C	`ed.`	Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), Prague, Czech Republic, April 18-21, 2006 DDECS Matteo Sonza Reorda, Ondrej Novák, Bernd Straube, Hana Kubátová, Zdenek Kotásek, Pavel Kubalík, Raimund Ubar, Jirí Bucek
2006	—	`conf`	Software-Based On-Line Test of Communication Peripherals in Processor-Based Systems for Automotive Applications. MTV Paolo Bernardi, Letícia Maria Veiras Bolzani, Alberto Manzone, Massimo Osella, Massimo Violante, Matteo Sonza Reorda
2006	—	`book`	Software-Implemented Hardware Fault Tolerance. Olga Goloubeva, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
2006	J	`jnl`	System-in-Package Testing: Problems and Solutions. IEEE Des. Test Comput. Davide Appello, Paolo Bernardi, Michelangelo Grosso, Matteo Sonza Reorda
2005	—	`conf`	An Integrated Approach for Increasing the Soft-Error Detection Capabilities in SoCs processors. DFT Paolo Bernardi, Letícia Maria Veiras Bolzani, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
2005	—	`conf`	Automatic Completion and Refinement of Verification Sets for Microprocessor Cores. EvoWorkshops Ernesto Sánchez, Matteo Sonza Reorda, Giovanni Squillero
2005	—	`conf`	Automatic generation of test sets for SBST of microprocessor IP cores. SBCCI Ernesto Sánchez, Matteo Sonza Reorda, Giovanni Squillero, Massimo Violante
2005	—	`conf`	Diagnosing Faulty Functional Units in Processors by Using Automatically Generated Test Sets. MTV Paolo Bernardi, Ernesto Sánchez, Massimiliano Schillaci, Matteo Sonza Reorda, Giovanni Squillero
2005	C	`conf`	Efficient Estimation of SEU Effects in SRAM-Based FPGAs. IOLTS Matteo Sonza Reorda, Luca Sterpone, Massimo Violante
2005	—	`conf`	Exploiting an I-IP for both Test and Silicon Debug of Microprocessor Cores. MTV Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda
2005	B	`conf`	Exploiting an infrastructure IP to reduce memory diagnosis costs in SoCs. ETS Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda
2005	C	`conf`	Integrating BIST Techniques for On-Line SoC Testing. IOLTS Alberto Manzone, Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Ernesto Sánchez, Matteo Sonza Reorda
2005	B	`conf`	Multiple errors produced by single upsets in FPGA configuration memory: a possible solution. ETS Matteo Sonza Reorda, Luca Sterpone, Massimo Violante
2005	A	`conf`	New evolutionary techniques for test-program generation for complex microprocessor cores. GECCO Ernesto Sánchez, Massimiliano Schillaci, Matteo Sonza Reorda, Giovanni Squillero, Luca Sterpone, Massimo Violante
2005	A	`conf`	On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs. DATE Fernanda Lima Kastensmidt, Luca Sterpone, Luigi Carro, Matteo Sonza Reorda
2005	—	`conf`	On the Transformation of Manufacturing Test Sets into On-Line Test Sets for Microprocessors. DFT Ernesto Sánchez, Matteo Sonza Reorda, Giovanni Squillero
2005	A	`conf`	On-Line Detection of Control-Flow Errors in SoCs by Means of an Infrastructure IP Core. DSN Paolo Bernardi, Letícia Maria Veiras Bolzani, Maurizio Rebaudengo, Matteo Sonza Reorda, Fabian Vargas, Massimo Violante
2004	J	`jnl`	A BIST-based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques. J. Electron. Test. Davide Appello, Alessandra Fudoli, Vincenzo Tancorre, Paolo Bernardi, Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda
2004	J	`jnl`	A New Approach to Software-Implemented Fault Tolerance. J. Electron. Test. Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
2004	J	`jnl`	A New Approach to the Analysis of Single Event Transients in VLSI Circuits. J. Electron. Test. Matteo Sonza Reorda, Massimo Violante
2004	—	`conf`	A multi-level approach to the dependability analysis of networked systems based on the CAN protocol. SBCCI Fulvio Corno, Julio Pérez Acle, Matteo Sonza Reorda, Massimo Violante
2004	A	`conf`	Automatic Generation of Validation Stimuli for Application-Specific Processors. DATE Olga Goloubeva, Matteo Sonza Reorda, Massimo Violante
2004	J	`jnl`	Automatic Test Program Generation: A Case Study. IEEE Des. Test Comput. Fulvio Corno, Ernesto Sánchez, Matteo Sonza Reorda, Giovanni Squillero
2004	—	`conf`	Automatic Test Programs Generation Driven by Internal Performance Counters. MTV W. Lindsay, Ernesto Sánchez, Matteo Sonza Reorda, Giovanni Squillero
2004	J	`jnl`	Code Generation for Functional Validation of Pipelined Microprocessors. J. Electron. Test. Fulvio Corno, Ernesto Sánchez, Matteo Sonza Reorda, Giovanni Squillero
2004	—	`conf`	Coupling Different Methodologies to Validate Obsolete Microprocessors. DFT Lorena Anghel, Ernesto Sánchez, Matteo Sonza Reorda, Giovanni Squillero, Raoul Velazco
2004	J	`jnl`	Efficient analysis of single event transients. J. Syst. Archit. Matteo Sonza Reorda, Massimo Violante
2004	A	`conf`	Evaluating the Effects of SEUs Affecting the Configuration Memory of an SRAM-Based FPGA. DATE M. Bellato, Paolo Bernardi, D. Bortolato, A. Candelori, M. Ceschia, Alessandro Paccagnella, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante, P. Zambolin
2004	A	`conf`	Evaluating the Effects of Transient Faults on Vehicle Dynamic Performance in Automotive Systems. ITC Fulvio Corno, Matteo Sonza Reorda, Simonluca Tosato, F. Esposito
2004	J	`jnl`	Evolutionary Simulation-Based Validation. Int. J. Artif. Intell. Tools Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero
2004	—	`conf`	Exploiting an I-IP for In-Field SOC Test. DFT Paolo Bernardi, Maurizio Rebaudengo, Matteo Sonza Reorda
2004	J	`jnl`	Guest Editorial. J. Electron. Test. Cecilia Metra, Matteo Sonza Reorda
2004	C	`conf`	Hybrid Soft Error Detection by Means of Infrastructure IP Cores. IOLTS Letícia Maria Veiras Bolzani, Maurizio Rebaudengo, Matteo Sonza Reorda, Fabian Vargas, Massimo Violante
2004	C	`conf`	On the Evaluation of SEU Sensitiveness in SRAM-Based FPGAs. IOLTS Paolo Bernardi, Matteo Sonza Reorda, Luca Sterpone, Massimo Violante
2004	—	`conf`	On-Line Analysis and Perturbation of CAN Networks. DFT Matteo Sonza Reorda, Massimo Violante
2004	A	`conf`	Testing Logic Cores using a BIST P1500 Compliant Approach: A Case of Study. DATE Paolo Bernardi, Guido Masera, Federico Quaglio, Matteo Sonza Reorda
2004	—	`conf`	Using Infrastructure IPs to Support SW-Based Self-Test of Processor Cores. MTV Paolo Bernardi, Maurizio Rebaudengo, Matteo Sonza Reorda
2004	—	`conf`	Validation of the dependability of CAN-based networked systems. HLDVT Fulvio Corno, Julio Pérez Acle, Mattia Ramasso, Matteo Sonza Reorda, Massimo Violante
2003	A	`conf`	A P1500-Compatible Programmable BIST Approach for the Test of Embedded Flash Memories. DATE Paolo Bernardi, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
2003	J	`jnl`	Accurate Analysis of Single Event Upsets in a Pipelined Microprocessor. J. Electron. Test. Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
2003	—	`conf`	Accurate Dependability Analysis of CAN-Based Networked Systems. SBCCI Julio Pérez, Matteo Sonza Reorda, Massimo Violante
2003	C	`conf`	Accurate and Efficient Analysis of Single Event Transients in VLSI Circuits. IOLTS Matteo Sonza Reorda, Massimo Violante
2003	A	`conf`	An Accurate Analysis of the Effects of Soft Errors in the Instruction and Data Caches of a Pipelined Microprocessor. DATE Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
2003	C	`conf`	An RT-level Concurrent Error Detection Technique for Data Dominated Systems. IOLTS Olga Goloubeva, Matteo Sonza Reorda, Massimo Violante
2003	—	`conf`	An efficient algorithm for the extraction of compressed diagnostic information from embedded memory cores. ETFA (1) Paolo Bernardi, Maurizio Rebaudengo, Matteo Sonza Reorda
2003	C	`conf`	Analyzing SEU Effects in SRAM-based FPGAs. IOLTS Massimo Violante, M. Ceschia, Matteo Sonza Reorda, Alessandro Paccagnella, Paolo Bernardi, Maurizio Rebaudengo, D. Bortolato, M. Bellato, P. Zambolin, A. Candelori
2003	Misc	`conf`	Automatic Test Program Generation for Pipeline Processors. SAC Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda, Giovanni Squillero
2003	—	`conf`	Code generation for functional validation of pipelined microprocessors. ETW Fulvio Corno, Giovanni Squillero, Matteo Sonza Reorda
2003	—	`conf`	Dependability Analysis of CAN Networks: An Emulation-Based Approach. DFT Julio Pérez, Matteo Sonza Reorda, Massimo Violante
2003	—	`conf`	Detailed Comparison of Dependability Analyses Performed at RT and Gate Levels. DFT Abdelaziz Ammari, Régis Leveugle, Matteo Sonza Reorda, Massimo Violante
2003	B	`conf`	Emulation-Based Analysis of Soft Errors in Deep Sub-micron Circuits. FPL Matteo Sonza Reorda, Massimo Violante
2003	A	`conf`	Exploiting Programmable BIST For The Diagnosis of Embedded Memory Cores. ITC Davide Appello, Paolo Bernardi, Alessandra Fudoli, Maurizio Rebaudengo, Matteo Sonza Reorda, Vincenzo Tancorre, Massimo Violante
2003	A	`conf`	Fully Automatic Test Program Generation for Microprocessor Cores. DATE Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda, Giovanni Squillero
2003	J	`jnl`	Guest Editorial. J. Electron. Test. Cecilia Metra, Matteo Sonza Reorda
2003	—	`conf`	High-level test generation for hardware testing and software validation. HLDVT Olga Goloubeva, Matteo Sonza Reorda, Massimo Violante
2003	C	`conf`	Introducing SW-Based Fault Handling Mechanisms to Cope with EMI in Embedded Electronics: Are They A Good Remedy? IOLTS Fabian Vargas, Diogo B. Brum, Dárcio Prestes, Letícia Maria Veiras Bolzani, Eduardo Luis Rhod, Matteo Sonza Reorda
2003	J	`jnl`	New techniques for efficiently assessing reliability of SOCs. Microelectron. J. Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
2003	—	`conf`	Soft-Error Detection Using Control Flow Assertions. DFT Olga Goloubeva, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
2002	—	`conf`	A BIST-Based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques. IOLTW Davide Appello, Alessandra Fudoli, Vincenzo Tancorre, Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda
2002	—	`conf`	A BIST-Based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques. MTDT Davide Appello, Alessandra Fudoli, Vincenzo Tancorre, Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda
2002	—	`conf`	A New Approach to Software-Implemented Fault Tolerance. LATW Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
2002	—	`conf`	A New Functional Fault Model for FPGA Application-Oriented Testing. DFT Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
2002	—	`conf`	A Software Fault Tolerance Method for Safety-Critical Systems: Effectiveness and Drawbacks. SBCCI Bogdan Nicolescu, Raoul Velazco, Matteo Sonza Reorda, Maurizio Rebaudengo, Massimo Violante
2002	—	`conf`	A hierarchical approach for designing dependable systems. HLDVT Matteo Sonza Reorda, Massimo Violante, Nicola Mazzocca, Salvatore Venticinque, Andrea Bobbio, Giuliana Franceschinis
2002	J	`jnl`	An FPGA-Based Approach for Speeding-Up Fault Injection Campaigns on Safety-Critical Circuits. J. Electron. Test. Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
2002	Misc	`conf`	An Industrial Environment for High-Level Fault-Tolerant Structures Insertion and Validation. VTS Luis Berrojo, Isabel González, Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero, Luis Entrena, Celia López
2002	—	`conf`	An Overview Covering the Different Solutions: from radiation testing to Software Fault Injection. LATW Matteo Sonza Reorda
2002	Misc	`conf`	An evolutionary algorithm for reducing integrated-circuit test application time. SAC Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero
2002	—	`conf`	Analysis of SEU Effects in a Pipelined Processor. IOLTW Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
2002	—	`conf`	Analysis of the Equivalences and Dominances of Transient Faults at the RT Level. IOLTW Luis Berrojo, Isabel González, Luis Entrena, Celia López, Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero
2002	—	`conf`	Automatic Test Program Generation from RT-Level Microprocessor Descriptions. ISQED Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda, Giovanni Squillero
2002	B	`conf`	Efficient machine-code test-program induction. IEEE Congress on Evolutionary Computation Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda, Giovanni Squillero
2002	—	`conf`	Evolutionary Techniques for Minimizing Test Signals Application Time. EvoWorkshops Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero
2002	—	`conf`	Evolutionary Test Program Induction for Microprocessor Design Verification. Asian Test Symposium Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda, Giovanni Squillero
2002	—	`conf`	Fault List Compaction through Static Timing Analysis for Efficient Fault Injection Experiments. DFT Matteo Sonza Reorda, Massimo Violante
2002	—	`conf`	High-level and hierarchical test sequence generation. HLDVT Gert Jervan, Zebo Peng, Olga Goloubeva, Matteo Sonza Reorda, Massimo Violante
2002	J	`jnl`	Initializability analysis of synchronous sequential circuits. ACM Trans. Design Autom. Electr. Syst. Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Giovanni Squillero
2002	A	`conf`	New Techniques for Speeding-Up Fault-Injection Campaigns. DATE Luis Berrojo, Isabel González, Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero, Luis Entrena, Celia López
2002	—	`conf`	Reducing Test Application Time through Interleaved Scan. SBCCI Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero
2002	B	`conf`	Simulation-Based Analysis of SEU Effects on SRAM-based FPGAs. FPL Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
2001	—	`conf`	A P1500 Compliant BIST-Based Approach to Embedded RAM Diagnosis. Asian Test Symposium Davide Appello, Fulvio Corno, M. Giovinetto, Maurizio Rebaudengo, Matteo Sonza Reorda
2001	C	`conf`	A Source-to-Source Compiler for Generating Dependable Software. SCAM Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante, Marco Torchiano
2001	—	`conf`	ARPIA: A High-Level Evolutionary Test Signal Generator. EvoWorkshops Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda, Giovanni Squillero
2001	Misc	`conf`	Early Evaluation Of Bus Interconnects Dependability For System-On-Chip Designs. VLSI Design Marcello Lajolo, Matteo Sonza Reorda, Massimo Violante
2001	—	`conf`	Effective Techniques for High-Level ATPG. Asian Test Symposium Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda, Giovanni Squillero
2001	—	`conf`	Effectiveness and Limitations of Various Software Techniques for "Soft Error" Detection: A Comparative Study. IOLTW Bogdan Nicolescu, Raoul Velazco, Matteo Sonza Reorda
2001	Misc	`conf`	Evolving effective CA/CSTP: BIST architectures for sequential circuits. SAC Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero
2001	—	`conf`	Exploiting FPGA for Accelerating Fault Injection Experiments. IOLTW Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
2001	—	`conf`	Exploiting FPGA-Based Techniques for Fault Injection Campaigns on VLSI Circuits . DFT Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
2001	B	`conf`	FPGA-Based Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI Circuits. FPL Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
2001	—	`conf`	FPGA-Based Fault Injection for Microprocessor Systems. Asian Test Symposium Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
2001	A	`conf`	On the test of microprocessor IP cores. DATE Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero, Massimo Violante
2001	A	`conf`	System safety through automatic high-level code transformations: an experimental evaluation. DATE Ph. Cheynet, Bogdan Nicolescu, Raoul Velazco, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
2000	B	`conf`	A genetic algorithm-based system for generating test programs for microprocessor IP cores. ICTAI Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero, Massimo Violante
2000	—	`conf`	An Experimental Evaluation of the Effectiveness of Automatic Rule-Based Transformations for Safety-Critical Applications. DFT Maurizio Rebaudengo, Matteo Sonza Reorda, Marco Torchiano, Massimo Violante
2000	—	`conf`	An RT-level fault model with high gate level correlation. HLDVT Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda, Giovanni Squillero
2000	C	`conf`	An improved cellular automata-based BIST architecture for sequential circuits. ISCAS Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero
2000	A	`conf`	Automatic Test Bench Generation for Validation of RT-Level Descriptions: An Industrial Experience. DATE Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero, Alberto Manzone, Alessandro Pincetti
2000	—	`conf`	Automatic Validation of Protocol Interfaces Described in VHDL. EvoWorkshops Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero
2000	—	`conf`	Automatic test bench generation for simulation-based validation. CODES Marcello Lajolo, Luciano Lavagno, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
2000	—	`conf`	Behavioral-level test vector generation for system-on-chip designs. HLDVT Marcello Lajolo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante, Luciano Lavagno
2000	—	`conf`	CA-CSTP: a new BIST architecture for sequential circuits. ETW Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero, Massimo Violante
2000	—	`conf`	Early Power Estimation for System-on-Chip Designs. PATMOS Marcello Lajolo, Luciano Lavagno, Matteo Sonza Reorda, Massimo Violante
2000	A	`conf`	Evaluating System Dependability in a Co-Design Framework. DATE Marcello Lajolo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante, Luciano Lavagno
2000	—	`conf`	Evaluating the Effectiveness of a Software Fault-Tolerance Technique on RISC- and CISC-Based Architectures. IOLTW Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante, Ph. Cheynet, Bogdan Nicolescu, Raoul Velazco
2000	—	`conf`	Evolving Cellular Automata for Self-Testing Hardware. ICES Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero
2000	—	`conf`	Exploiting the Selfish Gene Algorithm for Evolving Cellular Automata. IJCNN (6) Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero
2000	B	`conf`	Exploiting the Selfish Gene algorithm for evolving hardware cellular automata. CEC Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero
2000	—	`conf`	Hardening the Software with Respect to Transient Errors: a Method and Experimental Results. LATW Ph. Cheynet, Raoul Velazco, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
2000	Misc	`conf`	High-Level Observability for Effective High-Level ATPG. VTS Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero
2000	Misc	`conf`	Low Power BIST via Non-Linear Hybrid Cellular Automata. VTS Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda, Giovanni Squillero, Massimo Violante
2000	—	`conf`	New Techniques for Accelerating Fault Injection in VHDL Descriptions. IOLTW B. Parrotta, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
2000	—	`conf`	Prediction of Power Requirements for High-Speed Circuits. EvoWorkshops Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
2000	J	`jnl`	RT-Level ITC'99 Benchmarks and First ATPG Results. IEEE Des. Test Comput. Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero
2000	B	`conf`	Speeding-Up Fault Injection Campaigns in VHDL Models. SAFECOMP B. Parrotta, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
2000	—	`conf`	System-level test bench generation in a co-design framework. ETW Marcello Lajolo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante, Luciano Lavagno
1999	—	`conf`	A new BIST architecture for low power circuits. ETW Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
1999	—	`conf`	ALPS: A Peak Power Estimation Tool for Sequential Circuits. Great Lakes Symposium on VLSI Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
1999	—	`conf`	Approximate Equivalence Verification for Protocol Interface Implementation via Genetic Algorithms. EvoWorkshops Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero
1999	A	`conf`	Approximate Equivalence Verification of Sequential Circuits via Genetic Algorithms. DATE Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero
1999	Misc	`conf`	Evaluating the Fault Tolerance Capabilities of Embedded Systems via BDM . VTS Maurizio Rebaudengo, Matteo Sonza Reorda
1999	J	`jnl`	Fault Injection for Embedded Microprocessor-based Systems. J. Univers. Comput. Sci. Alfredo Benso, Maurizio Rebaudengo, Matteo Sonza Reorda
1999	B	`conf`	FlexFi: A Flexible Fault Injection Environment for Microprocessor-Based Systems. SAFECOMP Alfredo Benso, Maurizio Rebaudengo, Matteo Sonza Reorda
1999	A	`conf`	High-level ATPG: a real topic or an academic amusement? ITC Matteo Sonza Reorda
1999	—	`conf`	Optimal Vector Selection for Low Power BIST. DFT Fulvio Corno, Matteo Sonza Reorda, Maurizio Rebaudengo, Massimo Violante
1999	B	`conf`	Optimizing deceptive functions with the SG-Clans algorithm. CEC Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero
1999	—	`conf`	Simulation-based sequential equivalence checking of RTL VHDL. ICECS Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero
1999	—	`conf`	Soft-Error Detection through Software Fault-Tolerance Techniques. DFT Maurizio Rebaudengo, Matteo Sonza Reorda, Marco Torchiano, Massimo Violante
1999	J	`jnl`	SymFony: a hybrid topological-symbolic ATPG exploiting RT-level information. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Fulvio Corno, Uwe Gläser, Paolo Prinetto, Matteo Sonza Reorda, Heinrich Theodor Vierhaus, Massimo Violante
1999	—	`conf`	Test Pattern Generation Under Low Power Constraints. EvoWorkshops Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
1999	B	`conf`	Verifying the equivalence of sequential circuits with genetic algorithms. CEC Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero
1998	—	`conf`	A System for Evaluating On-Line Testability at the RT-level. DFT Silvia Chiusano, Fulvio Corno, Matteo Sonza Reorda, Roberto Vietti
1998	Misc	`conf`	A Test Pattern Generation Methodology for Low-Power Consumption. VTS Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda
1998	A	`conf`	A fault injection environment for microprocessor-based boards. ITC Alfredo Benso, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda
1998	—	`conf`	An Integrated HW and SW Fault Injection Environment for Real-Time Systems. DFT Alfredo Benso, Maurizio Rebaudengo, Matteo Sonza Reorda, Pierluigi Civera
1998	J	`jnl`	EXFI: a low-cost fault injection system for embedded microprocessor-based boards. ACM Trans. Design Autom. Electr. Syst. Alfredo Benso, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda
1998	C	`conf`	Enhancing topological ATPG with high-level information and symbolic techniques. ICCD Fulvio Corno, Janak H. Patel, Elizabeth M. Rudnick, Matteo Sonza Reorda, Roberto Vietti
1998	A	`conf`	Exploiting Symbolic Techniques for Partial Scan Flip Flop Selection. DATE Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda, Massimo Violante
1998	A	`conf`	Fast Sequential Circuit Test Generation Using High-Level and Gate-Level Techniques. DATE Elizabeth M. Rudnick, Roberto Vietti, Akilah Ellis, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda
1998	J	`jnl`	Integrating Online and Offline Testing of a Switching Memory. IEEE Des. Test Comput. Stefano Barbagallo, Davide Medina, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda
1998	Misc	`conf`	On the Identification of Optimal Cellular Automata for Built-In Self-Test of Sequential Circuits. VTS Fulvio Corno, Nicola Gaudenzi, Paolo Prinetto, Matteo Sonza Reorda
1998	J	`jnl`	The General Product Machine: a New Model for Symbolic FSM Traversal. Formal Methods Syst. Des. Gianpiero Cabodi, Paolo Camurati, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda
1998	Misc	`conf`	The selfish gene algorithm: a new evolutionary optimization strategy. SAC Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero
1998	—	`conf`	The training environment for the course on microprocessor systems at the Politecnico di Torino. WCAE@ISCA Maurizio Rebaudengo, Matteo Sonza Reorda
1998	C	`conf`	VEGA: a verification tool based on genetic algorithms. ICCD Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero
1997	—	`conf`	A Genetic Algorithm for the Computation of Initialization Sequences for Synchronous Sequential Circuits. Asian Test Symposium Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Giovanni Squillero
1997	C	`conf`	A new Approach for Initialization Sequences Computation for Synchronous Sequential Circuits. ICCD Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Giovanni Squillero
1997	—	`conf`	A new approach to build a low-level malicious fault list starting from high-level description and alternative graphs. ED&TC Alfredo Benso, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Raimund Ubar
1997	—	`conf`	Boolean Function Manipulation on a Parallel System Using BDDs. HPCN Europe F. Bianchi, Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda, Roberto Ansaloni
1997	Misc	`conf`	Cellular automata for deterministic sequential test pattern generation. VTS Silvia Chiusano, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda
1997	—	`conf`	Exploiting High-Level Descriptions for Circuits Fault Tolerance Assessments. DFT Alfredo Benso, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Jaan Raik, Raimund Ubar
1997	—	`conf`	Exploiting Logic Simulation to Improve Simulation-based Sequential ATPG. Asian Test Symposium Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
1997	B	`conf`	Exploiting Symbolic Techniques within Genetic Algorithms for Power Optimization. ICTAI S. Chuisano, Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda
1997	—	`conf`	Guaranteeing Testability in Re-encoding for Low Power. Asian Test Symposium Silvia Chiusano, Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda
1997	—	`conf`	Hybrid symbolic-explicit techniques for the graph coloring problem. ED&TC Silvia Chiusano, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda
1997	—	`conf`	New static compaction techniques of test sequences for sequential circuits. ED&TC Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda
1997	Misc	`conf`	SAARA: a simulated annealing algorithm for test pattern generation for digital circuits. SAC Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda
1997	—	`conf`	Simulation-based verification of network protocols performance. CHARME Mario Baldi, Fulvio Corno, Maurizio Rebaudengo, Paolo Prinetto, Matteo Sonza Reorda, Giovanni Squillero
1997	A	`conf`	Testability Analysis and ATPG on Behavioral RT-Level VHDL. ITC Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda
1996	—	`conf`	A Cellular Genetic Algorithm for the Floorplan Area Optimization Problem on a SIMD Architecture. HPCN Europe Maurizio Rebaudengo, Matteo Sonza Reorda
1996	B	`conf`	A Genetic Algorithm for Automatic Generation of Test Logic for Digital Circuits. ICTAI Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda
1996	—	`conf`	A Parallel Genetic Algorithm for Automatic Generation of Test Sequences for Digital Circuits. HPCN Europe Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda
1996	—	`conf`	Advanced Techniques for GA-based sequential ATPGs. ED&TC Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, R. Mosca
1996	J	`jnl`	Circular Self-Test Path for FSMs. IEEE Des. Test Comput. Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda
1996	A	`conf`	Comparing Topological, Symbolic and GA-based ATPGs: An Experimental Approach. ITC Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda
1996	A	`conf`	Exploiting Competing Subpopulations for Automatic Generation of Test Sequences for Digital Cicuits. PPSN Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda
1996	—	`conf`	Fault behavior observation of a microprocessor system through a VHDL simulation-based fault injection experiment. EURO-DAC Paolo Prinetto, Alfredo Benso, Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda, Arturo M. Amendola, Leonardo Impagliazzo, P. Marmo
1996	—	`conf`	Fault tolerant and BIST design of a FIFO cell. EURO-DAC Paolo Prinetto, Fulvio Corno, Matteo Sonza Reorda
1996	J	`jnl`	GALLO: a genetic algorithm for floorplan area optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Maurizio Rebaudengo, Matteo Sonza Reorda
1996	J	`jnl`	GATTO: a genetic algorithm for automatic test pattern generation for large synchronous sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda
1996	Misc	`conf`	On-line Testing of an Off-the-shelf Microprocessor Board for Safety-critical Applications. EDCC Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Maurizio Damiani, Leonardo Impagliazzo, G. Sartore
1996	A	`conf`	Partial Scan Flip Flop Selection for Simulation-Based Sequential ATPGs. ITC Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda
1996	Misc	`conf`	Scan insertion criteria for low design impact. VTS Stefano Barbagallo, Monica Lobetti Bodoni, Davide Medina, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda
1996	—	`conf`	Self-Checking and Fault Tolerant Approaches Can Help BIST Fault Coverage: A Case Study. ED&TC Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda
1996	—	`conf`	Using Parallel Genetic Algorithms for Solving the Min-Cut Problem. HPCN Europe Gavril Godza, Maurizio Rebaudengo, Matteo Sonza Reorda
1995	—	`conf`	A PVM tool for automatic test generation on parallel and distributed systems. HPCN Europe Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Enzo Veiluva
1995	Misc	`conf`	A portable ATPG tool for parallel and distributed systems. VTS Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Enzo Veiluva
1995	C	`conf`	An improved data parallel algorithm for Boolean function manipulation using BDDs. PDP Silvano Gai, Maurizio Rebaudengo, Matteo Sonza Reorda
1995	—	`conf`	Exploiting massively parallel architectures for the solution of diffusion and propagation problems. HPCN Europe Pier Paolo Delsanto, S. Biancotto, Marco Scalerandi, Maurizio Rebaudengo, Matteo Sonza Reorda
1995	—	`conf`	GARDA: a diagnostic ATPG for large synchronous sequential circuits. ED&TC Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda
1995	Misc	`conf`	Improving topological ATPG with symbolic techniques. VTS Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda, Uwe Gläser, Heinrich Theodor Vierhaus
1995	J	`jnl`	Industrial BIST of Embedded RAMs. IEEE Des. Test Comput. Paolo Camurati, Paolo Prinetto, Matteo Sonza Reorda, Stefano Barbagallo, Andrea Burri, Davide Medina
1995	A	`conf`	Testing a Switching Memory in a Telcommunication System. ITC Stefano Barbagallo, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda
1995	—	`conf`	Using symbolic techniques to find the maximum clique in very large sparse graphs. ED&TC Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda
1994	C	`conf`	A BDD Package For A Massively Parallel SIMD Architecture. PDP Gianpiero Cabodi, Silvano Gai, Maurizio Rebaudengo, Matteo Sonza Reorda
1994	—	`conf`	A Genetic Algorithm for Floorplan Area Optimization. International Conference on Evolutionary Computation Matteo Sonza Reorda, Maurizio Rebaudengo
1994	A	`conf`	An Automatic Test Pattern Generator for Large Sequential Circuits Based on Genetic Algorithms. ITC Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda
1994	—	`conf`	An experimental analysis of the effectiveness of the circular self-test path technique. EURO-DAC Paolo Prinetto, Fulvio Corno, Matteo Sonza Reorda
1994	Misc	`conf`	An industrial experience in the built-in self test of embedded RAMs. VTS Paolo Camurati, Paolo Prinetto, Matteo Sonza Reorda, Stefano Barbagallo, Andrea Burri, Davide Medina
1994	—	`conf`	Floorplan area optimization using genetic algorithms. Great Lakes Symposium on VLSI Maurizio Rebaudengo, Matteo Sonza Reorda
1994	B	`conf`	GATTO: An Intelligent Tool for Automatic Test Pattern Generation for Digital Circuits. ICTAI Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Enzo Veiluva
1994	A	`conf`	Making the Circular Self-Test Path Technique Effective for Real Circuits. ITC Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda
1994	—	`conf`	TORSIM: An Efficient Fault Simulator for Synchronous Sequential Circuits. EDAC-ETC-EUROASIC Silvano Gai, Pier Luca Montessoro, Matteo Sonza Reorda
1993	J	`jnl`	A Parallel System for Test Pattern Generation. Parallel Comput. Gianpiero Balboni, Gianpiero Cabodi, Silvano Gai, Matteo Sonza Reorda
1993	J	`jnl`	An approach to sequential circuit diagnosis based on formal verification techniques. J. Electron. Test. Gianpiero Cabodi, Paolo Camurati, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda
1993	C	`conf`	An experimental analysis of the effects of migration in parallel genetic algorithms. PDP Maurizio Rebaudengo, Matteo Sonza Reorda
1992	A*	`conf`	A New Model for Improving symbolic Product Machine Traversal. DAC Gianpiero Cabodi, Paolo Camurati, Fulvio Corno, Silvano Gai, Paolo Prinetto, Matteo Sonza Reorda
1992	Misc	`conf`	A simulation-based approach to test pattern generation for synchronous sequential circuits. VTS Paolo Camurati, Fulvio Corno, Fulvio Prinetto, Matteo Sonza Reorda
1992	—	`conf`	Cross-fertilizing FSM verification techniques and sequential diagnosis. EURO-DAC Gianpiero Cabodi, Paolo Camurati, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda
1992	A	`conf`	Sequential Circuit Diagnosis Based on Formal Verification Techniques. ITC Gianpiero Cabodi, Paolo Camurati, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda
1991	—	`conf`	A parallel system for test pattern generation. SPDP Gianpiero Balboni, Gianpiero Cabodi, Silvano Gai, D. Sismondi, Matteo Sonza Reorda
1991	—	`conf`	An algebraic approach to test generation for sequential circuits. Great Lakes Symposium on VLSI Antonio Lioy, Enrico Macii, Angelo Raffaele Meo, Matteo Sonza Reorda
1991	C	`conf`	Fast Differential Fault Simulation by Dynamic Fault Ordering. ICCD Gianpiero Cabodi, Silvano Gai, Matteo Sonza Reorda
1991	—	`conf`	Proving finite state machines correct with an automaton-based method. Great Lakes Symposium on VLSI Paolo Camurati, Marco Gilli, Paolo Prinetto, Matteo Sonza Reorda
1991	J	`jnl`	TPDL: Extended Temporal Profile Description Language. Softw. Pract. Exp. Gianpiero Cabodi, Paolo Camurati, Paolo Prinetto, Matteo Sonza Reorda
1990	A	`conf`	A diagnostic test pattern generation algorithm. ITC Paolo Camurati, Davide Medina, Paolo Prinetto, Matteo Sonza Reorda
1990	J	`jnl`	A transputer-based gate-level fault simulator. Microprocessing and Microprogramming Gianpiero Cabodi, Silvano Gai, Matteo Sonza Reorda
1990	J	`jnl`	Assessing the diagnostic power of test pattern sets. Microprocessing and Microprogramming Paolo Camurati, Antonio Lioy, Paolo Prinetto, Matteo Sonza Reorda
1990	—	`conf`	Diagnosis oriented test pattern generation. EURO-DAC Paolo Camurati, Antonio Lioy, Paolo Prinetto, Matteo Sonza Reorda
1990	J	`jnl`	Exact probabilistic testability measures for multi-output circuits. J. Electron. Test. Paolo Camurati, Paolo Prinetto, Matteo Sonza Reorda
1990	—	`conf`	Model Checking and Graph Theory in Sequential ATPG. CAV (DIMACS/AMS volume) Paolo Camurati, Marco Gilli, Paolo Prinetto, Matteo Sonza Reorda
1990	A*	`conf`	The Use of Model Checking in ATPG for Sequential Circuits. CAV Paolo Camurati, Marco Gilli, Paolo Prinetto, Matteo Sonza Reorda
1989	J	`jnl`	Expressing logical and temporal conditions in simulation environments: TPDL Microprocessing and Microprogramming Gianpiero Cabodi, Paolo Camurati, Paolo Prinetto, Matteo Sonza Reorda
1988	C	`conf`	Random testability analysis: comparing and evaluating existing approaches. ICCD Paolo Camurati, Paolo Prinetto, Matteo Sonza Reorda