Matteo Perotti

36 papers A 5C 3Journal 21Unranked 7

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	A Reliable, Time-Predictable Heterogeneous SoC for AI-Enhanced Mixed-Criticality Edge Applications. CoRR Angelo Garofalo, Alessandro Ottaviano, Matteo Perotti, Thomas Benz, Yvan Tortorella, Robert Balas, Michael Rogenmoser, Chi Zhang, Luca Bertaccini, Nils Wistoff, Maicol Ciani, Cyril Koenig, Mattia Sinigaglia, Luca Valente, Paul Scheffler, Manuel Eggimann, Matheus A. Cavalcante, Francesco Restuccia, Alessandro Biondi, Francesco Conti, Frank K. Gürkaynak, Davide Rossi, Luca Benini
2025	J	`jnl`	A Reliable, Time-Predictable Heterogeneous SoC for AI-Enhanced Mixed-Criticality Edge Applications. IEEE Trans. Circuits Syst. II Express Briefs Angelo Garofalo, Alessandro Ottaviano, Matteo Perotti, Thomas Benz, Yvan Tortorella, Robert Balas, Michael Rogenmoser, Chi Zhang, Luca Bertaccini, Nils Wistoff, Maicol Ciani, Cyril Koenig, Mattia Sinigaglia, Luca Valente, Paul Scheffler, Manuel Eggimann, Matheus A. Cavalcante, Francesco Restuccia, Alessandro Biondi, Francesco Conti, Frank K. Gürkaynak, Davide Rossi, Luca Benini
2025	—	`conf`	AraOS: Analyzing the Impact of Virtual Memory Management on Vector Unit Performance. CF (Companion) Matteo Perotti, Vincenzo Maisto, Moritz Imfeld, Nils Wistoff, Alessandro Cilardo, Luca Benini
2025	J	`jnl`	AraOS: Analyzing the Impact of Virtual Memory Management on Vector Unit Performance. CoRR Matteo Perotti, Vincenzo Maisto, Moritz Imfeld, Nils Wistoff, Alessandro Cilardo, Luca Benini
2025	A	`conf`	AraXL: A Physically Scalable, Ultra-Wide RISC-V Vector Processor Design for Fast and Efficient Computation on Long Vectors. DATE Navaneeth Kunhi Purayil, Matteo Perotti, Tim Fischer, Luca Benini
2025	J	`jnl`	AraXL: A Physically Scalable, Ultra-Wide RISC-V Vector Processor Design for Fast and Efficient Computation on Long Vectors. CoRR Navaneeth Kunhi Purayil, Matteo Perotti, Tim Fischer, Luca Benini
2025	—	`conf`	Quadrilatero: A RISC-V programmable matrix coprocessor for low-power edge applications. CF (Companion) Danilo Cammarata, Matteo Perotti, Marco Bertuletti, Angelo Garofalo, Pasquale Davide Schiavone, David Atienza, Luca Benini
2025	J	`jnl`	Quadrilatero: A RISC-V programmable matrix coprocessor for low-power edge applications. CoRR Danilo Cammarata, Matteo Perotti, Marco Bertuletti, Angelo Garofalo, Pasquale Davide Schiavone, David Atienza, Luca Benini
2025	J	`jnl`	Spatz: Clustering Compact RISC-V-Based Vector Units to Maximize Computing Efficiency. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Matteo Perotti, Samuel Riedel, Matheus A. Cavalcante, Luca Benini
2025	—	`conf`	Stella Nera: A Differentiable Maddness-Based Hardware Accelerator for Efficient Approximate Matrix Multiplication. ISVLSI Jannis Schönleber, Lukas Cavigelli, Matteo Perotti, Luca Benini, Renzo Andri
2025	C	`conf`	TROOP: At-the-Roofline Performance for Vector Processors on Low Operational Intensity Workloads. ICCD Navaneeth Kunhi Purayil, Diyou Shen, Matteo Perotti, Luca Benini
2025	J	`jnl`	TROOP: At-the-Roofline Performance for Vector Processors on Low Operational Intensity Workloads. CoRR Navaneeth Kunhi Purayil, Diyou Shen, Matteo Perotti, Luca Benini
2024	J	`jnl`	Ara2: Exploring Single- and Multi-Core Vector Processing With an Efficient RVV 1.0 Compliant Open-Source Processor. IEEE Trans. Computers Matteo Perotti, Matheus A. Cavalcante, Renzo Andri, Lukas Cavigelli, Luca Benini
2024	A	`conf`	MX: Enhancing RISC-V's Vector ISA for Ultra-Low Overhead, Energy-Efficient Matrix Multiplication. DATE Matteo Perotti, Yichao Zhang, Matheus A. Cavalcante, Enis Mustafa, Luca Benini
2024	J	`jnl`	MX: Enhancing RISC-V's Vector ISA for Ultra-Low Overhead, Energy-Efficient Matrix Multiplication. CoRR Matteo Perotti, Yichao Zhang, Matheus A. Cavalcante, Enis Mustafa, Luca Benini
2024	A	`conf`	Near-Memory Parallel Indexing and Coalescing: Enabling Highly Efficient Indirect Access for SpMV. DATE Chi Zhang, Paul Scheffler, Thomas Benz, Matteo Perotti, Luca Benini
2024	J	`jnl`	SentryCore: A RISC-V Co-Processor System for Safe, Real-Time Control Applications. CoRR Michael Rogenmoser, Alessandro Ottaviano, Thomas Benz, Robert Balas, Matteo Perotti, Angelo Garofalo, Luca Benini
2024	—	`conf`	Spatzformer: An Efficient Reconfigurable Dual-Core RISC-V V Cluster for Mixed Scalar-Vector Workloads. ASAP Matteo Perotti, Michele Raeber, Mattia Sinigaglia, Matheus A. Cavalcante, Davide Rossi, Luca Benini
2024	J	`jnl`	Spatzformer: An Efficient Reconfigurable Dual-Core RISC-V V Cluster for Mixed Scalar-Vector Workloads. CoRR Matteo Perotti, Michele Raeber, Mattia Sinigaglia, Matheus A. Cavalcante, Davide Rossi, Luca Benini
2023	A	`conf`	AXI-Pack: Near-Memory Bus Packing for Bandwidth-Efficient Irregular Workloads. DATE Chi Zhang, Paul Scheffler, Thomas Benz, Matteo Perotti, Luca Benini
2023	J	`jnl`	Ara2: Exploring Single- and Multi-Core Vector Processing with an Efficient RVV1.0 Compliant Open-Source Processor. CoRR Matteo Perotti, Matheus A. Cavalcante, Renzo Andri, Lukas Cavigelli, Luca Benini
2023	J	`jnl`	DARKSIDE: A Heterogeneous RISC-V Compute Cluster for Extreme-Edge On-Chip DNN Inference and Training. CoRR Angelo Garofalo, Yvan Tortorella, Matteo Perotti, Luca Valente, Alessandro Nadalini, Luca Benini, Davide Rossi, Francesco Conti
2023	J	`jnl`	Near-Memory Parallel Indexing and Coalescing: Enabling Highly Efficient Indirect Access for SpMV. CoRR Chi Zhang, Paul Scheffler, Thomas Benz, Matteo Perotti, Luca Benini
2023	C	`conf`	Quark: An Integer RISC-V Vector Processor for Sub-Byte Quantized DNN Inference. ISCAS MohammadHossein AskariHemmat, Théo Dupuis, Yoan Fournier, Nizar El Zarif, Matheus A. Cavalcante, Matteo Perotti, Frank K. Gürkaynak, Luca Benini, François Leduc-Primeau, Yvon Savaria, Jean-Pierre David
2023	J	`jnl`	Quark: An Integer RISC-V Vector Processor for Sub-Byte Quantized DNN Inference. CoRR MohammadHossein AskariHemmat, Théo Dupuis, Yoan Fournier, Nizar El Zarif, Matheus A. Cavalcante, Matteo Perotti, Frank K. Gürkaynak, Luca Benini, François Leduc-Primeau, Yvon Savaria, Jean-Pierre David
2023	J	`jnl`	Spatz: Clustering Compact RISC-V-Based Vector Units to Maximize Computing Efficiency. CoRR Matheus A. Cavalcante, Matteo Perotti, Samuel Riedel, Luca Benini
2023	J	`jnl`	Stella Nera: Achieving 161 TOp/s/W with Multiplier-free DNN Acceleration based on Approximate Matrix Multiplication. CoRR Jannis Schönleber, Lukas Cavigelli, Renzo Andri, Matteo Perotti, Luca Benini
2023	J	`jnl`	Yun: An Open-Source, 64-Bit RISC-V-Based Vector Processor With Multi-Precision Integer and Floating-Point Support in 65-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs Matteo Perotti, Matheus A. Cavalcante, Alessandro Ottaviano, Jiantao Liu, Luca Benini
2022	—	`conf`	A "New Ara" for Vector Computing: An Open Source Highly Efficient RISC-V V 1.0 Vector Processor Design. ASAP Matteo Perotti, Matheus A. Cavalcante, Nils Wistoff, Renzo Andri, Lukas Cavigelli, Luca Benini
2022	J	`jnl`	A "New Ara" for Vector Computing: An Open Source Highly Efficient RISC-V V 1.0 Vector Processor Design. CoRR Matteo Perotti, Matheus A. Cavalcante, Nils Wistoff, Renzo Andri, Lukas Cavigelli, Luca Benini
2022	J	`jnl`	AXI-Pack: Near-Memory Bus Packing for Bandwidth-Efficient Irregular Workloads. CoRR Chi Zhang, Paul Scheffler, Thomas Benz, Matteo Perotti, Luca Benini
2022	—	`conf`	Darkside: 2.6GFLOPS, 8.7mW Heterogeneous RISC-V Cluster for Extreme-Edge On-Chip DNN Inference and Training. ESSCIRC Angelo Garofalo, Matteo Perotti, Luca Valente, Yvan Tortorella, Alessandro Nadalini, Luca Benini, Davide Rossi, Francesco Conti
2022	A	`conf`	Spatz: A Compact Vector Processing Unit for High-Performance and Energy-Efficient Shared-L1 Clusters. ICCAD Matheus A. Cavalcante, Domenic Wüthrich, Matteo Perotti, Samuel Riedel, Luca Benini
2022	J	`jnl`	Spatz: A Compact Vector Processing Unit for High-Performance and Energy-Efficient Shared-L1 Clusters. CoRR Matheus A. Cavalcante, Domenic Wüthrich, Matteo Perotti, Samuel Riedel, Luca Benini
2021	—	`conf`	RVfplib: A Fast and Compact Open-Source Floating-Point Emulation Library for Tiny RISC-V Processors. SAMOS Matteo Perotti, Giuseppe Tagliavini, Stefan Mach, Luca Bertaccini, Luca Benini
2021	C	`conf`	Tiny-FPU: Low-Cost Floating-Point Support for Small RISC-V MCU Cores. ISCAS Luca Bertaccini, Matteo Perotti, Stefan Mach, Pasquale Davide Schiavone, Florian Zaruba, Luca Benini