Matteo Monchiero

36 papers A* 3A 6B 1C 1Journal 11Unranked 13
YearRankTypeTitle / Venue / Authors
2023 J jnl
Corona: System Implications of Emerging Nanophotonic Technology.
CoRR
Dana Vantrease, Robert Schreiber, Matteo Monchiero, Moray McLaren, Norman P. Jouppi, Marco Fiorentino, Al Davis, Nathan L. Binkert, Raymond G. Beausoleil, Jung Ho Ahn
2023 J jnl
RETROSPECTIVE: Corona: System Implications of Emerging Nanophotonic Technology.
CoRR
Dana Vantrease, Robert Schreiber, Matteo Monchiero, Moray McLaren, Norman P. Jouppi, Marco Fiorentino, Al Davis, Nathan L. Binkert, Raymond G. Beausoleil, Jung Ho Ahn
2013 A conf
Capturing vulnerability variations for register files.
DATE
Javier Carretero, Enric Herrero, Matteo Monchiero, Tanausú Ramírez, Xavier Vera
2011 — conf
Ally: OS-Transparent Packet Inspection Using Sequestered Cores.
ANCS
Jen-Cheng Huang, Matteo Monchiero, Yoshio Turner, Hsien-Hsin S. Lee
2011 — ch.
CMOS Nanophotonics: Technology, System Implications, and a CMP Case Study.
Low Power Networks-on-Chip
Jung Ho Ahn, Raymond G. Beausoleil, Nathan L. Binkert, Al Davis, Marco Fiorentino, Norman P. Jouppi, Moray McLaren, Matteo Monchiero, Naveen Muralimanohar, Robert Schreiber, Dana Vantrease
2011 A* conf
Hardware/software-based diagnosis of load-store queues using expandable activity logs.
HPCA
Javier Carretero, Xavier Vera, Jaume Abella, Tanausú Ramírez, Matteo Monchiero, Antonio González
2009 A conf
A multiprocessor self-reconfigurable JPEG2000 encoder.
IPDPS
Antonino Tumeo, Simone Borgio, Davide Bosisio, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto
2009 J jnl
COTSon: infrastructure for full system simulation.
ACM SIGOPS Oper. Syst. Rev.
Eduardo Argollo, Ayose Falcón, Paolo Faraboschi, Matteo Monchiero, Daniel Ortega
2009 J jnl
How to simulate 1000 cores.
SIGARCH Comput. Archit. News
Matteo Monchiero, Jung Ho Ahn, Ayose Falcón, Daniel Ortega, Paolo Faraboschi
2009 J jnl
Power Management of Datacenter Workloads Using Per-Core Power Gating.
IEEE Comput. Archit. Lett.
Jacob Leverich, Matteo Monchiero, Vanish Talwar, Parthasarathy Ranganathan, Christos Kozyrakis
2009 — conf
Prototyping pipelined applications on a heterogeneous FPGA multiprocessor virtual platform.
ASP-DAC
Antonino Tumeo, Marco Branca, Lorenzo Camerini, Marco Ceriani, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto
2009 B conf
Using Coherence Information and Decay Techniques to Optimize L2 Cache Leakage in CMPs.
ICPP
Matteo Monchiero, Ramon Canal, Antonio González
2008 A* conf
A Comprehensive Memory Modeling Tool and Its Application to the Design and Analysis of Future Memory Hierarchies.
ISCA
Shyamkumar Thoziyoor, Jung Ho Ahn, Matteo Monchiero, Jay B. Brockman, Norman P. Jouppi
2008 A conf
A Dual-Priority Real-Time Multiprocessor System on FPGA for Automotive Applications.
DATE
Antonino Tumeo, Marco Branca, Lorenzo Camerini, Marco Ceriani, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto
2008 C conf
A Modular Approach to Model Heterogeneous MPSoC at Cycle Level.
DSD
Matteo Monchiero, Gianluca Palermo, Cristina Silvano, Oreste Villa
2008 A* conf
Corona: System Implications of Emerging Nanophotonic Technology.
ISCA
Dana Vantrease, Robert Schreiber, Matteo Monchiero, Moray McLaren, Norman P. Jouppi, Marco Fiorentino, Al Davis, Nathan L. Binkert, Raymond G. Beausoleil, Jung Ho Ahn
2008 — conf
Lightweight DMA management mechanisms for multiprocessors on FPGA.
ASAP
Antonino Tumeo, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto
2008 J jnl
Power/Performance/Thermal Design-Space Exploration for Multicore Architectures.
IEEE Trans. Parallel Distributed Syst.
Matteo Monchiero, Ramon Canal, Antonio González
2007 — conf
A Pipelined Fast 2D-DCT Accelerator for FPGA-based SoCs.
ISVLSI
Antonino Tumeo, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto
2007 — conf
A Self-Reconfigurable Implementation of the JPEG Encoder.
ASAP
Antonino Tumeo, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto
2007 — conf
A design kit for a fully working shared memory multiprocessor on FPGA.
ACM Great Lakes Symposium on VLSI
Antonino Tumeo, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto
2007 — conf
An Internal Partial Dynamic Reconfiguration Implementation of the JPEG Encoder for Low-Cost FPGAsb.
ISVLSI
Antonino Tumeo, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto
2007 — conf
An Interrupt Controller for FPGA-based Multiprocessors.
ICSAMOS
Antonino Tumeo, Marco Branca, Lorenzo Camerini, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto
2007 J jnl
Exploration of distributed shared memory architectures for NoC-based multiprocessors.
J. Syst. Archit.
Matteo Monchiero, Gianluca Palermo, Cristina Silvano, Oreste Villa
2007 J jnl
Fast Dynamic Memory Integration in Co-Simulation Frameworks for Multiprocessor System on-Chip
CoRR
Oreste Villa, Patrick Schaumont, Ingrid Verbauwhede, Matteo Monchiero, Gianluca Palermo
2006 J jnl
An efficient synchronization technique for multiprocessor systems on-chip.
SIGARCH Comput. Archit. News
Matteo Monchiero, Gianluca Palermo, Cristina Silvano, Oreste Villa
2006 A conf
Design space exploration for multicore architectures: a power/performance/thermal view.
ICS
Matteo Monchiero, Ramon Canal, Antonio González
2006 J jnl
Efficient Synchronization for Embedded On-Chip Multiprocessors.
IEEE Trans. Very Large Scale Integr. Syst.
Matteo Monchiero, Gianluca Palermo, Cristina Silvano, Oreste Villa
2006 — conf
Exploration of Distributed Shared Memory Architectures for NoC-based Multiprocessors.
ICSAMOS
Matteo Monchiero, Gianluca Palermo, Cristina Silvano, Oreste Villa
2006 — conf
Hardware DWT accelerator for MultiProcessor System-on-Chip on FPGA.
ICSAMOS
Simone Borgio, Davide Bosisio, Fabrizio Ferrandi, Matteo Monchiero, Marco D. Santambrogio, Donatella Sciuto, Antonino Tumeo
2006 A conf
Power/performance hardware optimization for synchronization intensive applications in MPSoCs.
DATE
Matteo Monchiero, Gianluca Palermo, Cristina Silvano, Oreste Villa
2005 — conf
AES Power Attack Based on Induced Cache Miss and Countermeasure.
ITCC (1)
Guido Bertoni, Vittorio Zaccaria, Luca Breveglieri, Matteo Monchiero, Gianluca Palermo
2005 A conf
Fast Dynamic Memory Integration in Co-Simulation Frameworks for Multiprocessor System on-Chip.
DATE
Oreste Villa, Patrick Schaumont, Ingrid Verbauwhede, Matteo Monchiero, Gianluca Palermo
2005 J jnl
Low-power branch prediction techniques for VLIW architectures: a compiler-hints based approach.
Integr.
Matteo Monchiero, Gianluca Palermo, Mariagiovanna Sami, Cristina Silvano, Vittorio Zaccaria, Roberto Zafalon
2005 — conf
The Combined Perceptron Branch Predictor.
Euro-Par
Matteo Monchiero, Gianluca Palermo
2004 — conf
Power-aware branch prediction techniques: a compiler-hints based approach for VLIW processors.
ACM Great Lakes Symposium on VLSI
Matteo Monchiero, Gianluca Palermo, Mariagiovanna Sami, Cristina Silvano, Vittorio Zaccaria, Roberto Zafalon