Mathias Soeken

201 papers A* 10A 34B 4C 29Misc 2Journal 55Unranked 64

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	Back-end-aware Fault-tolerant Quantum Oracle Synthesis. ASP-DAC Mingfei Yu, Alessandro Tempia Calvino, Mathias Soeken, Giovanni De Micheli
2025	—	`conf`	Quantum system architecture for utility scale: Keynote. CF Mathias Soeken
2024	Misc	`conf`	Utilizing Resource Estimation for the Development of Quantum Computing Applications. QCE Nils Quetschlich, Mathias Soeken, Prakash Murali, Robert Wille
2023	—	`conf`	Using Azure Quantum Resource Estimator for Assessing Performance of Fault Tolerant Quantum Computation. SC Workshops Wim van Dam, Mariia Mykhailova, Mathias Soeken
2022	J	`jnl`	A Q# Implementation of a Quantum Lookup Table for Quantum Arithmetic Functions. CoRR Rajiv Krishnakumar, Mathias Soeken, Martin Roetteler, William J. Zeng
2022	J	`jnl`	Advances in Quantum Computation and Quantum Technologies: A Design Automation Perspective. IEEE J. Emerg. Sel. Topics Circuits Syst. Giovanni De Micheli, Jie-Hong R. Jiang, Robert Rand, Kaitlin N. Smith, Mathias Soeken
2022	J	`jnl`	Assessing requirements to scale to practical quantum advantage. CoRR Michael E. Beverland, Prakash Murali, Matthias Troyer, Krysta M. Svore, Torsten Hoefler, Vadym Kliuchnikov, Guang Hao Low, Mathias Soeken, Aarthi Sundaram, Alexander Vaschillo
2022	A*	`conf`	Automatic oracle generation in microsoft's quantum development kit using QIR and LLVM passes. DAC Mathias Soeken, Mariia Mykhailova
2022	J	`jnl`	Design and Automation for Quantum Computation and Quantum Technologies. IEEE J. Emerg. Sel. Topics Circuits Syst. Jie-Hong R. Jiang, Giovanni De Micheli, Kaitlin N. Smith, Mathias Soeken
2022	J	`jnl`	Lowering the T-depth of Quantum Circuits via Logic Network Optimization. ACM Trans. Quantum Comput. Thomas Häner, Mathias Soeken
2022	J	`jnl`	QParallel: Explicit Parallelism for Programming Quantum Computers. CoRR Thomas Häner, Vadym Kliuchnikov, Martin Roetteler, Mathias Soeken, Alexander Vaschillo
2022	J	`jnl`	Space-time optimized table lookup. CoRR Thomas Häner, Vadym Kliuchnikov, Martin Roetteler, Mathias Soeken
2022	J	`jnl`	The multiplicative complexity of interval checking. CoRR Thomas Häner, Mathias Soeken
2022	J	`jnl`	The multiplicative complexity of interval checking. IACR Cryptol. ePrint Arch. Thomas Häner, Mathias Soeken
2021	A	`conf`	A Resource Estimation and Verification Workflow in Q# Special session paper. DATE Mathias Soeken, Mariia Mykhailova, Vadym Kliuchnikov, Christopher E. Granade, Alexander Vaschillo
2021	—	`conf`	Testing Quantum Programs using Q# and Microsoft Quantum Development Kit. Q-SET@QCE Mariia Mykhailova, Mathias Soeken
2021	J	`jnl`	Three-Input Gates for Logic Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Dewmini Sudara Marakkalage, Eleonora Testa, Heinz Riener, Alan Mishchenko, Mathias Soeken, Giovanni De Micheli
2020	A	`conf`	A Logic Synthesis Toolbox for Reducing the Multiplicative Complexity in Logic Networks. DATE Eleonora Testa, Mathias Soeken, Heinz Riener, Luca G. Amarù, Giovanni De Micheli
2020	J	`jnl`	A Logic Synthesis Toolbox for Reducing the Multiplicative Complexity in Logic Networks. IACR Cryptol. ePrint Arch. Eleonora Testa, Mathias Soeken, Heinz Riener, Luca G. Amarù, Giovanni De Micheli
2020	J	`jnl`	A Spectral Algorithm for 3-valued Function Equivalence Classification. J. Multiple Valued Log. Soft Comput. D. Michael Miller, Mathias Soeken
2020	J	`jnl`	Advanced Functional Decomposition Using Majority and Its Applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Zhufei Chu, Mathias Soeken, Yinshui Xia, Lun-Yao Wang, Giovanni De Micheli
2020	—	`conf`	Automatic Uniform Quantum State Preparation Using Decision Diagrams. ISMVL Fereshte Mozafari, Mathias Soeken, Heinz Riener, Giovanni De Micheli
2020	J	`jnl`	Automatic accuracy management of quantum programs via (near-)symbolic resource estimation. CoRR Giulia Meuli, Mathias Soeken, Martin Roetteler, Thomas Häner
2020	J	`jnl`	Determining the Multiplicative Complexity of Boolean Functions using SAT. CoRR Mathias Soeken
2020	J	`jnl`	Determining the Multiplicative Complexity of Boolean Functions using SAT. IACR Cryptol. ePrint Arch. Mathias Soeken
2020	J	`jnl`	Enabling accuracy-aware Quantum compilers using symbolic resource estimation. Proc. ACM Program. Lang. Giulia Meuli, Mathias Soeken, Martin Roetteler, Thomas Häner
2020	C	`conf`	Enumerating Optimal Quantum Circuits using Spectral Classification. ISCAS Giulia Meuli, Mathias Soeken, Martin Roetteler, Giovanni De Micheli
2020	A	`conf`	Exact DAG-Aware Rewriting. DATE Heinz Riener, Alan Mishchenko, Mathias Soeken
2020	J	`jnl`	Extending Boolean Methods for Scalable Logic Synthesis. IEEE Access Eleonora Testa, Luca G. Amarù, Mathias Soeken, Alan Mishchenko, Patrick Vuillod, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
2020	C	`conf`	Improved Quantum Circuits for Elliptic Curve Discrete Logarithms. PQCrypto Thomas Häner, Samuel Jaques, Michael Naehrig, Martin Roetteler, Mathias Soeken
2020	J	`jnl`	Improved Quantum Circuits for Elliptic Curve Discrete Logarithms. IACR Cryptol. ePrint Arch. Thomas Häner, Samuel Jaques, Michael Naehrig, Martin Roetteler, Mathias Soeken
2020	J	`jnl`	Improved quantum circuits for elliptic curve discrete logarithms. CoRR Thomas Häner, Samuel Jaques, Michael Naehrig, Martin Roetteler, Mathias Soeken
2020	J	`jnl`	Lowering the T-depth of Quantum Circuits By Reducing the Multiplicative Depth Of Logic Networks. CoRR Thomas Häner, Mathias Soeken
2020	A	`conf`	Multiplier Architectures: Challenges and Opportunities with Plasmonic-based Logic : (Special Session Paper). DATE Eleonora Testa, Samantha Lubaba Noor, Odysseas Zografos, Mathias Soeken, Francky Catthoor, Azad Naeemi, Giovanni De Micheli
2020	Misc	`conf`	Quantum Circuits for Functionally Controlled NOT Gates. QCE Mathias Soeken, Martin Roetteler
2020	J	`jnl`	Quantum Circuits for Functionally Controlled NOT Gates. CoRR Mathias Soeken, Martin Roetteler
2020	J	`jnl`	SAT-Based Exact Synthesis: Encodings, Topology Families, and Parallelism. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Winston Haaswijk, Mathias Soeken, Alan Mishchenko, Giovanni De Micheli
2020	—	`conf`	Symbolic Algorithms for Token Swapping. ISMVL Bruno Schmitt, Mathias Soeken, Giovanni De Micheli
2019	—	`conf`	A Hybrid Method for Spectral Translation Equivalent Boolean Functions. PACRIM Mathias Soeken, Eleonora Testa, D. Michael Miller
2019	A	`conf`	Compiling Permutations for Superconducting QPUs. DATE Mathias Soeken, Fereshte Mozafari, Bruno Schmitt, Giovanni De Micheli
2019	C	`conf`	Exact Synthesis of Boolean Functions in Majority-of-Five Forms. ISCAS Zhufei Chu, Winston Haaswijk, Mathias Soeken, Yinshui Xia, Lun-Yao Wang, Giovanni De Micheli
2019	J	`jnl`	LUT-Based Hierarchical Reversible Logic Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Mathias Soeken, Martin Roetteler, Nathan Wiebe, Giovanni De Micheli
2019	—	`conf`	Logic Optimization of Majority-Inverter Graphs. MBMV Heinz Riener, Eleonora Testa, Winston Haaswijk, Alan Mishchenko, Luca G. Amarù, Giovanni De Micheli, Mathias Soeken
2019	J	`jnl`	Logic Synthesis for Established and Emerging Computing. Proc. IEEE Eleonora Testa, Mathias Soeken, Luca Gaetano Amarù, Giovanni De Micheli
2019	J	`jnl`	Mapping Monotone Boolean Functions into Majority. IEEE Trans. Computers Eleonora Testa, Mathias Soeken, Luca Gaetano Amarù, Winston Haaswijk, Giovanni De Micheli
2019	A	`conf`	On-the-fly and DAG-aware: Rewriting Boolean Networks with Exact Synthesis. DATE Heinz Riener, Winston Haaswijk, Alan Mishchenko, Giovanni De Micheli, Mathias Soeken
2019	—	`conf`	ROS: Resource-constrained Oracle Synthesis for Quantum Computers. QPL Giulia Meuli, Mathias Soeken, Martin Roetteler, Giovanni De Micheli
2019	A*	`conf`	Reducing the Multiplicative Complexity in Logic Networks for Cryptography and Security Applications. DAC Eleonora Testa, Mathias Soeken, Luca G. Amarù, Giovanni De Micheli
2019	C	`ed.`	Reversible Computation - 11th International Conference, RC 2019, Lausanne, Switzerland, June 24-25, 2019, Proceedings RC Michael Kirkedal Thomsen, Mathias Soeken
2019	—	`conf`	Reversible Pebble Games for Reducing Qubits in Hierarchical Quantum Circuit Synthesis. ISMVL Debjyoti Bhattacharjee, Mathias Soeken, Srijit Dutta, Anupam Chattopadhyay, Giovanni De Micheli
2019	A	`conf`	Reversible Pebbling Game for Quantum Memory Management. DATE Giulia Meuli, Mathias Soeken, Martin Roetteler, Nikolaj S. Bjørner, Giovanni De Micheli
2019	J	`jnl`	Reversible Pebbling Game for Quantum Memory Management. CoRR Giulia Meuli, Mathias Soeken, Martin Roetteler, Nikolaj S. Bjørner, Giovanni De Micheli
2019	A	`conf`	Scalable Boolean Methods in a Modern Synthesis Flow. DATE Eleonora Testa, Luca G. Amarù, Mathias Soeken, Alan Mishchenko, Patrick Vuillod, Jiong Luo, Christopher Casares, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
2019	A*	`conf`	Scalable Generic Logic Synthesis: One Approach to Rule Them All. DAC Heinz Riener, Eleonora Testa, Winston Haaswijk, Alan Mishchenko, Luca G. Amarù, Giovanni De Micheli, Mathias Soeken
2019	—	`conf`	Scaling-up ESOP Synthesis for Quantum Compilation. ISMVL Bruno Schmitt, Mathias Soeken, Giovanni De Micheli, Alan Mishchenko
2019	—	`conf`	Structural rewriting in XOR-majority graphs. ASP-DAC Zhufei Chu, Mathias Soeken, Yinshui Xia, Lun-Yao Wang, Giovanni De Micheli
2019	A	`conf`	The Role of Multiplicative Complexity in Compiling Low $T$-count Oracle Circuits. ICCAD Giulia Meuli, Mathias Soeken, Earl T. Campbell, Martin Roetteler, Giovanni De Micheli
2019	J	`jnl`	The Role of Multiplicative Complexity in Compiling Low T-count Oracle Circuits. CoRR Giulia Meuli, Mathias Soeken, Earl T. Campbell, Martin Roetteler, Giovanni De Micheli
2019	—	`conf`	Using ZDDs in the mapping of quantum circuits. QPL Mathias Soeken
2018	—	`conf`	A Spectral Algorithm for Ternary Function Classification. ISMVL D. Michael Miller, Mathias Soeken
2018	—	`conf`	A best-fit mapping algorithm to facilitate ESOP-decomposition in Clifford+T quantum network synthesis. ASP-DAC Giulia Meuli, Mathias Soeken, Martin Roetteler, Nathan Wiebe, Giovanni De Micheli
2018	J	`jnl`	Behaviour Driven Development for Hardware Design. IPSJ Trans. Syst. LSI Des. Methodol. Melanie Diepenbeck, Ulrich Kühne, Mathias Soeken, Daniel Große, Rolf Drechsler
2018	A*	`conf`	Canonical computation without canonical representation. DAC Alan Mishchenko, Robert K. Brayton, Ana Petkovska, Mathias Soeken, Luca G. Amarù, Antun Domic
2018	C	`conf`	Deep Learning for Logic Optimization Algorithms. ISCAS Winston Haaswijk, Edo Collins, Benoit Seguin, Mathias Soeken, Frédéric Kaplan, Sabine Süsstrunk, Giovanni De Micheli
2018	—	`conf`	Functional decomposition using majority. ASP-DAC Zhufei Chu, Mathias Soeken, Yinshui Xia, Giovanni De Micheli
2018	A	`conf`	Improvements to boolean resynthesis. DATE Luca Gaetano Amarù, Mathias Soeken, Patrick Vuillod, Jiong Luo, Alan Mishchenko, Janet Olson, Robert K. Brayton, Giovanni De Micheli
2018	—	`conf`	Integrated ESOP Refactoring for Industrial Designs. ICECS Winston Haaswijk, Luca Gaetano Amarù, Patrick Vuillod, Jiong Luo, Mathias Soeken, Giovanni De Micheli
2018	J	`jnl`	Logic Synthesis for RRAM-Based In-Memory Computing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Saeideh Shirinzadeh, Mathias Soeken, Pierre-Emmanuel Gaillardon, Rolf Drechsler
2018	A	`conf`	Majority logic synthesis. ICCAD Luca G. Amarù, Eleonora Testa, Miguel Couceiro, Odysseas Zografos, Giovanni De Micheli, Mathias Soeken
2018	J	`jnl`	Pairs of majority-decomposing functions. Inf. Process. Lett. Mathias Soeken, Eleonora Testa, Alan Mishchenko, Giovanni De Micheli
2018	A	`conf`	Practical exact synthesis. DATE Mathias Soeken, Winston Haaswijk, Eleonora Testa, Alan Mishchenko, Luca Gaetano Amarù, Robert K. Brayton, Giovanni De Micheli
2018	J	`jnl`	Programming Quantum Computers Using Design Automation. CoRR Mathias Soeken, Thomas Häner, Martin Roetteler
2018	A	`conf`	Programming quantum computers using design automation. DATE Mathias Soeken, Thomas Häner, Martin Roetteler
2018	C	`conf`	Quantum Circuits for Floating-Point Arithmetic. RC Thomas Häner, Mathias Soeken, Martin Roetteler, Krysta M. Svore
2018	J	`jnl`	Quantum circuits for floating-point arithmetic. CoRR Thomas Häner, Mathias Soeken, Martin Roetteler, Krysta M. Svore
2018	A*	`conf`	SAT based exact synthesis using DAG topology families. DAC Winston Haaswijk, Alan Mishchenko, Mathias Soeken, Giovanni De Micheli
2018	C	`conf`	SAT-based {CNOT, T} Quantum Circuit Synthesis. RC Giulia Meuli, Mathias Soeken, Giovanni De Micheli
2018	—	`conf`	Size Optimization of MIGs with an Application to QCA and STMG Technologies. NANOARCH Heinz Riener, Eleonora Testa, Luca G. Amarù, Mathias Soeken, Giovanni De Micheli
2018	J	`jnl`	The EPFL Logic Synthesis Libraries. CoRR Mathias Soeken, Heinz Riener, Winston Haaswijk, Giovanni De Micheli
2018	J	`jnl`	The complexity of error metrics. Inf. Process. Lett. Oliver Keszöcze, Mathias Soeken, Rolf Drechsler
2018	—	`conf`	Translating Between the Roots of the Identity in Quantum Computers. ISMVL Wouter Castryck, Jeroen Demeyer, Alexis De Vos, Oliver Keszöcze, Mathias Soeken
2017	J	`jnl`	A PLiM Computer for the Internet of Things. Computer Mathias Soeken, Pierre-Emmanuel Gaillardon, Saeideh Shirinzadeh, Rolf Drechsler, Giovanni De Micheli
2017	—	`conf`	A novel basis for logic rewriting. ASP-DAC Winston Haaswijk, Mathias Soeken, Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
2017	A	`conf`	An adaptive prioritized GECCO Saeideh Shirinzadeh, Mathias Soeken, Daniel Große, Rolf Drechsler
2017	A	`conf`	Busy man's synthesis: Combinational delay optimization with SAT. DATE Mathias Soeken, Giovanni De Micheli, Alan Mishchenko
2017	—	`conf`	Classifying Functions with Exact Synthesis. ISMVL Winston Haaswijk, Eleonora Testa, Mathias Soeken, Giovanni De Micheli
2017	A	`conf`	Design automation and design space exploration for quantum computers. DATE Mathias Soeken, Martin Roetteler, Nathan Wiebe, Giovanni De Micheli
2017	A	`conf`	Enabling exact delay synthesis. ICCAD Luca Gaetano Amarù, Mathias Soeken, Patrick Vuillod, Jiong Luo, Alan Mishchenko, Pierre-Emmanuel Gaillardon, Janet Olson, Robert K. Brayton, Giovanni De Micheli
2017	A	`conf`	Endurance management for resistive Logic-In-Memory computing architectures. DATE Saeideh Shirinzadeh, Mathias Soeken, Pierre-Emmanuel Gaillardon, Giovanni De Micheli, Rolf Drechsler
2017	J	`jnl`	Exact Synthesis of Majority-Inverter Graphs and Its Applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Mathias Soeken, Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
2017	A*	`conf`	Hierarchical Reversible Logic Synthesis Using LUTs. DAC Mathias Soeken, Martin Roetteler, Nathan Wiebe, Giovanni De Micheli
2017	—	`conf`	Improving Circuit Mapping Performance Through MIG-based Synthesis for Carry Chains. ACM Great Lakes Symposium on VLSI Zhufei Chu, Xifan Tang, Mathias Soeken, Ana Petkovska, Grace Zgheib, Luca Gaetano Amarù, Yinshui Xia, Paolo Ienne, Giovanni De Micheli, Pierre-Emmanuel Gaillardon
2017	—	`conf`	Inverter Propagation and Fan-Out Constraints for Beyond-CMOS Majority-Based Technologies. ISVLSI Eleonora Testa, Odysseas Zografos, Mathias Soeken, Adrien Vaysset, Mauricio Manfrini, Rudy Lauwereins, Giovanni De Micheli
2017	J	`jnl`	Logic Synthesis for Quantum Computing. CoRR Mathias Soeken, Martin Roetteler, Nathan Wiebe, Giovanni De Micheli
2017	—	`conf`	Multi-level logic benchmarks: An exactness study. ASP-DAC Luca Gaetano Amarù, Mathias Soeken, Winston Haaswijk, Eleonora Testa, Patrick Vuillod, Jiong Luo, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
2017	C	`conf`	RM3 based logic synthesis (Special session paper). ISCAS Mathias Soeken, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
2017	A	`conf`	Wave pipelining for majority-based beyond-CMOS technologies. DATE Odysseas Zografos, A. De Meester, Eleonora Testa, Mathias Soeken, Pierre-Emmanuel Gaillardon, Giovanni De Micheli, Luca Gaetano Amarù, Praveen Raghavan, Francky Catthoor, Rudy Lauwereins
2017	J	`jnl`	metaSMT: focus on your application and not on solver integration. Int. J. Softw. Tools Technol. Transf. Heinz Riener, Finn Haedicke, Stefan Frehse, Mathias Soeken, Daniel Große, Rolf Drechsler, Görschwin Fey
2016	C	`conf`	A Fast Symbolic Transformation Based Algorithm for Reversible Logic Synthesis. RC Mathias Soeken, Gerhard W. Dueck, D. Michael Miller
2016	A*	`conf`	An MIG-based compiler for programmable logic-in-memory architectures. DAC Mathias Soeken, Saeideh Shirinzadeh, Pierre-Emmanuel Gaillardon, Luca Gaetano Amarù, Rolf Drechsler, Giovanni De Micheli
2016	C	`conf`	An extension of transformation-based reversible and quantum circuit synthesis. ISCAS Mathias Soeken, Gerhard W. Dueck, Md. Mazder Rahman, D. Michael Miller
2016	J	`jnl`	Ancilla-free synthesis of large reversible functions using binary decision diagrams. J. Symb. Comput. Mathias Soeken, Laura Tague, Gerhard W. Dueck, Rolf Drechsler
2016	—	`conf`	Approximate BDD Optimization with Prioritized ε-Preferred Evolutionary Algorithm. GECCO (Companion) Saeideh Shirinzadeh, Mathias Soeken, Daniel Große, Rolf Drechsler
2016	A	`conf`	Approximation-aware rewriting of AIGs for error tolerant applications. ICCAD Arun Chandrasekharan, Mathias Soeken, Daniel Große, Rolf Drechsler
2016	—	`conf`	BDD minimization for approximate computing. ASP-DAC Mathias Soeken, Daniel Große, Arun Chandrasekharan, Rolf Drechsler
2016	J	`jnl`	Complexity of reversible circuits and their quantum implementations. Theor. Comput. Sci. Nabila Abdessaied, Matthew Amy, Rolf Drechsler, Mathias Soeken
2016	J	`jnl`	Design Automation and Design Space Exploration for Quantum Computers. CoRR Mathias Soeken, Martin Rötteler, Nathan Wiebe, Giovanni De Micheli
2016	—	`conf`	Dynamic NoC buffer allocation for MPSoC timing side channel attack protection. LASCAS Johanna Sepúlveda, Daniel Florez, Mathias Soeken, Jean-Philippe Diguet, Guy Gogniat
2016	J	`jnl`	Embedding of Large Boolean Functions for Reversible Logic. ACM J. Emerg. Technol. Comput. Syst. Mathias Soeken, Robert Wille, Oliver Keszöcze, D. Michael Miller, Rolf Drechsler
2016	C	`conf`	Enumeration of Reversible Functions and Its Application to Circuit Complexity. RC Mathias Soeken, Nabila Abdessaied, Giovanni De Micheli
2016	B	`conf`	Equivalence checking using Gröbner bases. FMCAD Amr A. R. Sayed-Ahmed, Daniel Große, Mathias Soeken, Rolf Drechsler
2016	A	`conf`	Fast generation of lexicographic satisfiable assignments: enabling canonicity in SAT-based applications. ICCAD Ana Petkovska, Alan Mishchenko, Mathias Soeken, Giovanni De Micheli, Robert K. Brayton, Paolo Ienne
2016	B	`conf`	Fast hierarchical NPN classification. FPL Ana Petkovska, Mathias Soeken, Giovanni De Micheli, Paolo Ienne, Alan Mishchenko
2016	A	`conf`	Fast logic synthesis for RRAM-based in-memory computing using Majority-Inverter Graphs. DATE Saeideh Shirinzadeh, Mathias Soeken, Pierre-Emmanuel Gaillardon, Rolf Drechsler
2016	A	`conf`	Formal verification of integer multipliers by combining Gröbner basis with logic reduction. DATE Amr A. R. Sayed-Ahmed, Daniel Große, Ulrich Kühne, Mathias Soeken, Rolf Drechsler
2016	A	`conf`	Heuristic NPN Classification for Large Functions Using AIGs and LEXSAT. SAT Mathias Soeken, Alan Mishchenko, Ana Petkovska, Baruch Sterin, Paolo Ienne, Robert K. Brayton, Giovanni De Micheli
2016	—	`conf`	Inversion optimization in Majority-Inverter Graphs. NANOARCH Eleonora Testa, Mathias Soeken, Odysseas Zografos, Luca Gaetano Amarù, Praveen Raghavan, Rudy Lauwereins, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
2016	C	`conf`	Multi-objective BDD optimization for RRAM based circuit design. DDECS Saeideh Shirinzadeh, Mathias Soeken, Rolf Drechsler
2016	A	`conf`	Multilevel design understanding: from specification to logic (invited paper). ICCAD Sandip Ray, Ian G. Harris, Görschwin Fey, Mathias Soeken
2016	—	`conf`	Notes on Majority Boolean Algebra. ISMVL Anupam Chattopadhyay, Luca Gaetano Amarù, Mathias Soeken, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
2016	A	`conf`	Optimizing Majority-Inverter Graphs with functional hashing. DATE Mathias Soeken, Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
2016	A*	`conf`	Precise error determination of approximated components in sequential circuits with model checking. DAC Arun Chandrasekharan, Mathias Soeken, Daniel Große, Rolf Drechsler
2016	—	`conf`	SAT-Based Combinational and Sequential Dependency Computation. Haifa Verification Conference Mathias Soeken, Pascal Raiola, Baruch Sterin, Bernd Becker, Giovanni De Micheli, Matthias Sauer
2016	J	`jnl`	SyReC: A hardware description language for the specification and synthesis of reversible circuits. Integr. Robert Wille, Eleonora Schönborn, Mathias Soeken, Rolf Drechsler
2016	—	`conf`	Symbolic Error Metric Determination for Approximate Computing. MBMV Arun Chandrasekharan, Daniel Große, Mathias Soeken, Rolf Drechsler
2016	—	`conf`	Technology Mapping of Reversible Circuits to Clifford+T Quantum Circuits. ISMVL Nabila Abdessaied, Matthew Amy, Mathias Soeken, Rolf Drechsler
2016	A*	`conf`	Unlocking efficiency and scalability of reversible logic synthesis using conventional logic synthesis. DAC Mathias Soeken, Anupam Chattopadhyay
2016	J	`jnl`	Verifying the structure and behavior in UML/OCL models using satisfiability solvers. IET Cyper-Phys. Syst.: Theory & Appl. Nils Przigoda, Mathias Soeken, Robert Wille, Rolf Drechsler
2015	—	`conf`	Coverage of OCL Operation Specifications and Invariants. TAP@STAF Mathias Soeken, Julia Seiter, Rolf Drechsler
2015	—	`conf`	Dynamic Template Matching with Mixed-Polarity Toffoli Gates. ISMVL Md. Mazder Rahman, Mathias Soeken, Gerhard W. Dueck
2015	—	`book`	Formal Specification Level - Concepts, Methods, and Algorithms. Mathias Soeken, Rolf Drechsler
2015	—	`conf`	Fredkin-Enabled Transformation-Based Reversible Logic Synthesis. ISMVL Mathias Soeken, Anupam Chattopadhyay
2015	A	`conf`	Multi-Objective BDD Optimization with Evolutionary Algorithms. GECCO Saeideh Shirinzadeh, Mathias Soeken, Rolf Drechsler
2015	C	`conf`	Requirement Phrasing Assistance Using Automatic Quality Assessment. DDECS Arman Allahyari-Abhari, Mathias Soeken, Rolf Drechsler
2015	C	`conf`	Reversible circuit rewriting with simulated annealing. VLSI-SoC Nabila Abdessaied, Mathias Soeken, Gerhard W. Dueck, Rolf Drechsler
2015	C	`conf`	Ricercar: A Language for Describing and Rewriting Reversible Circuits with Ancillae and Its Permutation Semantics. RC Michael Kirkedal Thomsen, Robin Kaarsgaard, Mathias Soeken
2015	J	`jnl`	Self-Inverse Functions and Palindromic Circuits. CoRR Mathias Soeken, Michael Kirkedal Thomsen, Gerhard W. Dueck, D. Michael Miller
2015	B	`conf`	Simulation Graphs for Reverse Engineering. FMCAD Mathias Soeken, Baruch Sterin, Rolf Drechsler, Robert K. Brayton
2015	J	`jnl`	Specification-driven model transformation testing. Softw. Syst. Model. Esther Guerra, Mathias Soeken
2015	C	`conf`	Technology Mapping for Single Target Gate Based Circuits Using Boolean Functional Decomposition. RC Nabila Abdessaied, Mathias Soeken, Rolf Drechsler
2015	—	`conf`	Towards an Automatic Approach for Restricting UML/OCL Invariability Clauses. MoDeVVa@MoDELS Nils Przigoda, Judith Peters, Mathias Soeken, Robert Wille, Rolf Drechsler
2014	J	`jnl`	A framework for reversible circuit complexity. CoRR Mathias Soeken, Nabila Abdessaied, Rolf Drechsler
2014	J	`jnl`	Ancilla-free synthesis of large reversible functions using binary decision diagrams. CoRR Mathias Soeken, Laura Tague, Gerhard W. Dueck, Rolf Drechsler
2014	A	`conf`	Automated and quality-driven requirements engineering. ICCAD Rolf Drechsler, Mathias Soeken, Robert Wille
2014	C	`conf`	Automating the translation of assertions using natural language processing techniques. FDL Mathias Soeken, Christopher B. Harris, Nabila Abdessaied, Ian G. Harris, Rolf Drechsler
2014	—	`conf`	Behaviour Driven Development for Tests and Verification. TAP@STAF Melanie Diepenbeck, Ulrich Kühne, Mathias Soeken, Rolf Drechsler
2014	J	`jnl`	Embedding of Large Boolean Functions for Reversible Logic. CoRR Mathias Soeken, Robert Wille, Oliver Keszöcze, D. Michael Miller, Rolf Drechsler
2014	—	`conf`	Formale Methoden für Alle. MBMV Mathias Soeken, Max Nitze, Rolf Drechsler
2014	C	`conf`	Mapping NCV Circuits to Optimized Clifford+T Circuits. RC D. Michael Miller, Mathias Soeken, Rolf Drechsler
2014	C	`conf`	MetaSMT: a unified interface to SMT-LIB2. FDL Heinz Riener, Mathias Soeken, Clemens Werther, Görschwin Fey, Rolf Drechsler
2014	C	`conf`	Quantum Circuit Optimization by Hadamard Gate Reduction. RC Nabila Abdessaied, Mathias Soeken, Rolf Drechsler
2014	—	`conf`	Requirements Engineering for Cyber-Physical Systems - Challenges in the Context of "Industrie 4.0". APMS (1) Stefan A. Wiesner, Christian Gorldt, Mathias Soeken, Klaus-Dieter Thoben, Rolf Drechsler
2014	—	`conf`	Self-Verification as the Key Technology for Next Generation Electronic Systems. SBCCI Rolf Drechsler, Hoang Minh Le, Mathias Soeken
2014	J	`jnl`	Trading off circuit lines and gate costs in the synthesis of reversible logic. Integr. Robert Wille, Mathias Soeken, D. Michael Miller, Rolf Drechsler
2014	J	`jnl`	Upper bounds for reversible circuits based on Young subgroups. Inf. Process. Lett. Nabila Abdessaied, Mathias Soeken, Michael Kirkedal Thomsen, Rolf Drechsler
2014	—	`conf`	iTac: Aspect Based Sentiment Analysis using Sentiment Trees and Dictionaries. SemEval@COLING Fritjof Bornebusch, Glaucia Cancino, Melanie Diepenbeck, Rolf Drechsler, Smith Djomkam, Alvine Nzeungang Fanseu, Maryam Jalali, Marc Michael, Jamal Mohsen, Max Nitze, Christina Plump, Mathias Soeken, Hubert Fred Tchambo, Toni, Henning Ziegler
2013	—	`conf`	Debugging of Reversible Circuits Using pDDs. ISMVL Laura Tague, Mathias Soeken, Shin-ichi Minato, Rolf Drechsler
2013	A	`conf`	Determining relevant model elements for the verification of UML/OCL specifications. DATE Julia Seiter, Robert Wille, Mathias Soeken, Rolf Drechsler
2013	J	`jnl`	Effect of Negative Control Lines on the Exact Synthesis of Reversible Circuits. J. Multiple Valued Log. Soft Comput. Robert Wille, Mathias Soeken, Nils Przigoda, Rolf Drechsler
2013	—	`conf`	Exact Template Matching Using Boolean Satisfiability. ISMVL Nabila Abdessaied, Mathias Soeken, Robert Wille, Rolf Drechsler
2013	—	`—`	Formal specification level: concepts, methods, and algorithms. Mathias Soeken
2013	—	`ch.`	Formale Spezifikationsebene. Ausgezeichnete Informatikdissertationen Mathias Soeken
2013	—	`conf`	Generierung von OCL-Ausdrücken aus natürlichsprachlichen Beschreibungen. MBMV Mathias Soeken, Robert Wille, Eugen Kuksa, Rolf Drechsler
2013	—	`conf`	Grammar-based program generation based on model finding. IDT Mathias Soeken, Rolf Drechsler
2013	C	`conf`	Hardware-Software Co-Visualization: Developing systems in the holodeck. DDECS Rolf Drechsler, Mathias Soeken
2013	—	`conf`	Improving the mapping of reversible circuits to quantum circuits using multiple target lines. ASP-DAC Robert Wille, Mathias Soeken, Christian Otterstedt, Rolf Drechsler
2013	J	`jnl`	On quantum circuits employing roots of the Pauli matrices. CoRR Mathias Soeken, D. Michael Miller, Rolf Drechsler
2013	C	`conf`	Reducing the Depth of Quantum Circuits Using Additional Circuit Lines. RC Nabila Abdessaied, Robert Wille, Mathias Soeken, Rolf Drechsler
2013	—	`conf`	Text statt C++: Automatisierung des Systementwurfs mit Hilfe natürlicher Sprachverarbeitung. GI-Jahrestagung Rolf Drechsler, Mathias Soeken, Robert Wille
2013	A	`conf`	Towards a generic verification methodology for system models. DATE Robert Wille, Martin Gogolla, Mathias Soeken, Mirco Kuhlmann, Rolf Drechsler
2013	—	`conf`	Towards automatic scenario generation from coverage information. AST@ICSE Melanie Diepenbeck, Mathias Soeken, Daniel Große, Rolf Drechsler
2013	C	`conf`	White Dots do Matter: Rewriting Reversible Logic Circuits. RC Mathias Soeken, Michael Kirkedal Thomsen
2012	—	`conf`	A Synthesis Flow for Sequential Reversible Circuits. ISMVL Mathias Soeken, Robert Wille, Christian Otterstedt, Rolf Drechsler
2012	—	`conf`	Assisted Behavior Driven Development Using Natural Language Processing. TOOLS (50) Mathias Soeken, Robert Wille, Rolf Drechsler
2012	—	`conf`	Behavior Driven Development for circuit design and verification. HLDVT Melanie Diepenbeck, Mathias Soeken, Daniel Große, Rolf Drechsler
2012	—	`conf`	Circuit Line Minimization in the HDL-Based Synthesis of Reversible Logic. ISVLSI Robert Wille, Mathias Soeken, Eleonora Schönborn, Rolf Drechsler
2012	B	`conf`	Completeness-Driven Development. ICGT Rolf Drechsler, Melanie Diepenbeck, Daniel Große, Ulrich Kühne, Hoang Minh Le, Julia Seiter, Mathias Soeken, Robert Wille
2012	A	`conf`	Debugging of inconsistent UML/OCL models. DATE Robert Wille, Mathias Soeken, Rolf Drechsler
2012	A	`conf`	Eliminating invariants in UML/OCL models. DATE Mathias Soeken, Robert Wille, Rolf Drechsler
2012	—	`conf`	Exact Synthesis of Toffoli Gate Circuits with Negative Control Lines. ISMVL Robert Wille, Mathias Soeken, Nils Przigoda, Rolf Drechsler
2012	—	`conf`	Formal Specification Level. FDL (Selected Papers) Rolf Drechsler, Mathias Soeken, Robert Wille
2012	C	`conf`	Formal Specification Level: Towards verification-driven design based on natural language processing. FDL Rolf Drechsler, Mathias Soeken, Robert Wille
2012	—	`conf`	Optimizing the Mapping of Reversible Circuits to Four-Valued Quantum Gate Circuits. ISMVL Mathias Soeken, Zahra Sasanian, Robert Wille, D. Michael Miller, Rolf Drechsler
2012	C	`conf`	Property Checking of Quantum Circuits Using Quantum Multiple-Valued Decision Diagrams. RC Julia Seiter, Mathias Soeken, Robert Wille, Rolf Drechsler
2012	J	`jnl`	RevKit: A Toolkit for Reversible Circuit Design. J. Multiple Valued Log. Soft Comput. Mathias Soeken, Stefan Frehse, Robert Wille, Rolf Drechsler
2012	—	`conf`	Synthesis of reversible circuits with minimal lines for large functions. ASP-DAC Mathias Soeken, Robert Wille, Christoph Hilken, Nils Przigoda, Rolf Drechsler
2012	C	`conf`	Using RC Mathias Soeken, Robert Wille, Shin-ichi Minato, Rolf Drechsler
2011	C	`conf`	Automatic property generation for the formal verification of bus bridges. DDECS Mathias Soeken, Ulrich Kühne, Martin Freibothe, Görschwin Fey, Rolf Drechsler
2011	—	`conf`	Designing a RISC CPU in Reversible Logic. ISMVL Robert Wille, Mathias Soeken, Daniel Große, Eleonora Schönborn, Rolf Drechsler
2011	—	`conf`	Designing a RISC CPU in Reversible Logic. MBMV Robert Wille, Mathias Soeken, Daniel Große, Eleonora Schönborn, Rolf Drechsler
2011	—	`conf`	Encoding OCL Data Types for SAT-Based Verification of UML/OCL Models. TAP@TOOLS Mathias Soeken, Robert Wille, Rolf Drechsler
2011	C	`conf`	RevKit: An Open Source Toolkit for the Design of Reversible Circuits. RC Mathias Soeken, Stefan Frehse, Robert Wille, Rolf Drechsler
2011	—	`conf`	Towards Automatic Property Generation for the Formal Verification of Bus Bridges. MBMV Mathias Soeken, Ulrich Kühne, Martin Freibothe, Görschwin Fey, Rolf Drechsler
2011	—	`conf`	Towards automatic determination of problem bounds for object instantiation in static model verification. MoDeVVa@MoDELS Mathias Soeken, Robert Wille, Rolf Drechsler
2011	A	`conf`	Verifying dynamic aspects of UML models. DATE Mathias Soeken, Robert Wille, Rolf Drechsler
2010	—	`conf`	Hierarchical synthesis of reversible circuits using positive and negative Davio decomposition. IDT Mathias Soeken, Robert Wille, Rolf Drechsler
2010	A*	`conf`	Reducing the number of lines in reversible circuits. DAC Robert Wille, Mathias Soeken, Rolf Drechsler
2010	—	`conf`	Verifying UML/OCL Models Using Boolean Satisfiability. MBMV Mathias Soeken, Robert Wille, Mirco Kuhlmann, Martin Gogolla, Rolf Drechsler
2010	A	`conf`	Verifying UML/OCL models using Boolean satisfiability. DATE Mathias Soeken, Robert Wille, Mirco Kuhlmann, Martin Gogolla, Rolf Drechsler
2010	C	`conf`	Window optimization of reversible and quantum circuits. DDECS Mathias Soeken, Robert Wille, Gerhard W. Dueck, Rolf Drechsler
2008	—	`conf`	Using Higher Levels of Abstraction for Solving Optimization Problems by Boolean Satisfiability. ISVLSI Robert Wille, Daniel Große, Mathias Soeken, Rolf Drechsler