Matheus Trevisan Moreira

24 papers A 1C 3Journal 6Unranked 13

Year	Rank	Type	Title / Venue / Authors
2025	A	`conf`	A 3D Design Methodology for Integrated Wearable SoCs: Enabling Energy Efficiency and Enhanced Performance at Iso-Area Footprint. DATE Huseyin Ekin Sumbul, Arne Symons, Lita Yang, Huichu Liu, Tony F. Wu, Matheus Trevisan Moreira, Debabrata Mohapatra, Abhinav Agarwal, Kaushik Ravindran, Chris Thompson, Yuecheng Li, Edith Beigné
2024	—	`conf`	11.2 A 3D integrated Prototype System-on-Chip for Augmented Reality Applications Using Face-to-Face Wafer Bonded 7nm Logic at <2μm Pitch with up to 40% Energy Reduction at Iso-Area Footprint. ISSCC Tony F. Wu, Huichu Liu, Huseyin Ekin Sumbul, Lita Yang, Dipti Baheti, Jeremy Coriell, William Koven, Anu Krishnan, Mohit Mittal, Matheus Trevisan Moreira, Max Waugaman, Laurent Ye, Edith Beigné
2023	—	`conf`	A QDI Interconnect for 3D Systems Using Industry Standard EDA and Cell Libraries. ASYNC Matheus Trevisan Moreira, William Koven, Tony F. Wu, Huseyin Ekin Sumbul, Edith Beigné
2023	—	`conf`	Validating an Automated Asynchronous Synthesis Environment with a Challenging Design: RISC-V. SBCCI Willian Analdo Nunes, Marcos Luiggi Lemos Sartori, Matheus Trevisan Moreira, Fernando Gehm Moraes, Ney Laert Vilar Calazans
2021	J	`jnl`	A High-Level Modeling Framework for Estimating Hardware Metrics of CNN Accelerators. IEEE Trans. Circuits Syst. I Regul. Pap. Leonardo Rezende Juracy, Matheus Trevisan Moreira, Alexandre de Morais Amory, Alexandre F. Hampel, Fernando Gehm Moraes
2021	—	`conf`	Read your Circuit: Leveraging Word Embedding to Guide Logic Optimization. ASP-DAC Walter Lau Neto, Matheus Trevisan Moreira, Luca G. Amarù, Cunxi Yu, Pierre-Emmanuel Gaillardon
2020	J	`jnl`	A Survey of Aging Monitors and Reconfiguration Techniques. CoRR Leonardo Rezende Juracy, Matheus Trevisan Moreira, Alexandre de Morais Amory, Fernando Gehm Moraes
2020	—	`conf`	Chronos Link: A QDI Interconnect for Modern SoCs. ASYNC Matheus Trevisan Moreira, Stefano Giaconi
2017	J	`jnl`	Optimized Design of an LSSD Scan Cell. IEEE Trans. Very Large Scale Integr. Syst. Leonardo Rezende Juracy, Matheus Trevisan Moreira, Felipe Augusto Kuentzer, Alexandre de Morais Amory
2016	—	`conf`	A standard cell characterization flow for non-standard voltage supplies. SBCCI Matheus Gibiluka, Matheus Trevisan Moreira, Walter Lau Neto, Ney Laert Vilar Calazans
2016	—	`—`	Asynchronous circuits: innovations in components, cell libraries and design templates. Matheus Trevisan Moreira
2016	—	`conf`	Design and analysis of the HF-RISC processor targeting voltage scaling applications. SBCCI Felipe Todeschini Bortolon, Sergio Johann Filho, Matheus Gibiluka, Sergio Bampi, Ney Laert Vilar Calazans, Fabiano Passuelo Hessel, Matheus Trevisan Moreira
2015	C	`conf`	A Bundled-Data Asynchronous Circuit Synthesis Flow Using a Commercial EDA Framework. DSD Matheus Gibiluka, Matheus Trevisan Moreira, Ney Laert Vilar Calazans
2015	—	`conf`	BAT-Hermes: A transition-signaling bundled-data NoC router. LASCAS Matheus Gibiluka, Matheus Trevisan Moreira, Fernando Gehm Moraes, Ney Laert Vilar Calazans
2015	—	`conf`	Blade - A Timing Violation Resilient Asynchronous Template. ASYNC Dylan Hand, Matheus Trevisan Moreira, Hsin-Ho Huang, Danlei Chen, Frederico Butzke, Zhichao Li, Matheus Gibiluka, Melvin A. Breuer, Ney Laert Vilar Calazans, Peter A. Beerel
2015	—	`conf`	Performance Optimization and Analysis of Blade Designs under Delay Variability. ASYNC Dylan Hand, Hsin-Ho Huang, Benmao Cheng, Yang Zhang, Matheus Trevisan Moreira, Melvin A. Breuer, Ney Laert Vilar Calazans, Peter A. Beerel
2015	J	`jnl`	Static Differential NCL Gates: Toward Low Power. IEEE Trans. Circuits Syst. II Express Briefs Matheus Trevisan Moreira, Michel Evandro Arendt, Fernando Gehm Moraes, Ney Laert Vilar Calazans
2014	—	`conf`	A New CMOS Topology for Low-Voltage Null Convention Logic Gates Design. ASYNC Matheus Trevisan Moreira, Michel Evandro Arendt, Ricardo Aquino Guazzelli, Ney Laert Vilar Calazans
2014	J	`jnl`	Beware the Dynamic C-Element. IEEE Trans. Very Large Scale Integr. Syst. Matheus Trevisan Moreira, Fernando Gehm Moraes, Ney Laert Vilar Calazans
2014	—	`conf`	Hardening QDI circuits against transient faults using delay-insensitive maxterm synthesis. ACM Great Lakes Symposium on VLSI Matheus Trevisan Moreira, Ricardo Aquino Guazzelli, Guilherme Heck, Ney Laert Vilar Calazans
2014	J	`jnl`	Spatially Distributed Dual-Spacer Null Convention Logic Design. J. Low Power Electron. Matheus Trevisan Moreira, Guilherme Trojan, Fernando Gehm Moraes, Ney Laert Vilar Calazans
2013	—	`conf`	Design of standard-cell libraries for asynchronous circuits with the ASCEnD flow. ISVLSI Matheus Trevisan Moreira, Ney Laert Vilar Calazans
2013	C	`conf`	LiChEn: Automated Electrical Characterization of Asynchronous Standard Cell Libraries. DSD Matheus Trevisan Moreira, Carlos Henrique Menezes Oliveira, Ney Laert Vilar Calazans, Luciano Copello Ost
2013	C	`conf`	Voltage scaling on C-elements: A speed, power and energy efficiency analysis. ICCD Matheus Trevisan Moreira, Ney Laert Vilar Calazans