Matheus T. Moreira

57 papers A* 2C 6Misc 1Journal 7Unranked 41

Year	Rank	Type	Title / Venue / Authors
2025	A*	`conf`	LLMs: A Driving Force in Next Generation Digital Design Automation. DAC Matheus T. Moreira, Aram H. Markosyan, Chris Cummins, Warren Hunt, Gabriel Synnaeve, Edith Beigné
2021	—	`conf`	A TensorFlow and System Simulator Integration Approach to Estimate Hardware Metrics of Convolution Accelerators. LASCAS Leonardo Rezende Juracy, Matheus T. Moreira, Alexandre M. Amory, Fernando Gehm Moraes
2021	C	`conf`	Quasi Delay Insensitive FIFOs: Design Choices Exploration and Comparison. ISCAS Taciano A. Rodolfo, Marcos L. L. Sartori, Matheus T. Moreira, Ney Laert Vilar Calazans
2021	A*	`conf`	SLAP: A Supervised Learning Approach for Priority Cuts Technology Mapping. DAC Walter Lau Neto, Matheus T. Moreira, Yingjie Li, Luca G. Amarù, Cunxi Yu, Pierre-Emmanuel Gaillardon
2020	—	`conf`	A Frontend using Traditional EDA Tools for the Pulsar QDI Design Flow. ASYNC Marcos L. L. Sartori, Matheus T. Moreira, Ney Laert Vilar Calazans
2020	C	`conf`	Leveraging QDI Robustness to Simplify the Design of IoT Circuits. ISCAS Marcos L. L. Sartori, Rodrigo N. Wuerdig, Matheus T. Moreira, Sergio Bampi, Ney Laert Vilar Calazans
2020	—	`conf`	Test Oriented Design and Layout Generation of an Asynchronous Controller for the Blade Template. ASYNC Felipe A. Kuentzer, Leonardo Rezende Juracy, Matheus T. Moreira, Alexandre M. Amory
2019	—	`conf`	Pulsar: Constraining QDI Circuits Cycle Time Using Traditional EDA Tools. ASYNC Marcos L. L. Sartori, Rodrigo N. Wuerdig, Matheus T. Moreira, Ney Laert Vilar Calazans
2018	J	`jnl`	A DfT Insertion Methodology to Scannable Q-Flop Elements. IEEE Trans. Very Large Scale Integr. Syst. Leonardo Rezende Juracy, Matheus T. Moreira, Felipe A. Kuentzer, Alexandre M. Amory
2018	C	`conf`	An LSSD Compliant Scan Cell for Flip-Flops. ISCAS Leonardo Rezende Juracy, Matheus T. Moreira, Felipe A. Kuentzer, Fernando Gehm Moraes, Alexandre M. Amory
2018	J	`jnl`	Libra: An Automatic Design Methodology for CMOS Complex Gates. IEEE Trans. Circuits Syst. II Express Briefs Maicon Schneider Cardoso, Gustavo H. Smaniotto, Andrei A. O. Bubolz, Matheus T. Moreira, Leomar S. da Rosa Jr., Felipe de Souza Marques
2018	J	`jnl`	NCL Synthesis With Conventional EDA Tools: Technology Mapping and Optimization. IEEE Trans. Circuits Syst. I Regul. Pap. Matheus T. Moreira, Peter A. Beerel, Marcos L. L. Sartori, Ney Laert Vilar Calazans
2018	—	`conf`	Testable Error Detection Logic Design Applied to an Asynchronous Timing Resilient Template. SBCCI Felipe A. Kuentzer, Leonardo Rezende Juracy, Matheus T. Moreira, Alexandre M. Amory
2017	—	`conf`	A comparison of asynchronous QDI templates using static logic. LASCAS Ricardo A. Guazzelli, Matheus T. Moreira, Ney Laert Vilar Calazans
2017	—	`conf`	A post-processing methodology to improve the automatic design of CMOS gates at layout-level. ICECS Gustavo H. Smaniotto, Regis Zanandrea, Maicon Schneider Cardoso, Renato Souza de Souza, Matheus T. Moreira, Felipe S. Marques, Leomar S. da Rosa Jr.
2017	—	`conf`	Estimation methods for static noise margins in CMOS subthreshold logic circuits. SBCCI Felipe T. Bortolon, Fernando Gehm Moraes, Matheus T. Moreira, Sergio Bampi
2017	—	`conf`	Hardening C-elements against metastability. ICECS Leandro S. Heck, Matheus T. Moreira, Ney Laert Vilar Calazans
2017	C	`conf`	Post-processing of supergate networks aiming cell layout optimization. ISCAS Gustavo H. Smaniotto, Regis Zanandrea, Maicon Schneider Cardoso, Renato Souza de Souza, Matheus T. Moreira, Felipe S. Marques, Leomar S. da Rosa Jr.
2017	—	`conf`	Sleep convention logic isochronic fork: an analysis. SBCCI Ricardo A. Guazzelli, Matheus T. Moreira, Walter Lau Neto, Ney Laert Vilar Calazans
2017	—	`conf`	Transistor placement strategies for non-series-parallel cells. MWSCAS Maicon Schneider Cardoso, Gustavo H. Smaniotto, Joao Junior da Silva Machado, Matheus T. Moreira, Leomar S. da Rosa, Felipe de Souza Marques
2016	J	`jnl`	A Fine-Grain, Uniform, Energy-Efficient Delay Element for 2-Phase Bundled-Data Circuits. ACM J. Emerg. Technol. Comput. Syst. Ajay Singhvi, Matheus T. Moreira, Ramy N. Tadros, Ney Laert Vilar Calazans, Peter A. Beerel
2016	J	`jnl`	A Low-Power Low-Area Error-Detecting Latch for Resilient Architectures in 28-nm FDSOI. IEEE Trans. Circuits Syst. II Express Briefs Ramy N. Tadros, Weizhe Hua, Matheus T. Moreira, Ney Laert Vilar Calazans, Peter A. Beerel
2016	J	`jnl`	A processor for IoT applications: An assessment of design space and trade-offs. Microprocess. Microsystems Sergio Johann Filho, Matheus T. Moreira, Leandro S. Heck, Ney Laert Vilar Calazans, Fabiano Passuelo Hessel
2016	—	`conf`	ASCEnD-FreePDK45: An open source standard cell library for asynchronous design. ICECS Carlos Henrique Menezes Oliveira, Matheus T. Moreira, Ricardo A. Guazzelli, Ney Laert Vilar Calazans
2016	—	`conf`	Analysis and Design of Delay Lines for Dynamic Voltage Scaling Applications. ASYNC Ramy N. Tadros, Weizhe Hua, Matheus Gibiluka, Matheus T. Moreira, Ney Laert Vilar Calazans, Peter A. Beerel
2016	—	`conf`	Optimizing cell area by applying an alternative transistor folding technique in an open source physical synthesis CAD tool. LASCAS Gustavo H. Smaniotto, Joao Junior da Silva Machado, Matheus T. Moreira, Adriel Mota Ziesemer, Felipe S. Marques, Leomar S. da Rosa Jr.
2016	J	`jnl`	Testable MUTEX Design. IEEE Trans. Circuits Syst. I Regul. Pap. Yang Zhang, Leandro S. Heck, Matheus T. Moreira, David Zar, Melvin A. Breuer, Ney Laert Vilar Calazans, Peter A. Beerel
2016	—	`conf`	The HF-RISC processor: Performance assessment. LASCAS Sergio Johann Filho, Matheus T. Moreira, Ney Laert Vilar Calazans, Fabiano Passuelo Hessel
2016	—	`conf`	Toward better layout design in ASTRAN CAD tool by using an efficient transistor folding. MWSCAS Gustavo H. Smaniotto, Matheus T. Moreira, Adriel Mota Ziesemer, Felipe S. Marques, Leomar S. da Rosa
2015	—	`conf`	A Fine-Grained, Uniform, Energy-Efficient Delay Element for FD-SOI Technologies. ISVLSI Ajay Singhvi, Matheus T. Moreira, Ramy N. Tadros, Ney Laert Vilar Calazans, Peter A. Beerel
2015	—	`conf`	A digitally controlled oscillator for fine-grained local clock generators in MPSoCs. LASCAS Guilherme Heck, Leandro S. Heck, Matheus T. Moreira, Fernando Gehm Moraes, Ney Laert Vilar Calazans
2015	Misc	`conf`	Analysis and Optimization of Programmable Delay Elements for 2-Phase Bundled-Data Circuits. VLSID Guilherme Heck, Leandro S. Heck, Ajay Singhvi, Matheus T. Moreira, Peter A. Beerel, Ney Laert Vilar Calazans
2015	—	`conf`	Design and Analysis of Testable Mutual Exclusion Elements. ASYNC Yang Zhang, Leandro S. Heck, Matheus T. Moreira, David Zar, Melvin A. Breuer, Ney Laert Vilar Calazans, Peter A. Beerel
2015	—	`conf`	SDDS-NCL Design: Analysis of Supply Voltage Scaling. SBCCI Ricardo A. Guazzelli, Fernando Gehm Moraes, Ney Laert Vilar Calazans, Matheus T. Moreira
2015	—	`conf`	TDTB error detecting latches: Timing violation sensitivity analysis and optimization. ISQED Matheus T. Moreira, Dylan Hand, Peter A. Beerel, Ney Laert Vilar Calazans
2014	—	`conf`	A design flow for physical synthesis of digital cells with ASTRAN. ACM Great Lakes Symposium on VLSI Adriel Ziesemer, Ricardo Reis, Matheus T. Moreira, Michel Evandro Arendt, Ney Laert Vilar Calazans
2014	C	`conf`	Advances on the state of the art in QDI design. VLSI-SoC Matheus T. Moreira, Ney Laert Vilar Calazans
2014	—	`conf`	Automatic layout synthesis with ASTRAN applied to asynchronous cells. LASCAS Adriel Ziesemer, Ricardo Reis, Matheus T. Moreira, Michel Evandro Arendt, Ney Laert Vilar Calazans
2014	—	`conf`	Schmitt trigger on output inverters of NCL gates for soft error hardening: Is it enough? LATW Ricardo A. Guazzelli, Guilherme Heck, Matheus T. Moreira, Ney Laert Vilar Calazans
2014	—	`conf`	Semi-custom NCL Design with Commercial EDA Frameworks: Is it Possible? ASYNC Matheus T. Moreira, Augusto Neutzling, Mayler G. A. Martins, André Inácio Reis, Renato P. Ribas, Ney Calazans
2014	—	`conf`	Tradeoffs between RTO and RTZ in WCHB QDI asynchronous design. ISQED Matheus T. Moreira, Julian J. H. Pontes, Ney Laert Vilar Calazans
2013	C	`conf`	BaBaNoC: An asynchronous network-on-chip described in Balsa. RSP Matheus T. Moreira, Felipe G. Magalhaes, Matheus Gibiluka, Fabiano Hessel, Ney Laert Vilar Calazans
2013	—	`conf`	Charge sharing aware NCL gates design. DFTS Matheus T. Moreira, Bruno S. Oliveira, Fernando Gehm Moraes, Ney Laert Vilar Calazans
2013	—	`conf`	Design of NCL gates with the ASCEnD flow. LASCAS Matheus T. Moreira, Carlos Henrique Menezes Oliveira, Ricardo C. Porto, Ney Laert Vilar Calazans
2013	—	`conf`	Evaluating the scalability of test buses. ISSoC Alexandre M. Amory, Matheus T. Moreira, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Cristiano Lazzari, Marcelo Soares Lubaszewski
2013	—	`conf`	Lasio 3D NoC vertical links serialization: Evaluation of latency and buffer occupancy. SBCCI Yan Ghidini, Matheus T. Moreira, Lucas Brahm, Thais Webber, Ney Calazans, César A. M. Marcon
2013	—	`conf`	NCL+: Return-to-one Null Convention Logic. MWSCAS Matheus T. Moreira, Carlos Henrique Menezes Oliveira, Ricardo C. Porto, Ney Laert Vilar Calazans
2012	—	`conf`	A generic FPGA emulation framework. ICECS Fernando Gehm Moraes, Matheus T. Moreira, Carlos Lucas, D. Correa, Douglas de O. Cardoso, Maurício Cecílio Magnaguagno, Guilherme M. Castilhos, Ney Laert Vilar Calazans
2012	—	`conf`	Electrical characterization of a C-Element with LiChEn. ICECS Matheus T. Moreira, Ney Laert Vilar Calazans
2012	—	`conf`	Impact of C-elements in asynchronous circuits. ISQED Matheus T. Moreira, Bruno Cruz de Oliveira, Fernando Moraes, Ney Calazans
2012	—	`conf`	Return-to-One DIMS logic on 4-phase m-of-n asynchronous circuits. ICECS Matheus T. Moreira, Ricardo A. Guazzelli, Ney Laert Vilar Calazans
2012	—	`conf`	Return-to-one protocol for reducing static power in C-elements of QDI circuits employing m-of-n codes. SBCCI Matheus T. Moreira, Ricardo A. Guazzelli, Ney Laert Vilar Calazans
2011	—	`conf`	A 65nm standard cell set and flow dedicated to automated asynchronous circuits design. SoCC Matheus T. Moreira, Bruno Cruz de Oliveira, Julian J. H. Pontes, Ney Calazans
2011	—	`conf`	Adapting a C-element design flow for low power. ICECS Matheus T. Moreira, Bruno Cruz de Oliveira, Julian J. H. Pontes, Fernando Moraes, Ney Calazans
2010	—	`conf`	Hermes-A - An Asynchronous NoC Router with Distributed Routing. PATMOS Julian J. H. Pontes, Matheus T. Moreira, Fernando Moraes, Ney Calazans
2010	—	`conf`	Hermes-AA: A 65nm asynchronous NoC router with adaptive routing. SoCC Julian J. H. Pontes, Matheus T. Moreira, Fernando Moraes, Ney Calazans
2008	—	`conf`	Hermes-GLP: A GALS Network on Chip Router with Power Control Techniques. ISVLSI Julian J. H. Pontes, Matheus T. Moreira, Rafael Soares, Ney Laert Vilar Calazans