Matheus A. Cavalcante

54 papers A* 3A 6C 1Journal 35Unranked 8

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	A Reliable, Time-Predictable Heterogeneous SoC for AI-Enhanced Mixed-Criticality Edge Applications. CoRR Angelo Garofalo, Alessandro Ottaviano, Matteo Perotti, Thomas Benz, Yvan Tortorella, Robert Balas, Michael Rogenmoser, Chi Zhang, Luca Bertaccini, Nils Wistoff, Maicol Ciani, Cyril Koenig, Mattia Sinigaglia, Luca Valente, Paul Scheffler, Manuel Eggimann, Matheus A. Cavalcante, Francesco Restuccia, Alessandro Biondi, Francesco Conti, Frank K. Gürkaynak, Davide Rossi, Luca Benini
2025	J	`jnl`	A Reliable, Time-Predictable Heterogeneous SoC for AI-Enhanced Mixed-Criticality Edge Applications. IEEE Trans. Circuits Syst. II Express Briefs Angelo Garofalo, Alessandro Ottaviano, Matteo Perotti, Thomas Benz, Yvan Tortorella, Robert Balas, Michael Rogenmoser, Chi Zhang, Luca Bertaccini, Nils Wistoff, Maicol Ciani, Cyril Koenig, Mattia Sinigaglia, Luca Valente, Paul Scheffler, Manuel Eggimann, Matheus A. Cavalcante, Francesco Restuccia, Alessandro Biondi, Francesco Conti, Frank K. Gürkaynak, Davide Rossi, Luca Benini
2025	J	`jnl`	Occamy: A 432-Core Dual-Chiplet Dual-HBM2E 768-DP-GFLOP/s RISC-V System for 8-to-64-bit Dense and Sparse Computing in 12-nm FinFET. IEEE J. Solid State Circuits Paul Scheffler, Thomas Benz, Viviane Potocnik, Tim Fischer, Luca Colagrande, Nils Wistoff, Yichao Zhang, Luca Bertaccini, Gianmarco Ottavi, Manuel Eggimann, Matheus A. Cavalcante, Gianna Paulin, Frank K. Gürkaynak, Davide Rossi, Luca Benini
2025	J	`jnl`	Occamy: A 432-Core Dual-Chiplet Dual-HBM2E 768-DP-GFLOP/s RISC-V System for 8-to-64-bit Dense and Sparse Computing in 12nm FinFET. CoRR Paul Scheffler, Thomas Benz, Viviane Potocnik, Tim Fischer, Luca Colagrande, Nils Wistoff, Yichao Zhang, Luca Bertaccini, Gianmarco Ottavi, Manuel Eggimann, Matheus A. Cavalcante, Gianna Paulin, Frank K. Gürkaynak, Davide Rossi, Luca Benini
2025	J	`jnl`	Spatz: Clustering Compact RISC-V-Based Vector Units to Maximize Computing Efficiency. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Matteo Perotti, Samuel Riedel, Matheus A. Cavalcante, Luca Benini
2024	J	`jnl`	Ara2: Exploring Single- and Multi-Core Vector Processing With an Efficient RVV 1.0 Compliant Open-Source Processor. IEEE Trans. Computers Matteo Perotti, Matheus A. Cavalcante, Renzo Andri, Lukas Cavigelli, Luca Benini
2024	J	`jnl`	Hier-3D: A Methodology for Physical Hierarchy Exploration of 3-D ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Nesara Eranna Bethur, Anthony Agnesina, Moritz Brunion, Alberto García Ortiz, Francky Catthoor, Dragomir Milojevic, Manu Komalan, Matheus A. Cavalcante, Samuel Riedel, Luca Benini, Sung Kyu Lim
2024	A	`conf`	MX: Enhancing RISC-V's Vector ISA for Ultra-Low Overhead, Energy-Efficient Matrix Multiplication. DATE Matteo Perotti, Yichao Zhang, Matheus A. Cavalcante, Enis Mustafa, Luca Benini
2024	J	`jnl`	MX: Enhancing RISC-V's Vector ISA for Ultra-Low Overhead, Energy-Efficient Matrix Multiplication. CoRR Matteo Perotti, Yichao Zhang, Matheus A. Cavalcante, Enis Mustafa, Luca Benini
2024	J	`jnl`	MiniFloats on RISC-V Cores: ISA Extensions With Mixed-Precision Short Dot Products. IEEE Trans. Emerg. Top. Comput. Luca Bertaccini, Gianna Paulin, Matheus A. Cavalcante, Tim Fischer, Stefan Mach, Luca Benini
2024	—	`conf`	Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-Based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET. VLSI Technology and Circuits Gianna Paulin, Paul Scheffler, Thomas Benz, Matheus A. Cavalcante, Tim Fischer, Manuel Eggimann, Yichao Zhang, Nils Wistoff, Luca Bertaccini, Luca Colagrande, Gianmarco Ottavi, Frank K. Gürkaynak, Davide Rossi, Luca Benini
2024	J	`jnl`	Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET. CoRR Gianna Paulin, Paul Scheffler, Thomas Benz, Matheus A. Cavalcante, Tim Fischer, Manuel Eggimann, Yichao Zhang, Nils Wistoff, Luca Bertaccini, Luca Colagrande, Gianmarco Ottavi, Frank K. Gürkaynak, Davide Rossi, Luca Benini
2024	—	`conf`	Spatzformer: An Efficient Reconfigurable Dual-Core RISC-V V Cluster for Mixed Scalar-Vector Workloads. ASAP Matteo Perotti, Michele Raeber, Mattia Sinigaglia, Matheus A. Cavalcante, Davide Rossi, Luca Benini
2024	J	`jnl`	Spatzformer: An Efficient Reconfigurable Dual-Core RISC-V V Cluster for Mixed Scalar-Vector Workloads. CoRR Matteo Perotti, Michele Raeber, Mattia Sinigaglia, Matheus A. Cavalcante, Davide Rossi, Luca Benini
2024	—	`conf`	TeraPool-SDR: An 1.89TOPS 1024 RV-Cores 4MiB Shared-L1 Cluster for Next-Generation Open-Source Software-Defined Radios. ACM Great Lakes Symposium on VLSI Yichao Zhang, Marco Bertuletti, Samuel Riedel, Matheus A. Cavalcante, Alessandro Vanelli-Coralli, Luca Benini
2024	J	`jnl`	TeraPool-SDR: An 1.89TOPS 1024 RV-Cores 4MiB Shared-L1 Cluster for Next-Generation Open-Source Software-Defined Radios. CoRR Yichao Zhang, Marco Bertuletti, Samuel Riedel, Matheus A. Cavalcante, Alessandro Vanelli-Coralli, Luca Benini
2023	J	`jnl`	Ara2: Exploring Single- and Multi-Core Vector Processing with an Efficient RVV1.0 Compliant Open-Source Processor. CoRR Matteo Perotti, Matheus A. Cavalcante, Renzo Andri, Lukas Cavigelli, Luca Benini
2023	—	`—`	Fighting back the von Neumann bottleneck with small- and large-scale vector microprocessors. Matheus A. Cavalcante
2023	J	`jnl`	FlooNoC: A Multi-Tb/s Wide NoC for Heterogeneous AXI4 Traffic. IEEE Des. Test Tim Fischer, Michael Rogenmoser, Matheus A. Cavalcante, Frank K. Gürkaynak, Luca Benini
2023	J	`jnl`	FlooNoC: A Multi-Tbps Wide NoC for Heterogeneous AXI4 Traffic. CoRR Tim Fischer, Michael Rogenmoser, Matheus A. Cavalcante, Frank K. Gürkaynak, Luca Benini
2023	A*	`conf`	HexaMesh: Scaling to Hundreds of Chiplets with an Optimized Chiplet Arrangement. DAC Patrick Iff, Maciej Besta, Matheus A. Cavalcante, Tim Fischer, Luca Benini, Torsten Hoefler
2023	A	`conf`	MemPool Meets Systolic: Flexible Systolic Computation in a Large Shared-Memory Processor Cluster. DATE Samuel Riedel, Gua Hao Khov, Sergio Mazzola, Matheus A. Cavalcante, Renzo Andri, Luca Benini
2023	J	`jnl`	MemPool: A Scalable Manycore Architecture With a Low-Latency Shared L1 Memory. IEEE Trans. Computers Samuel Riedel, Matheus A. Cavalcante, Renzo Andri, Luca Benini
2023	J	`jnl`	MemPool: A Scalable Manycore Architecture with a Low-Latency Shared L1 Memory. CoRR Samuel Riedel, Matheus A. Cavalcante, Renzo Andri, Luca Benini
2023	—	`conf`	MinPool: A 16-core NUMA-L1 Memory RISC-V Processor Cluster for Always-on Image Processing in 65nm CMOS. ICECS Samuel Riedel, Matheus A. Cavalcante, Manos Frouzakis, Domenic Wüthrich, Enis Mustafa, Arlind Billa, Luca Benini
2023	A*	`conf`	PATRONoC: Parallel AXI Transport Reducing Overhead for Networks-on-Chip targeting Multi-Accelerator DNN Platforms at the Edge. DAC Vikram Jain, Matheus A. Cavalcante, Nazareno Bruschi, Michael Rogenmoser, Thomas Benz, Andreas Kurth, Davide Rossi, Luca Benini, Marian Verhelst
2023	J	`jnl`	PATRONoC: Parallel AXI Transport Reducing Overhead for Networks-on-Chip targeting Multi-Accelerator DNN Platforms at the Edge. CoRR Vikram Jain, Matheus A. Cavalcante, Nazareno Bruschi, Michael Rogenmoser, Thomas Benz, Andreas Kurth, Davide Rossi, Luca Benini, Marian Verhelst
2023	C	`conf`	Quark: An Integer RISC-V Vector Processor for Sub-Byte Quantized DNN Inference. ISCAS MohammadHossein AskariHemmat, Théo Dupuis, Yoan Fournier, Nizar El Zarif, Matheus A. Cavalcante, Matteo Perotti, Frank K. Gürkaynak, Luca Benini, François Leduc-Primeau, Yvon Savaria, Jean-Pierre David
2023	J	`jnl`	Quark: An Integer RISC-V Vector Processor for Sub-Byte Quantized DNN Inference. CoRR MohammadHossein AskariHemmat, Théo Dupuis, Yoan Fournier, Nizar El Zarif, Matheus A. Cavalcante, Matteo Perotti, Frank K. Gürkaynak, Luca Benini, François Leduc-Primeau, Yvon Savaria, Jean-Pierre David
2023	A*	`conf`	Sparse Hamming Graph: A Customizable Network-on-Chip Topology. DAC Patrick Iff, Maciej Besta, Matheus A. Cavalcante, Tim Fischer, Luca Benini, Torsten Hoefler
2023	J	`jnl`	Spatz: Clustering Compact RISC-V-Based Vector Units to Maximize Computing Efficiency. CoRR Matheus A. Cavalcante, Matteo Perotti, Samuel Riedel, Luca Benini
2023	J	`jnl`	Yun: An Open-Source, 64-Bit RISC-V-Based Vector Processor With Multi-Precision Integer and Floating-Point Support in 65-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs Matteo Perotti, Matheus A. Cavalcante, Alessandro Ottaviano, Jiantao Liu, Luca Benini
2022	—	`conf`	A "New Ara" for Vector Computing: An Open Source Highly Efficient RISC-V V 1.0 Vector Processor Design. ASAP Matteo Perotti, Matheus A. Cavalcante, Nils Wistoff, Renzo Andri, Lukas Cavigelli, Luca Benini
2022	J	`jnl`	A "New Ara" for Vector Computing: An Open Source Highly Efficient RISC-V V 1.0 Vector Processor Design. CoRR Matteo Perotti, Matheus A. Cavalcante, Nils Wistoff, Renzo Andri, Lukas Cavigelli, Luca Benini
2022	J	`jnl`	An Open-Source Platform for High-Performance Non-Coherent On-Chip Communication. IEEE Trans. Computers Andreas Kurth, Wolfgang Rönninger, Thomas Benz, Matheus A. Cavalcante, Fabian Schuiki, Florian Zaruba, Luca Benini
2022	J	`jnl`	HexaMesh: Scaling to Hundreds of Chiplets with an Optimized Chiplet Arrangement. CoRR Patrick Iff, Maciej Besta, Matheus A. Cavalcante, Tim Fischer, Luca Benini, Torsten Hoefler
2022	A	`conf`	Hier-3D: A Hierarchical Physical Design Methodology for Face-to-Face-Bonded 3D ICs. ISLPED Anthony Agnesina, Moritz Brunion, Alberto García Ortiz, Francky Catthoor, Dragomir Milojevic, Manu Komalan, Matheus A. Cavalcante, Samuel Riedel, Luca Benini, Sung Kyu Lim
2022	A	`conf`	MemPool-3D: Boosting Performance and Efficiency of Shared-L1 Memory Many-Core Clusters with 3D Integration. DATE Matheus A. Cavalcante, Anthony Agnesina, Samuel Riedel, Moritz Brunion, Alberto García-Ortiz, Dragomir Milojevic, Francky Catthoor, Sung Kyu Lim, Luca Benini
2022	—	`conf`	Soft Tiles: Capturing Physical Implementation Flexibility for Tightly-Coupled Parallel Processing Clusters. ISVLSI Gianna Paulin, Matheus A. Cavalcante, Paul Scheffler, Luca Bertaccini, Yichao Zhang, Frank K. Gürkaynak, Luca Benini
2022	J	`jnl`	Soft Tiles: Capturing Physical Implementation Flexibility for Tightly-Coupled Parallel Processing Clusters. CoRR Gianna Paulin, Matheus A. Cavalcante, Paul Scheffler, Luca Bertaccini, Yichao Zhang, Frank K. Gürkaynak, Luca Benini
2022	J	`jnl`	Sparse Hamming Graph: A Customizable Network-on-Chip Topology. CoRR Patrick Iff, Maciej Besta, Matheus A. Cavalcante, Tim Fischer, Luca Benini, Torsten Hoefler
2022	A	`conf`	Spatz: A Compact Vector Processing Unit for High-Performance and Energy-Efficient Shared-L1 Clusters. ICCAD Matheus A. Cavalcante, Domenic Wüthrich, Matteo Perotti, Samuel Riedel, Luca Benini
2022	J	`jnl`	Spatz: A Compact Vector Processing Unit for High-Performance and Energy-Efficient Shared-L1 Clusters. CoRR Matheus A. Cavalcante, Domenic Wüthrich, Matteo Perotti, Samuel Riedel, Luca Benini
2021	J	`jnl`	MemPool-3D: Boosting Performance and Efficiency of Shared-L1 Memory Many-Core Clusters with 3D Integration. CoRR Matheus A. Cavalcante, Anthony Agnesina, Samuel Riedel, Moritz Brunion, Alberto García-Ortiz, Dragomir Milojevic, Francky Catthoor, Sung Kyu Lim, Luca Benini
2021	A	`conf`	MemPool: A Shared-L1 Memory Many-Core Cluster with a Low-Latency Interconnect. DATE Matheus A. Cavalcante, Samuel Riedel, Antonio Pullini, Luca Benini
2020	J	`jnl`	An Open-Source Platform for High-Performance Non-Coherent On-Chip Communication. CoRR Andreas Kurth, Wolfgang Rönninger, Thomas Benz, Matheus A. Cavalcante, Fabian Schuiki, Florian Zaruba, Luca Benini
2020	J	`jnl`	Ara: A 1-GHz+ Scalable and Energy-Efficient RISC-V Vector Processor With Multiprecision Floating-Point Support in 22-nm FD-SOI. IEEE Trans. Very Large Scale Integr. Syst. Matheus A. Cavalcante, Fabian Schuiki, Florian Zaruba, Michael Schaffner, Luca Benini
2020	—	`conf`	Design of an open-source bridge between non-coherent burst-based and coherent cache-line-based memory systems. CF Matheus A. Cavalcante, Andreas Kurth, Fabian Schuiki, Luca Benini
2020	J	`jnl`	MemPool: A Shared-L1 Memory Many-Core Cluster with a Low-Latency Interconnect. CoRR Matheus A. Cavalcante, Samuel Riedel, Antonio Pullini, Luca Benini
2019	J	`jnl`	Ara: A 1 GHz+ Scalable and Energy-Efficient RISC-V Vector Processor with Multi-Precision Floating Point Support in 22 nm FD-SOI. CoRR Matheus A. Cavalcante, Fabian Schuiki, Florian Zaruba, Michael Schaffner, Luca Benini
2018	J	`jnl`	Evolutionary Multiobjective Strategy for Regenerator Placement in Elastic Optical Networks. IEEE Trans. Commun. Matheus A. Cavalcante, Helder A. Pereira, Daniel A. R. Chaves, Raul C. Almeida Jr.
2018	J	`jnl`	Optimizing the cost function of power series routing algorithm for transparent elastic optical networks. Opt. Switch. Netw. Matheus A. Cavalcante, Helder A. Pereira, Daniel A. R. Chaves, Raul C. Almeida Jr.
2017	J	`jnl`	SimEON: an open-source elastic optical network simulator for academic and industrial purposes. Photonic Netw. Commun. Matheus A. Cavalcante, Helder A. Pereira, Raul C. Almeida Jr.
2016	—	`conf`	A case study of regenerator placement and regenerator assignment in dynamic translucent elastic optical networks. ICTON Daniel A. R. Chaves, Matheus A. Cavalcante, Helder A. Pereira, Raul C. Almeida