Mateusz Majer

26 papers A 1B 5C 2Misc 1Journal 5Unranked 9
YearRankTypeTitle / Venue / Authors
2011 — —
The Erlangen Slot Machine - An FPGA-Based Partially Reconfigurable Computer.
Mateusz Majer
2010 — ch.
Erlangen Slot Machine: An FPGA-Based Dynamically Reconfigurable Computing Platform.
Dynamically Reconfigurable Systems
Josef Angermeier, Christophe Bobda, Mateusz Majer, Jürgen Teich
2010 — ch.
ReCoNodes - Optimization Methods for Module Scheduling and Placement on Reconfigurable Hardware Devices.
Dynamically Reconfigurable Systems
Ali Ahmadinia, Josef Angermeier, Sándor P. Fekete, Tom Kamphans, Dirk Koch, Mateusz Majer, Nils Schweer, Jürgen Teich, Christopher Tessars, Jan van der Veen
2008 C conf
Co-design Architecture and Implementation for Point-Based Rendering on FPGAs.
IEEE International Workshop on Rapid System Prototyping
Mateusz Majer, Stefan Wildermann, Josef Angermeier, Stefan Hanke, Jürgen Teich
2008 B conf
Fine grain reconfigurable architectures.
FPL
Josef Angermeier, Mateusz Majer, Jürgen Teich, Lars Braun, Tobias Schwalb, Philipp Graf, Michael Hübner, Jürgen Becker, Enno Lübbers, Marco Platzner, Christopher Claus, Walter Stechele, Andreas Herkersdorf, Markus Rullmann, Renate Merker
2008 J jnl
Offline and Online Aspects of Defragmenting the Module Layout of a Partially Reconfigurable Device.
IEEE Trans. Very Large Scale Integr. Syst.
Sándor P. Fekete, Jan van der Veen, Ali Ahmadinia, Diana Göhringer, Mateusz Majer, Jürgen Teich
2008 — conf
Reconfigurable HW/SW Architecture of a Real-Time Driver Assistance System.
ARC
Josef Angermeier, Ulrich Batzer, Mateusz Majer, Jürgen Teich, Christopher Claus, Walter Stechele
2007 J jnl
The Erlangen Slot Machine - A Platform for Interdisciplinary Research in Dynamically Reconfigurable Computing (ESM - Eine Hardware-Plattform für interdisziplinäre Forschung im Bereich des dynamischen rekonfigurierbaren Rechnens).
it Inf. Technol.
Josef Angermeier, Diana Göhringer, Mateusz Majer, Jürgen Teich, Sándor P. Fekete, Jan van der Veen
2007 J jnl
The Erlangen Slot Machine: A Dynamically Reconfigurable FPGA-based Computer.
J. VLSI Signal Process.
Mateusz Majer, Jürgen Teich, Ali Ahmadinia, Christophe Bobda
2006 — conf
A Flexible Reconfiguration Manager for the Erlangen Slot Machine.
ARCS Workshops
Mateusz Majer, Ali Ahmadinia, Christophe Bobda, Jürgen Teich
2006 B conf
An FPGA-Based Dynamically Reconfigurable Platform: From Concept to Realization.
FPL
Mateusz Majer
2006 — conf
Bridging the Gap between Relocatability and Available Technology: The Erlangen Slot Machine.
Dynamically Reconfigurable Architectures
Diana Göhringer, Mateusz Majer, Jürgen Teich
2006 B conf
Minimizing Communication Cost for Reconfigurable Slot Modules.
FPL
Sándor P. Fekete, Jan van der Veen, Mateusz Majer, Jürgen Teich
2005 J jnl
A Practical Approach for Circuit Routing on Dynamic Reconfigurable Devices
CoRR
Ali Ahmadinia, Christophe Bobda, Ji Ding, Mateusz Majer, Jürgen Teich, Sándor P. Fekete, Jan van der Veen
2005 C conf
A Practical Approach for Circuit Routing on Dynamic Reconfigurable Devices.
IEEE International Workshop on Rapid System Prototyping
Ali Ahmadinia, Christophe Bobda, Ji Ding, Mateusz Majer, Jürgen Teich, Sándor P. Fekete, Jan van der Veen
2005 — conf
Defragmenting the Module Layout of a Partially Reconfigurable Device.
ERSA
Jan van der Veen, Sándor P. Fekete, Mateusz Majer, Ali Ahmadinia, Christophe Bobda, Frank Hannig, Jürgen Teich
2005 J jnl
DyNoC: A Dynamic Infrastructure for Communication in Dynamically Reconfigurable Devices
CoRR
Christophe Bobda, Ali Ahmadinia, Mateusz Majer, Jürgen Teich, Sándor P. Fekete, Jan van der Veen
2005 B conf
DyNoC: A Dynamic Infrastructure for Communication in Dynamically Reconfigurable Devices.
FPL
Christophe Bobda, Ali Ahmadinia, Mateusz Majer, Jürgen Teich, Sándor P. Fekete, Jan van der Veen
2005 A conf
Packet Routing in Dynamically Changing Networks on Chip.
IPDPS
Mateusz Majer, Christophe Bobda, Ali Ahmadinia, Jürgen Teich
2005 — conf
Partial Configuration Design and Implementation Challenges on Xilinx Virtex FPGAs.
ARCS Workshops
Christophe Bobda, Ali Ahmadinia, Kurapati Rajesham, Mateusz Majer, Adronis Niyonkuru
2005 Misc conf
The Erlangen Slot Machine: A Highly Flexible FPGA-Based Reconfigurable Platform.
FCCM
Christophe Bobda, Mateusz Majer, Ali Ahmadinia, Thomas Haller, André Linarth, Jürgen Teich, Sándor P. Fekete, Jan van der Veen
2005 — conf
The Erlangen Slot Machine: Increasing Flexibility in FPGA-Based Reconfigurable Platforms.
FPT
Christophe Bobda, Mateusz Majer, Ali Ahmadinia, Thomas Haller, André Linarth, Jürgen Teich
2004 B conf
A Dynamic NoC Approach for Communication in Reconfigurable Devices.
FPL
Christophe Bobda, Mateusz Majer, Dirk Koch, Ali Ahmadinia, Jürgen Teich
2004 — conf
Adaptive architectures for an OTN processor: reducing design costs through reconfigurability and multiprocessing.
Conf. Computing Frontiers
Tudor Murgan, Mihail Petrov, Mateusz Majer, Peter Zipf, Manfred Glesner, Ulrich Heinkel, Jörg Pleickhardt, Bernd Bleisteiner
2004 — conf
Flexible Overhead Processing Architectures for G.709 Optical Transport Networks.
MBMV
Tudor Murgan, Mihail Petrov, Mateusz Majer, Peter Zipf, Manfred Glesner, Ulrich Heinkel
2004 — conf
Task scheduling for heterogeneous reconfigurable computers.
SBCCI
Ali Ahmadinia, Christophe Bobda, Dirk Koch, Mateusz Majer, Jürgen Teich