Mateo Valero

496 papers A* 58A 65B 53C 31Misc 8Journal 147Unranked 131
YearRankTypeTitle / Venue / Authors
2026 J jnl
LACIN: Linearly Arranged Complete Interconnection Networks.
IEEE Comput. Archit. Lett.
Ramón Beivide, Cristóbal Camarero, Carmen Martínez, Enrique Vallejo, Mateo Valero
2026 J jnl
LACIN: Linearly Arranged Complete Interconnection Networks.
CoRR
Ramón Beivide, Cristóbal Camarero, Carmen Martínez, Enrique Vallejo, Mateo Valero
2024 A* conf
QUETZAL: Vector Acceleration Framework for Modern Genome Sequence Analysis Algorithms.
ISCA
Julian Pavon, Iván Vargas Valdivieso, Carlos Rojas, César Hernández, Mehmet Aslan, Roger Figueras, Yichao Yuan, Joël Lindegger, Mohammed Alser, Francesc Moll, Santiago Marco-Sola, Oguz Ergin, Nishil Talati, Onur Mutlu, Osman S. Unsal, Mateo Valero, Adrián Cristal
2023 — conf
Sargantana: An Academic SoC RISC-V Processor in 22nm FDSOI Technology.
DCIS
Max Doblas, Gerard Candón, Xavier Carril, Marc Domínguez, Enric Erra, Alberto González, César Hernández, Víctor Jiménez, Vatistas Kostalampros, Rubén Langarita, Neiel Leyva, Guillem López-Paradís, Jonnatan Mendoza, Josep Oltra, Julián Pavón, Cristóbal Ramírez, Narcís Rodas, Enrico Reggiani, Mario Rodríguez, Carlos Rojas, Abraham Ruiz, Hugo Safadi, Víctor Soria, Alejandro Suanes, Iván Vargas, Fernando Arreza, Roger Figueras, Pau Fontova-Musté, Joan Marimon, Ricardo Martínez, Sergio Moreno, Jordi Sacristán, Oscar Alonso, Xavier Aragonès, Adrián Cristal, Ángel Diéguez, Manuel López, Diego Mateo, Francesc Moll, Miquel Moretó, Oscar Palomar, Marco A. Ramírez, Francisco Serra-Graells, Nehir Sönmez, Lluís Terés, Osman S. Unsal, Mateo Valero, Luis Villa
2023 A* conf
VAQUERO: A Scratchpad-based Vector Accelerator for Query Processing.
HPCA
Julián Pavón, Iván Vargas Valdivieso, Joan Marimon, Roger Figueras, Francesc Moll, Osman S. Unsal, Mateo Valero, Adrián Cristal
2023 J jnl
Vitruvius+: An Area-Efficient RISC-V Decoupled Vector Coprocessor for High Performance Computing Applications.
ACM Trans. Archit. Code Optim.
Francesco Minervini, Oscar Palomar, Osman S. Unsal, Enrico Reggiani, Josue V. Quiroga, Joan Marimon, Carlos Rojas, Roger Figueras, Abraham Ruiz, Alberto González, Jonnatan Mendoza, Iván Vargas, César Hernández, Joan Cabre, Lina Khoirunisya, Mustapha Bouhali, Julian Pavon, Francesc Moll, Mauro Olivieri, Mario Kovac, Mate Kovac, Leon Dragic, Mateo Valero, Adrián Cristal
2022 — conf
DVINO: A RISC-V Vector Processor Implemented in 65nm Technology.
DCIS
Guillem Cabo, Gerard Candón, Xavier Carril, Max Doblas, Marc Domínguez, Alberto González, César Hernández, Víctor Jiménez, Vatistas Kostalampros, Rubén Langarita, Neiel Leyva, Guillem López-Paradís, Jonnatan Mendoza, Francesco Minervini, Julián Pavón, Cristóbal Ramírez, Narcís Rodas, Enrico Reggiani, Mario Rodríguez, Carlos Rojas, Abraham Ruiz, Víctor Soria, Alejandro Suanes, Iván Vargas, Roger Figueras, Pau Fontova, Joan Marimon, Víctor Montabes, Adrián Cristal, Carles Hernández, Ricardo Martínez, Miquel Moretó, Francesc Moll, Oscar Palomar, Marco A. Ramírez, Antonio Rubio, Jordi Sacristán, Francisco Serra-Graells, Nehir Sönmez, Lluís Terés, Osman S. Unsal, Mateo Valero, Luis Villa
2021 — conf
PrioRAT: Criticality-Driven Prioritization Inside the On-Chip Memory Hierarchy.
Euro-Par
Vladimir Dimic, Miquel Moretó, Marc Casas, Mateo Valero
2021 — conf
The Ultimate DataFlow for Ultimate SuperComputers-on-a-Chip, for Scientific Computing, Geo Physics, Complex Mathematics, and Information Processing.
MECO
Veljko M. Milutinovic, Erfan Sadeqi Azer, Kristy Yoshimoto, Gerhard Klimeck, Miljan Djordjevic, Milos Kotlar, Miroslav Bojovic, Bozidar Miladinovic, Nenad Korolija, Stevan Stankovic, Nenad Filipovic, Zoran Babovic, Miroslav Kosanic, Akira Tsuda, Mateo Valero, Massimo De Santo, Erich J. Neuhold, Jelena Skorucak, Laura Dipietro, Ivan Ratkovic
2021 A* conf
VIA: A Smart Scratchpad for Vector Units with Application to Sparse Matrix Computations.
HPCA
Julian Pavon, Iván Vargas Valdivieso, Adrián Barredo, Joan Marimon, Miquel Moretó, Francesc Moll, Osman S. Unsal, Mateo Valero, Adrián Cristal
2021 J jnl
When Sally Met Harry or When AI Met HPC.
Supercomput. Front. Innov.
Ulises Cortés, Eduardo Ulises Moya-Sánchez, Mateo Valero
2020 J jnl
Advances in the Hierarchical Emergent Behaviors (HEB) Approach to Autonomous Vehicles.
IEEE Intell. Transp. Syst. Mag.
Damian Roca, Rodolfo A. Milito, Mario Nemirovsky, Mateo Valero
2020 — conf
An Academic RISC-V Silicon Implementation Based on Open-Source Components.
DCIS
Jaume Abella, Calvin Bulla, Guillem Cabo, Francisco J. Cazorla, Adrián Cristal, Max Doblas, Roger Figueras, Alberto González, Carles Hernández, César Hernández, Víctor Jiménez, Leonidas Kosmidis, Vatistas Kostalabros, Rubén Langarita, Neiel Leyva, Guillem López-Paradís, Joan Marimon, Ricardo Martínez, Jonnatan Mendoza, Francesc Moll, Miquel Moretó, Julián Pavón, Cristóbal Ramírez, Marco Antonio Ramírez, Carlos Rojas Morales, Antonio Rubio, Abraham Ruiz, Nehir Sönmez, Víctor Soria, Lluís Terés, Osman S. Unsal, Mateo Valero, Iván Vargas Valdivieso, Luis Villa
2020 J jnl
Efficiency analysis of modern vector architectures: vector ALU sizes, core counts and clock frequencies.
J. Supercomput.
Adrián Barredo, Juan M. Cebrian, Mateo Valero, Marc Casas, Miquel Moretó
2020 — conf
Improving Accuracy and Speeding Up Document Image Classification Through Parallel Systems.
ICCS (2)
Javier Ferrando, Juan Luis Domínguez, Jordi Torres, Raúl García, David García, Daniel Garrido, Jordi Cortada, Mateo Valero
2020 A* conf
Improving Predication Efficiency through Compaction/Restoration of SIMD Instructions.
HPCA
Adrián Barredo, Juan M. Cebrian, Miquel Moretó, Marc Casas, Mateo Valero
2020 J jnl
Improving accuracy and speeding up Document Image Classification through parallel systems.
CoRR
Javier Ferrando, Juan Luis Domínguez, Jordi Torres, Raúl García, David García, Daniel Garrido, Jordi Cortada, Mateo Valero
2020 A conf
RICH: implementing reductions in the cache hierarchy.
ICS
Vladimir Dimic, Miquel Moretó, Marc Casas, Jan Ciesko, Mateo Valero
2020 A conf
Runtime-guided ECC protection using online estimation of memory vulnerability.
SC
Luc Jaulmes, Miquel Moretó, Mateo Valero, Mattan Erez, Marc Casas
2020 J jnl
Semi-automatic validation of cycle-accurate simulation infrastructures: The case for gem5-x86.
Future Gener. Comput. Syst.
Juan M. Cebrian, Adrián Barredo, Helena Caminal, Miquel Moretó, Marc Casas, Mateo Valero
2020 J jnl
The Ultimate DataFlow for Ultimate SuperComputers-on-a-Chips.
CoRR
Veljko Milutinovic, Milos Kotlar, Ivan Ratkovic, Nenad Korolija, Miljan Djordjevic, Kristy Yoshimoto, Erik Klem, Mateo Valero
2020 J jnl
Using Arm's scalable vector extension on stencil codes.
J. Supercomput.
Adrià Armejach, Helena Caminal, Juan M. Cebrian, Rubén Langarita, Rekai González-Alberquilla, Chris Adeniyi-Jones, Mateo Valero, Marc Casas, Miquel Moretó
2019 J jnl
A Hardware Runtime for Task-Based Programming Models.
IEEE Trans. Parallel Distributed Syst.
Xubin Tan, Jaume Bosch, Carlos Álvarez, Daniel Jiménez-González, Eduard Ayguadé, Mateo Valero
2019 C conf
A Vulnerability Factor for ECC-protected Memory.
IOLTS
Luc Jaulmes, Miquel Moretó, Mateo Valero, Marc Casas
2019 J jnl
Guest Editorial: Special Issue on Network and Parallel Computing for Emerging Architectures and Applications.
Int. J. Parallel Program.
Feng Zhang, Jidong Zhai, Marc Snir, Hai Jin, Hironori Kasahara, Mateo Valero
2019 J jnl
On the maturity of parallel applications for asymmetric multi-core processors.
J. Parallel Distributed Comput.
Kallia Chronaki, Miquel Moretó, Marc Casas, Alejandro Rico, Rosa M. Badia, Eduard Ayguadé, Mateo Valero
2019 A conf
Optimizing computation-communication overlap in asynchronous task-based programs.
ICS
Emilio Castillo, Nikhil Jain, Marc Casas, Miquel Moretó, Martin Schulz, Ramón Beivide, Mateo Valero, Abhinav Bhatele
2019 B conf
Optimizing computation-communication overlap in asynchronous task-based programs: poster.
PPoPP
Emilio Castillo, Nikhil Jain, Marc Casas, Miquel Moretó, Martin Schulz, Ramón Beivide, Mateo Valero, Abhinav Bhatele
2019 B conf
POSTER: An Optimized Predication Execution for SIMD Extensions.
PACT
Adrián Barredo, Juan M. Cebrian, Miquel Moretó, Marc Casas, Mateo Valero
2019 A conf
Power efficient job scheduling by predicting the impact of processor manufacturing variability.
ICS
Dimitrios Chasapis, Miquel Moretó, Martin Schulz, Barry Rountree, Mateo Valero, Marc Casas
2019 J jnl
The international race towards Exascale in Europe.
CCF Trans. High Perform. Comput.
Fabrizio Gagliardi, Miquel Moretó, Mauro Olivieri, Mateo Valero
2018 J jnl
A General Guide to Applying Machine Learning to Computer Architecture.
Supercomput. Front. Innov.
Daniel Nemirovsky, Tugberk Arkose, Nikola Markovic, Mario Nemirovsky, Osman S. Unsal, Adrián Cristal, Mateo Valero
2018 A* conf
Architectural Support for Task Dependence Management with Flexible Software Scheduling.
HPCA
Emilio Castillo, Lluc Alvarez, Miquel Moretó, Marc Casas, Enrique Vallejo, José Luis Bosque, Ramón Beivide, Mateo Valero
2018 J jnl
Asynchronous and Exact Forward Recovery for Detected Errors in Iterative Solvers.
IEEE Trans. Parallel Distributed Syst.
Luc Jaulmes, Miquel Moretó, Eduard Ayguadé, Jesús Labarta, Mateo Valero, Marc Casas
2018 B conf
Graph partitioning applied to DAG scheduling to reduce NUMA effects.
PPoPP
Isaac Sánchez Barrera, Marc Casas, Miquel Moretó, Eduard Ayguadé, Jesús Labarta, Mateo Valero
2018 J jnl
Memory Vulnerability: A Case for Delaying Error Reporting.
CoRR
Luc Jaulmes, Miquel Moretó, Mateo Valero, Marc Casas
2018 C ed.
Network and Parallel Computing - 15th IFIP WG 10.3 International Conference, NPC 2018, Muroran, Japan, November 29 - December 1, 2018, Proceedings
NPC
Feng Zhang, Jidong Zhai, Marc Snir, Hai Jin, Hironori Kasahara, Mateo Valero
2018 J jnl
Performance and energy effects on task-based parallelized applications - User-directed versus manual vectorization.
J. Supercomput.
Helena Caminal, Diego Caballero, Juan M. Cebrian, Roger Ferrer, Marc Casas, Miquel Moretó, Xavier Martorell, Mateo Valero
2018 J jnl
Reducing Cache Coherence Traffic with a NUMA-Aware Runtime Approach.
IEEE Trans. Parallel Distributed Syst.
Paul Caheny, Lluc Alvarez, Said Derradji, Mateo Valero, Miquel Moretó, Marc Casas
2018 A conf
Reducing Data Movement on Large Shared Memory Systems by Exploiting Computation Dependencies.
ICS
Isaac Sánchez Barrera, Miquel Moretó, Eduard Ayguadé, Jesús Labarta, Mateo Valero, Marc Casas
2018 A conf
Runtime-Guided Management of Stacked DRAM Memories in Task Parallel Programs.
ICS
Lluc Alvarez, Marc Casas, Jesús Labarta, Eduard Ayguadé, Mateo Valero, Miquel Moretó
2018 A conf
Runtime-assisted cache coherence deactivation in task parallel programs.
SC
Paul Caheny, Lluc Alvarez, Mateo Valero, Miquel Moretó, Marc Casas
2018 B conf
Stencil codes on a vector length agnostic architecture.
PACT
Adrià Armejach, Helena Caminal, Juan M. Cebrian, Rekai González-Alberquilla, Chris Adeniyi-Jones, Mateo Valero, Marc Casas, Miquel Moretó
2018 J jnl
Vector Processing-Aware Advanced Clock-Gating Techniques for Low-Power Fused Multiply-Add.
IEEE Trans. Very Large Scale Integr. Syst.
Ivan Ratkovic, Oscar Palomar, Milan Stanic, Osman Sabri Unsal, Adrián Cristal, Mateo Valero
2017 — conf
A Deep Learning Mapper (DLM) for Scheduling on Heterogeneous Systems.
CARLA
Daniel Nemirovsky, Tugberk Arkose, Nikola Markovic, Mario Nemirovsky, Osman S. Unsal, Adrián Cristal, Mateo Valero
2017 J jnl
A scalable synthetic traffic model of Graph500 for computer networks analysis.
Concurr. Comput. Pract. Exp.
Pablo Fuentes, Mariano Benito, Enrique Vallejo, José Luis Bosque, Ramón Beivide, Andreea Anghel, Germán Rodríguez, Mitch Gusat, Cyriel Minkenberg, Mateo Valero
2017 A conf
ATM: Approximate Task Memoization in the Runtime System.
IPDPS
Iulian Brumar, Marc Casas, Miquel Moretó, Mateo Valero, Gurindar S. Sohi
2017 J jnl
An Integrated Vector-Scalar Design on an In-Order ARM Core.
ACM Trans. Archit. Code Optim.
Milan Stanic, Oscar Palomar, Timothy Hayes, Ivan Ratkovic, Adrián Cristal, Osman S. Unsal, Mateo Valero
2017 J jnl
Determinism at Standard-Library Level in TM-Based Applications.
Int. J. Parallel Program.
Vesna Smiljkovic, Osman S. Ünsal, Adrián Cristal, Mateo Valero
2017 A conf
Direct Inter-Process Communication (dIPC): Repurposing the CODOMs Architecture to Accelerate IPC.
EuroSys
Lluís Vilanova, Marc Jordà, Nacho Navarro, Yoav Etsion, Mateo Valero
2017 A conf
FlexVC: Flexible Virtual Channel Management in Low-Diameter Networks.
IPDPS
Pablo Fuentes, Enrique Vallejo, Ramón Beivide, Cyriel Minkenberg, Mateo Valero
2017 — conf
Fog Function Virtualization: A flexible solution for IoT applications.
FMEC
Damian Roca, Josue V. Quiroga, Mateo Valero, Mario Nemirovsky
2017 A conf
General Purpose Task-Dependence Management Hardware for Task-Based Dataflow Programming Models.
IPDPS
Xubin Tan, Jaume Bosch, Miquel Vidal, Carlos Álvarez, Daniel Jiménez-González, Eduard Ayguadé, Mateo Valero
2017 — conf
Picos, A Hardware Task-Dependence Manager for Task-Based Dataflow Programming Models.
HPCS
Xubin Tan, Jaume Bosch, Miquel Vidal, Carlos Álvarez, Daniel Jiménez-González, Eduard Ayguadé, Mateo Valero
2017 — conf
Runtime Aware Architectures.
Conf. Computing Frontiers
Mateo Valero
2017 A conf
Runtime Aware Architectures.
IPDPS
Mateo Valero
2017 — conf
Runtime-Assisted Shared Cache Insertion Policies Based on Re-reference Intervals.
Euro-Par
Vladimir Dimic, Miquel Moretó, Marc Casas, Mateo Valero
2017 C conf
SEDEA: A Sensible Approach to Account DRAM Energy in Multicore Systems.
SBAC-PAD
Qixiao Liu, Miquel Moretó, Jaume Abella, Francisco J. Cazorla, Mateo Valero
2017 J jnl
Task Scheduling Techniques for Asymmetric Multi-Core Systems.
IEEE Trans. Parallel Distributed Syst.
Kallia Chronaki, Alejandro Rico, Marc Casas, Miquel Moretó, Rosa M. Badia, Eduard Ayguadé, Jesús Labarta, Mateo Valero
2017 — conf
To Distribute or Not to Distribute: The Question of Load Balancing for Performance or Energy.
Euro-Par
Esteban Stafford, Borja Pérez, José Luis Bosque, Ramón Beivide, Mateo Valero
2017 B conf
iQ: An Efficient and Flexible Queue-Based Simulation Framework.
MASCOTS
Damian Roca, Daniel Nemirovsky, Marc Casas, Miquel Moretó, Mateo Valero, Mario Nemirovsky
2016 A conf
A Fully Parameterizable Low Power Design of Vector Fused Multiply-Add Using Active Clock-Gating Techniques.
ISLPED
Ivan Ratkovic, Oscar Palomar, Milan Stanic, Osman S. Unsal, Adrián Cristal, Mateo Valero
2016 J jnl
Alya: Multiphysics engineering simulation toward exascale.
J. Comput. Sci.
Mariano Vázquez, Guillaume Houzeaux, Seid Koric, Antoni Artigues, Jazmin Aguado-Sierra, Ruth Aris, Daniel Mira, Hadrien Calmet, Fernando M. Cucchietti, Herbert Coppola-Owen, Ahmed Taha, Evan Dering Burness, José María Cela, Mateo Valero
2016 A conf
CATA: Criticality Aware Task Acceleration for Multicore Processors.
IPDPS
Emilio Castillo, Miquel Moretó, Marc Casas, Lluc Alvarez, Enrique Vallejo, Kallia Chronaki, Rosa M. Badia, José Luis Bosque, Ramón Beivide, Eduard Ayguadé, Jesús Labarta, Mateo Valero
2016 J jnl
DReAM: An Approach to Estimate per-Task DRAM Energy in Multicore Systems.
ACM Trans. Design Autom. Electr. Syst.
Qixiao Liu, Miquel Moretó, Jaume Abella, Francisco J. Cazorla, Mateo Valero
2016 J jnl
Emergent Behaviors in the Internet of Things: The Ultimate Ultra-Large-Scale System.
IEEE Micro
Damian Roca, Daniel Nemirovsky, Mario Nemirovsky, Rodolfo A. Milito, Mateo Valero
2016 A* conf
Future Vector Microprocessor Extensions for Data Aggregations.
ISCA
Timothy Hayes, Oscar Palomar, Osman S. Unsal, Adrián Cristal, Mateo Valero
2016 J jnl
Interconnection Networks in Petascale Computer Systems: A Survey.
ACM Comput. Surv.
Roman Trobec, Radivoje Vasiljevic, Milo Tomasevic, Veljko Milutinovic, Ramón Beivide, Mateo Valero
2016 A conf
MUSA: a multi-level simulation approach for next-generation HPC machines.
SC
Thomas Grass, César Allande, Adrià Armejach, Alejandro Rico, Eduard Ayguadé, Jesús Labarta, Mateo Valero, Marc Casas, Miquel Moretó
2016 J jnl
Network unfairness in dragonfly topologies.
J. Supercomput.
Pablo Fuentes, Enrique Vallejo, Cristobal Camarero, Ramón Beivide, Mateo Valero
2016 J jnl
PARSECSs: Evaluating the Impact of Task Parallelism in the PARSEC Benchmark Suite.
ACM Trans. Archit. Code Optim.
Dimitrios Chasapis, Marc Casas, Miquel Moretó, Raul Vidal, Eduard Ayguadé, Jesús Labarta, Mateo Valero
2016 B conf
POSTER: An Integrated Vector-Scalar Design on an In-order ARM Core.
PACT
Milan Stanic, Oscar Palomar, Timothy Hayes, Ivan Ratkovic, Osman S. Unsal, Adrián Cristal, Mateo Valero
2016 B conf
POSTER: Exploiting Asymmetric Multi-Core Processors with Flexible System Sofware.
PACT
Kallia Chronaki, Miquel Moretó, Marc Casas, Alejandro Rico, Rosa M. Badia, Eduard Ayguadé, Jesús Labarta, Mateo Valero
2016 B conf
Performance analysis of a hardware accelerator of dependence management for task-based dataflow programming models.
ISPASS
Xubin Tan, Jaume Bosch, Daniel Jiménez-González, Carlos Álvarez-Martínez, Eduard Ayguadé, Mateo Valero
2016 B conf
Reducing Cache Coherence Traffic with Hierarchical Directory Cache and NUMA-Aware Runtime Scheduling.
PACT
Paul Caheny, Marc Casas, Miquel Moretó, Hervé Gloaguen, Maxime Saintes, Eduard Ayguadé, Jesús Labarta, Mateo Valero
2016 — conf
Runtime Aware Architectures.
DCNET
Mateo Valero
2016 — conf
Runtime Aware Architectures.
PECCS
Mateo Valero
2016 — conf
Runtime aware architectures.
GPGPU@PPoPP
Mateo Valero
2016 A conf
Runtime-Guided Mitigation of Manufacturing Variability in Power-Constrained Multi-Socket NUMA Nodes.
ICS
Dimitrios Chasapis, Marc Casas, Miquel Moretó, Martin Schulz, Eduard Ayguadé, Jesús Labarta, Mateo Valero
2016 J jnl
Sensible Energy Accounting with Abstract Metering for Multicore Systems.
ACM Trans. Archit. Code Optim.
Qixiao Liu, Miquel Moretó, Jaume Abella, Francisco J. Cazorla, Daniel A. Jiménez, Mateo Valero
2016 A conf
The mont-blanc prototype: an alternative approach for HPC systems.
SC
Nikola Rajovic, Alejandro Rico, Filippo Mantovani, Daniel Ruiz, Josep Oriol Vilarrubi, Constantino Gómez, Luna Backes, Diego Nieto, Harald Servat, Xavier Martorell, Jesús Labarta, Eduard Ayguadé, Chris Adeniyi-Jones, Said Derradji, Hervé Gloaguen, Piero Lanucara, Nico Sanna, Jean-François Méhaut, Kevin Pouget, Brice Videau, Eric Boyer, Momme Allalen, Axel Auweter, David Brayford, Daniele Tafani, Volker Weinberg, Dirk Brömmel, René Halver, Jan H. Meinke, Ramón Beivide, Mariano Benito, Enrique Vallejo, Mateo Valero, Alex Ramírez
2016 J jnl
Thread Assignment in Multicore/Multithreaded Processors: A Statistical Approach.
IEEE Trans. Computers
Petar Radojkovic, Paul M. Carpenter, Miquel Moretó, Vladimir Cakarevic, Javier Verdú, Alex Pajuelo, Francisco J. Cazorla, Mario Nemirovsky, Mateo Valero
2015 J jnl
Adaptive and application dependent runtime guided hardware prefetcher reconfiguration on the IBM POWER7.
CoRR
David Prat, Cristobal Ortega, Marc Casas, Miquel Moretó, Mateo Valero
2015 A* conf
Coherence protocol for transparent management of scratchpad memories in shared memory manycore architectures.
ISCA
Lluc Alvarez, Lluís Vilanova, Miquel Moretó, Marc Casas, Marc González, Xavier Martorell, Nacho Navarro, Eduard Ayguadé, Mateo Valero
2015 A conf
Contention-Based Nonminimal Adaptive Routing in High-Radix Networks.
IPDPS
Pablo Fuentes, Enrique Vallejo, Marina García, Ramón Beivide, Germán Rodríguez, Cyriel Minkenberg, Mateo Valero
2015 A conf
Criticality-Aware Dynamic Task Scheduling for Heterogeneous Architectures.
ICS
Kallia Chronaki, Alejandro Rico, Rosa M. Badia, Eduard Ayguadé, Jesús Labarta, Mateo Valero
2015 — conf
Evaluating the Impact of OpenMP 4.0 Extensions on Relevant Parallel Workloads.
IWOMP
Raul Vidal, Marc Casas, Miquel Moretó, Dimitrios Chasapis, Roger Ferrer, Xavier Martorell, Eduard Ayguadé, Jesús Labarta, Mateo Valero
2015 A conf
Exploiting asynchrony from exact forward recovery for DUE in iterative solvers.
SC
Luc Jaulmes, Marc Casas, Miquel Moretó, Eduard Ayguadé, Jesús Labarta, Mateo Valero
2015 — conf
Hardware Round-Robin Scheduler for Single-ISA Asymmetric Multi-core.
Euro-Par
Nikola Markovic, Daniel Nemirovsky, Veljko Milutinovic, Osman S. Unsal, Mateo Valero, Adrián Cristal
2015 — conf
Imposing coarse-grained reconfiguration to general purpose processors.
SAMOS
Milovan Duric, Milan Stanic, Ivan Ratkovic, Oscar Palomar, Osman S. Unsal, Adrián Cristal, Mateo Valero, Aaron Smith
2015 A* conf
Increasing multicore system efficiency through intelligent bandwidth shifting.
HPCA
Víctor Jiménez, Alper Buyuktosunoglu, Pradip Bose, Francis P. O'Connell, Francisco J. Cazorla, Mateo Valero
2015 — conf
Joint Circuit-System Design Space Exploration of Multiplier Unit Structure for Energy-Efficient Vector Processors.
ISVLSI
Ivan Ratkovic, Oscar Palomar, Milan Stanic, Milovan Duric, Djordje Peic, Osman S. Unsal, Adrián Cristal, Mateo Valero
2015 J jnl
Kernel-to-User-Mode Transition-Aware Hardware Scheduling.
IEEE Micro
Nikola Markovic, Daniel Nemirovsky, Osman S. Unsal, Mateo Valero, Adrián Cristal
2015 J jnl
New Benchmarking Methodology and Programming Model for Big Data Processing.
Int. J. Distributed Sens. Networks
Anton Kos, Saso Tomazic, Jakob Salom, Nemanja Trifunovic, Mateo Valero, Veljko Milutinovic
2015 J jnl
On-the-fly adaptive routing for dragonfly interconnection networks.
J. Supercomput.
Marina García, Enrique Vallejo, Ramón Beivide, Cristobal Camarero, Mateo Valero, Germán Rodríguez, Cyriel Minkenberg
2015 C conf
Performance and Energy Efficient Hardware-Based Scheduler for Symmetric/Asymmetric CMPs.
SBAC-PAD
Nikola Markovic, Daniel Nemirovsky, Osman S. Unsal, Mateo Valero, Adrián Cristal
2015 J jnl
Picos: A hardware runtime architecture support for OmpSs.
Future Gener. Comput. Syst.
Fahimeh Yazdanpanah, Carlos Álvarez, Daniel Jiménez-González, Rosa M. Badia, Mateo Valero
2015 J jnl
Reimagining Heterogeneous Computing: A Functional Instruction-Set Architecture Computing Model.
IEEE Micro
Daniel Nemirovsky, Nikola Markovic, Osman S. Unsal, Mateo Valero, Adrián Cristal
2015 — conf
Runtime-Aware Architectures.
Euro-Par
Marc Casas, Miquel Moretó, Lluc Alvarez, Emilio Castillo, Dimitrios Chasapis, Timothy Hayes, Luc Jaulmes, Oscar Palomar, Osman S. Unsal, Adrián Cristal, Eduard Ayguadé, Jesús Labarta, Mateo Valero
2015 B conf
Runtime-Guided Management of Scratchpad Memories in Multicore Architectures.
PACT
Lluc Alvarez, Miquel Moretó, Marc Casas, Emilio Castillo, Xavier Martorell, Jesús Labarta, Eduard Ayguadé, Mateo Valero
2015 — conf
Spark deployment and performance evaluation on the MareNostrum supercomputer.
IEEE BigData
Rubén Tous, Anastasios Gounaris, Carlos Tripiana, Jordi Torres, Sergi Girona, Eduard Ayguadé, Jesús Labarta, Yolanda Becerra, David Carrera, Mateo Valero
2015 J jnl
Thread Lock Section-Aware Scheduling on Asymmetric Single-ISA Multi-Core.
IEEE Comput. Archit. Lett.
Nikola Markovic, Daniel Nemirovsky, Osman S. Ünsal, Mateo Valero, Adrián Cristal
2015 C conf
Throughput Unfairness in Dragonfly Networks under Realistic Traffic Patterns.
CLUSTER
Pablo Fuentes, Enrique Vallejo, Cristobal Camarero, Ramón Beivide, Mateo Valero
2015 A* conf
VSR sort: A novel vectorised sorting algorithm & architecture extensions for future microprocessors.
HPCA
Timothy Hayes, Oscar Palomar, Osman S. Unsal, Adrián Cristal, Mateo Valero
2014 — conf
AMMC: Advanced Multi-Core Memory Controller.
FPT
Tassadaq Hussain, Oscar Palomar, Osman S. Unsal, Adrián Cristal, Eduard Ayguadé, Mateo Valero, Shakaib A. Gursal
2014 A conf
APMC: advanced pattern based memory controller (abstract only).
FPGA
Tassadaq Hussain, Oscar Palomar, Osman S. Unsal, Adrián Cristal, Eduard Ayguadé, Mateo Valero, Santhosh Kumar Rethinagiri
2014 — conf
Advanced Pattern based Memory Controller for FPGA based HPC applications.
HPCS
Tassadaq Hussain, Oscar Palomar, Osman S. Unsal, Adrián Cristal, Eduard Ayguadé, Mateo Valero
2014 J jnl
Analyzing the Efficiency of L1 Caches for Reliable Hybrid-Voltage Operation Using EDC Codes.
IEEE Trans. Very Large Scale Integr. Syst.
Bojan Maric, Jaume Abella, Mateo Valero
2014 — conf
Author retrospective for software trace cache.
ICS 25th Anniversary
Alex Ramírez, Ayose Falcón, Oliverio J. Santana, Mateo Valero
2014 C conf
Automatic Exploration of Potential Parallelism in Sequential Applications.
ISC
Vladimir Subotic, Eduard Ayguadé, Jesús Labarta, Mateo Valero
2014 — conf
Big Data Processing: Data Flow vs Control Flow (New Benchmarking Methodology).
IIKI
Anton Kos, Sao Tomac Jakob, Nemanja Trifunovic, Mateo Valero, Veljko Milutinovic
2014 A* conf
CODOMs: Protecting software with Code-centric memory Domains.
ISCA
Lluís Vilanova, Muli Ben-Yehuda, Nacho Navarro, Yoav Etsion, Mateo Valero
2014 — conf
Characterizing the Communication Demands of the Graph500 Benchmark on a Commodity Cluster.
BDC
Pablo Fuentes, José Luis Bosque, Ramón Beivide, Mateo Valero, Cyriel Minkenberg
2014 — conf
DReAM: Per-Task DRAM Energy Metering in Multicore Systems.
Euro-Par
Qixiao Liu, Miquel Moretó, Jaume Abella, Francisco J. Cazorla, Mateo Valero
2014 C conf
DeTrans: Deterministic and Parallel execution of Transactions.
SBAC-PAD
Vesna Smiljkovic, Srdan Stipic, Christof Fetzer, Osman S. Unsal, Adrián Cristal, Mateo Valero
2014 — conf
Dynamic transaction coalescing.
Conf. Computing Frontiers
Srdan Stipic, Vasileios Karakostas, Vesna Smiljkovic, Vladimir Gajinov, Osman S. Unsal, Adrián Cristal, Mateo Valero
2014 — conf
Dynamic-vector execution on a general purpose EDGE chip multiprocessor.
ICSAMOS
Milovan Duric, Oscar Palomar, Aaron Smith, Milan Stanic, Osman S. Unsal, Adrián Cristal, Mateo Valero, Doug Burger, Alexander V. Veidenbaum
2014 A conf
EVX: Vector execution on low power EDGE cores.
DATE
Milovan Duric, Oscar Palomar, Aaron Smith, Osman S. Unsal, Adrián Cristal, Mateo Valero, Doug Burger
2014 J jnl
Editorial.
Computación y Sistemas
Mateo Valero, Ulises Cortés
2014 A* conf
Enabling preemptive multiprogramming on GPUs.
ISCA
Ivan Tanasic, Isaac Gelado, Javier Cabezas, Alex Ramírez, Nacho Navarro, Mateo Valero
2014 — conf
Evaluation of vectorization potential of Graph500 on Intel's Xeon Phi.
HPCS
Milan Stanic, Oscar Palomar, Ivan Ratkovic, Milovan Duric, Osman S. Unsal, Adrián Cristal, Mateo Valero
2014 J jnl
Hybrid Cache Designs for Reliable Hybrid High and Ultra-Low Voltage Operation.
ACM Trans. Design Autom. Electr. Syst.
Bojan Maric, Jaume Abella, Francisco J. Cazorla, Mateo Valero
2014 B conf
MAPC: Memory access pattern based controller.
FPL
Tassadaq Hussain, Oscar Palomar, Osman S. Unsal, Adrián Cristal, Eduard Ayguadé, Mateo Valero
2014 — conf
PAMS: Pattern Aware Memory System for embedded systems.
ReConFig
Tassadaq Hussain, Nehir Sönmez, Oscar Palomar, Osman S. Unsal, Adrián Cristal, Eduard Ayguadé, Mateo Valero, Shakaib A. Gursal
2014 — conf
PVMC: Programmable Vector Memory Controller.
ASAP
Tassadaq Hussain, Oscar Palomar, Osman S. Unsal, Adrián Cristal, Eduard Ayguadé, Mateo Valero
2014 J jnl
Per-task Energy Accounting in Computing Systems.
IEEE Comput. Archit. Lett.
Qixiao Liu, Víctor Jiménez, Miquel Moretó, Jaume Abella, Francisco J. Cazorla, Mateo Valero
2014 — conf
Physical vs. Physically-Aware Estimation Flow: Case Study of Design Space Exploration of Adders.
ISVLSI
Ivan Ratkovic, Oscar Palomar, Milan Stanic, Osman S. Unsal, Adrián Cristal, Mateo Valero
2014 J jnl
Runtime-Aware Architectures: A First Approach.
Supercomput. Front. Innov.
Mateo Valero, Miquel Moretó, Marc Casas, Eduard Ayguadé, Jesús Labarta
2014 A conf
Scaling Irregular Applications through Data Aggregation and Software Multithreading.
IPDPS
Alessandro Morari, Antonino Tumeo, Daniel G. Chavarría-Miranda, Oreste Villa, Mateo Valero
2014 — conf
Stand-Alone Memory Controller for Graphics System.
ARC
Tassadaq Hussain, Oscar Palomar, Osman S. Ünsal, Adrián Cristal, Eduard Ayguadé, Mateo Valero, Amna Haider
2014 J jnl
TERAFLUX: Harnessing dataflow in next generation teradevices.
Microprocess. Microsystems
Roberto Giorgi, Rosa M. Badia, François Bodin, Albert Cohen, Paraskevas Evripidou, Paolo Faraboschi, Bernhard Fechner, Guang R. Gao, Arne Garbade, Rahulkumar Gayatri, Sylvain Girbal, Daniel Goodman, Behram Khan, Souad Koliai, Joshua Landwehr, Nhat Minh Lê, Feng Li, Mikel Luján, Avi Mendelson, Laurent Morin, Nacho Navarro, Tomasz Patejko, Antoniu Pop, Pedro Trancoso, Theo Ungerer, Ian Watson, Sebastian Weis, Stéphane Zuckerman, Mateo Valero
2014 J jnl
Using Dynamic Runtime Testing for Rapid Development of Architectural Simulators.
Int. J. Parallel Program.
Sasa Tomic, Adrián Cristal, Osman S. Unsal, Mateo Valero
2013 A* conf
APPLE: adaptive performance-predictable low-energy caches for reliable hybrid voltage operation.
DAC
Bojan Maric, Jaume Abella, Mateo Valero
2013 Misc conf
EcoTM: Conflict-Aware Economical Unbounded Hardware Transactional Memory.
ICCS
Sasa Tomic, Ege Akpinar, Adrián Cristal, Osman S. Unsal, Mateo Valero
2013 B conf
Efficient Routing Mechanisms for Dragonfly Networks.
ICPP
Marina García, Enrique Vallejo, Ramón Beivide, Miguel Odriozola, Mateo Valero
2013 A conf
Efficient cache architectures for reliable hybrid voltage operation using EDC codes.
DATE
Bojan Maric, Jaume Abella, Mateo Valero
2013 J jnl
Fair CPU time accounting in CMP+SMT processors.
ACM Trans. Archit. Code Optim.
Carlos Luque, Miquel Moretó, Francisco J. Cazorla, Mateo Valero
2013 — conf
Global misrouting policies in two-level hierarchical networks.
INA-OCMC@HiPEAC
Marina García, Enrique Vallejo, Ramón Beivide, Miguel Odriozola, Cristobal Camarero, Mateo Valero, Jesús Labarta, Germán Rodríguez
2013 — conf
HPC System Software for Regular and Irregular Parallel Applications.
IPDPS Workshops
Alessandro Morari, Mateo Valero
2013 — conf
HPCS 2013 panel: The era of exascale sciences: Challenges, needs and requirements.
HPCS
Franck Cappello, Wolfgang Gentzsch, Mateo Valero, Mads Nygård
2013 J jnl
Hardware support for accurate per-task energy metering in multicore systems.
ACM Trans. Archit. Code Optim.
Qixiao Liu, Miquel Moretó, Víctor Jiménez, Jaume Abella, Francisco J. Cazorla, Mateo Valero
2013 C conf
Identifying Critical Code Sections in Dataflow Programming Models.
PDP
Vladimir Subotic, José Carlos Sancho, Jesús Labarta, Mateo Valero
2013 — conf
Killer-mobiles - The Way Towards Energy Efficient High Performance Computers?
PECCS
Mateo Valero
2013 — conf
Killer-mobiles: The way towards energy efficient high performance computers?
ACSD
Mateo Valero
2013 J jnl
Moving from petaflops to petadata.
Commun. ACM
Michael J. Flynn, Oskar Mencer, Veljko M. Milutinovic, Goran Rakocevic, Per Stenström, Roman Trobec, Mateo Valero
2013 — conf
OFAR-CM: Efficient Dragonfly Networks with Simple Congestion Management.
Hot Interconnects
Marina García, Enrique Vallejo, Ramón Beivide, Mateo Valero, Germán Rodríguez
2013 — conf
On the selection of adder unit in energy efficient vector processing.
ISQED
Ivan Ratkovic, Oscar Palomar, Milan Stanic, Osman S. Unsal, Adrián Cristal, Mateo Valero
2013 J jnl
Profile-guided transaction coalescing - lowering transactional overheads by merging transactions.
ACM Trans. Archit. Code Optim.
Srdan Stipic, Vesna Smiljkovic, Osman S. Unsal, Adrián Cristal, Mateo Valero
2013 J jnl
Programmability and portability for exascale: Top down programming methodology and tools with StarSs.
J. Comput. Sci.
Vladimir Subotic, Steffen Brinkmann, Vladimir Marjanovic, Rosa M. Badia, José Gracia, Christoph Niethammer, Eduard Ayguadé, Jesús Labarta, Mateo Valero
2013 J jnl
SMT Malleability in IBM POWER5 and POWER6 Processors.
IEEE Trans. Computers
Alessandro Morari, Carlos Boneti, Francisco J. Cazorla, Roberto Gioiosa, Chen-Yong Cher, Alper Buyuktosunoglu, Pradip Bose, Mateo Valero
2013 A conf
Supercomputing with commodity CPUs: are mobile SoCs ready for HPC?
SC
Nikola Rajovic, Paul M. Carpenter, Isaac Gelado, Nikola Puzovic, Alex Ramírez, Mateo Valero
2013 A conf
TM-dietlibc: A TM-aware Real-World System Library.
IPDPS
Vesna Smiljkovic, Martin Nowack, Neboja Miletic, Tim Harris, Osman S. Ünsal, Adrián Cristal, Mateo Valero
2013 C conf
The TERAFLUX Project: Exploiting the DataFlow Paradigm in Next Generation Teradevices.
DSD
Marco Solinas, Rosa M. Badia, François Bodin, Albert Cohen, Paraskevas Evripidou, Paolo Faraboschi, Bernhard Fechner, Guang R. Gao, Arne Garbade, Sylvain Girbal, Daniel Goodman, Behram Khan, Souad Koliai, Feng Li, Mikel Luján, Laurent Morin, Avi Mendelson, Nacho Navarro, Antoniu Pop, Pedro Trancoso, Theo Ungerer, Mateo Valero, Sebastian Weis, Ian Watson, Stéphane Zuckerman, Roberto Giorgi
2013 J jnl
Thread Assignment of Multithreaded Network Applications in Multicore/Multithreaded Processors.
IEEE Trans. Parallel Distributed Syst.
Petar Radojkovic, Vladimir Cakarevic, Javier Verdú, Alex Pajuelo, Francisco J. Cazorla, Mario Nemirovsky, Mateo Valero
2013 B conf
Trace filtering of multithreaded applications for CMP memory simulation.
ISPASS
Alejandro Rico, Alex Ramírez, Mateo Valero
2012 — conf
ADAM: an efficient data management mechanism for hybrid high and ultra-low voltage operation caches.
ACM Great Lakes Symposium on VLSI
Bojan Maric, Jaume Abella, Mateo Valero
2012 J jnl
CPU Accounting for Multicore Processors.
IEEE Trans. Computers
Carlos Luque, Miquel Moretó, Francisco J. Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu, Mateo Valero
2012 J jnl
Circuit design of a dual-versioning L1 data cache.
Integr.
Azam Seyedi, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Ibrahim Hur, Mateo Valero
2012 J jnl
Dynamic Tolerance Region Computing for Multimedia.
IEEE Trans. Computers
Carlos Álvarez, Jesús Corbal, Mateo Valero
2012 C conf
Efficient Sorting on the Tilera Manycore Architecture.
SBAC-PAD
Alessandro Morari, Antonino Tumeo, Oreste Villa, Simone Secchi, Mateo Valero
2012 A conf
Enhancing the performance of assisted execution runtime systems through hardware/software techniques.
ICS
Gokcen Kestor, Roberto Gioiosa, Osman S. Unsal, Adrián Cristal, Mateo Valero
2012 A conf
Evaluating the Impact of TLB Misses on Future HPC Systems.
IPDPS
Alessandro Morari, Roberto Gioiosa, Robert W. Wisniewski, Bryan S. Rosenburg, Todd Inglett, Mateo Valero
2012 J jnl
Hardware transactional memory with software-defined conflicts.
ACM Trans. Archit. Code Optim.
J. Rubén Titos Gil, Manuel E. Acacio, José M. García, Tim Harris, Adrián Cristal, Osman S. Unsal, Ibrahim Hur, Mateo Valero
2012 A* conf
Improving Cache Management Policies Using Dynamic Reuse Distances.
MICRO
Nam Duong, Dali Zhao, Taesu Kim, Rosario Cammarota, Mateo Valero, Alexander V. Veidenbaum
2012 — conf
Novel SRAM bias control circuits for a low power L1 data cache.
NORCHIP
Azam Seyedi, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Mateo Valero
2012 J jnl
On the simulation of large-scale architectures using multiple application abstraction levels.
ACM Trans. Archit. Code Optim.
Alejandro Rico, Felipe Cabarcas, Carlos Villavieja, Milan Pavlovic, Augusto Vega, Yoav Etsion, Alex Ramírez, Mateo Valero
2012 B conf
On-the-Fly Adaptive Routing in High-Radix Hierarchical Networks.
ICPP
Marina García, Enrique Vallejo, Ramón Beivide, Miguel Odriozola, Cristobal Camarero, Mateo Valero, Germán Rodríguez, Jesús Labarta, Cyriel Minkenberg
2012 A* conf
Optimal task assignment in multithreaded processors: a statistical approach.
ASPLOS
Petar Radojkovic, Vladimir Cakarevic, Miquel Moretó, Javier Verdú, Alex Pajuelo, Francisco J. Cazorla, Mario Nemirovsky, Mateo Valero
2012 J jnl
Parallel job scheduling for power constrained HPC systems.
Parallel Comput.
Maja Etinski, Julita Corbalán, Jesús Labarta, Mateo Valero
2012 J jnl
Profiling and Optimizing Transactional Memory Applications.
Int. J. Parallel Program.
Ferad Zyulkyarov, Srdjan Stipic, Tim Harris, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Mateo Valero
2012 J jnl
Resource-bounded multicore emulation using Beefarm.
Microprocess. Microsystems
Oriol Arcas, Nehir Sönmez, Gokhan Sayilar, Satnam Singh, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Mateo Valero
2012 A conf
TagTM - accelerating STMs with hardware tags for fast meta-data access.
DATE
Srdjan Stipic, Sasa Tomic, Ferad Zyulkyarov, Adrián Cristal, Osman S. Ünsal, Mateo Valero
2012 C conf
The Network Adapter: The Missing Link between MPI Applications and Network Performance.
SBAC-PAD
Germán Rodríguez, Cyriel Minkenberg, Ronald P. Luijten, Ramón Beivide, Patrick Geoffray, Jesús Labarta, Mateo Valero, Steve Poole
2012 J jnl
The Problem of Evaluating CPU-GPU Systems with 3D Visualization Applications.
IEEE Micro
Javier Verdú, Alex Pajuelo, Mateo Valero
2012 J jnl
Understanding the future of energy-performance trade-off via DVFS in HPC environments.
J. Parallel Distributed Comput.
Maja Etinski, Julita Corbalán, Jesús Labarta, Mateo Valero
2012 A* conf
Vector Extensions for Decision Support DBMS Acceleration.
MICRO
Timothy Hayes, Oscar Palomar, Osman S. Unsal, Adrián Cristal, Mateo Valero
2011 J jnl
A Highly Scalable Parallel Implementation of H.264.
Trans. High Perform. Embed. Archit. Compil.
Arnaldo Azevedo, Ben H. H. Juurlink, Cor Meenderinck, Andrei Sergeevich Terechko, Jan Hoogerbrugge, Mauricio Alvarez, Alex Ramírez, Mateo Valero
2011 A conf
A Quantitative Analysis of OS Noise.
IPDPS
Alessandro Morari, Roberto Gioiosa, Robert W. Wisniewski, Francisco J. Cazorla, Mateo Valero
2011 B conf
An Abstraction Methodology for the Evaluation of Multi-core Multi-threaded Architectures.
MASCOTS
Ruken Zilan, Javier Verdú, Jorge García-Vidal, Mario Nemirovsky, Rodolfo A. Milito, Mateo Valero
2011 J jnl
Assessing Accelerator-Based HPC Reverse Time Migration.
IEEE Trans. Parallel Distributed Syst.
Mauricio Araya-Polo, Javier Cabezas, Mauricio Hanzich, Miquel Pericàs, Félix Rubio, Isaac Gelado, Muhammad Shafiq, Enric Morancho, Nacho Navarro, Eduard Ayguadé, José María Cela, Mateo Valero
2011 — conf
Breaking the bandwidth wall in chip multiprocessors.
ICSAMOS
Augusto Vega, Felipe Cabarcas, Alex Ramírez, Mateo Valero
2011 J jnl
Characterizing Power and Temperature Behavior of POWER6-Based System.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Víctor Jiménez, Francisco J. Cazorla, Roberto Gioiosa, Mateo Valero, Carlos Boneti, Eren Kursun, Chen-Yong Cher, Canturk Isci, Alper Buyuktosunoglu, Pradip Bose
2011 — conf
Circuit design of a dual-versioning L1 data cache for optimistic concurrency.
ACM Great Lakes Symposium on VLSI
Azam Seyedi, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Ibrahim Hur, Mateo Valero
2011 J jnl
Dynamic Cache Partitioning Based on the MLP of Cache Misses.
Trans. High Perform. Embed. Archit. Compil.
Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero
2011 J jnl
Energy-Aware Accounting and Billing in Large-Scale Computing Facilities.
IEEE Micro
Víctor Jiménez, Francisco J. Cazorla, Roberto Gioiosa, Eren Kursun, Canturk Isci, Alper Buyuktosunoglu, Pradip Bose, Mateo Valero
2011 J jnl
Exploiting intra-task slack time of load operations for DVFS in hard real-time multi-core systems.
SIGBED Rev.
Eduardo Quiñones, Jaume Abella, Francisco J. Cazorla, Mateo Valero
2011 C conf
FIMSIM: A fault injection infrastructure for microarchitectural simulators.
ICCD
Gulay Yalcin, Osman S. Unsal, Adrián Cristal, Mateo Valero
2011 — conf
From Plasma to BeeFarm: Design Experience of an FPGA-Based Multicore Prototype.
ARC
Nehir Sönmez, Oriol Arcas, Gokhan Sayilar, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Satnam Singh, Mateo Valero
2011 — conf
Hybrid Parallel Programming with MPI/StarSs.
PARCO
Jesús Labarta, Vladimir Marjanovic, Eduard Ayguadé, Rosa M. Badia, Mateo Valero
2011 J jnl
Hybrid Transactional Memory with Pessimistic Concurrency Control.
Int. J. Parallel Program.
Enrique Vallejo, Sutirtha Sanyal, Tim Harris, Fernando Vallejo, Ramón Beivide, Osman S. Unsal, Adrián Cristal, Mateo Valero
2011 — conf
Hybrid high-performance low-power and ultra-low energy reliable caches.
Conf. Computing Frontiers
Bojan Maric, Jaume Abella, Francisco J. Cazorla, Mateo Valero
2011 A conf
IA^3: An Interference Aware Allocation Algorithm for Multicore Hard Real-Time Systems.
IEEE Real-Time and Embedded Technology and Applications Symposium
Marco Paolieri, Eduardo Quiñones, Francisco J. Cazorla, Robert I. Davis, Mateo Valero
2011 — conf
Linear programming based parallel job scheduling for power constrained systems.
HPCS
Maja Etinski, Julita Corbalán, Jesús Labarta, Mateo Valero
2011 — conf
Quantifying the Potential Task-Based Dataflow Parallelism in MPI Applications.
Euro-Par (1)
Vladimir Subotic, Roger Ferrer, José Carlos Sancho, Jesús Labarta, Mateo Valero
2011 J jnl
RMS-TM: a comprehensive benchmark suite for transactional memory systems (abstracts only).
SIGMETRICS Perform. Evaluation Rev.
Gokcen Kestor, Vasileios Karakostas, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Mateo Valero
2011 B conf
RMS-TM: a comprehensive benchmark suite for transactional memory systems.
ICPE
Gokcen Kestor, Vasileios Karakostas, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Mateo Valero
2011 C conf
RVC-based time-predictable faulty caches for safety-critical systems.
IOLTS
Jaume Abella, Eduardo Quiñones, Francisco J. Cazorla, Mateo Valero, Yanos Sazeides
2011 — conf
RVC: a mechanism for time-analyzable real-time processors with faulty caches.
HiPEAC
Jaume Abella, Eduardo Quiñones, Francisco J. Cazorla, Yanos Sazeides, Mateo Valero
2011 C conf
Rapid Development of Error-Free Architectural Simulators Using Dynamic Runtime Testing.
SBAC-PAD
Sasa Tomic, Adrián Cristal, Osman S. Ünsal, Mateo Valero
2011 B conf
STM2: A Parallel STM for High Performance Simultaneous Multithreading Systems.
PACT
Gokcen Kestor, Roberto Gioiosa, Tim Harris, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Mateo Valero
2011 J jnl
Scalable multicore architectures for long DNA sequence comparison.
Concurr. Comput. Pract. Exp.
Friman Sánchez, Felipe Cabarcas, Alex Ramírez, Mateo Valero
2011 J jnl
Simulating Whole Supercomputer Applications.
IEEE Micro
Juan Gonzalez, Judit Giménez, Marc Casas, Miquel Moretó, Alex Ramírez, Jesús Labarta, Mateo Valero
2011 B conf
SymptomTM: Symptom-Based Error Detection and Recovery Using Hardware Transactional Memory.
PACT
Gulay Yalcin, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Mateo Valero
2011 Misc conf
TMbox: A Flexible and Reconfigurable 16-Core Hybrid Transactional Memory System.
FCCM
Nehir Sönmez, Oriol Arcas, Otto Pflucker, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Satnam Singh, Mateo Valero
2011 C conf
The Impact of Application's Micro-Imbalance on the Communication-Computation Overlap.
PDP
Vladimir Subotic, José Carlos Sancho, Jesús Labarta, Mateo Valero
2011 J jnl
The International Exascale Software Project roadmap.
Int. J. High Perform. Comput. Appl.
Jack J. Dongarra, Peter H. Beckman, Terry Moore, Patrick Aerts, Giovanni Aloisio, Jean-Claude Andre, David Barkai, Jean-Yves Berthou, Taisuke Boku, Bertrand Braunschweig, Franck Cappello, Barbara M. Chapman, Xuebin Chi, Alok N. Choudhary, Sudip S. Dosanjh, Thom H. Dunning, Sandro Fiore, Al Geist, Bill Gropp, Robert J. Harrison, Mark Hereld, Michael A. Heroux, Adolfy Hoisie, Koh Hotta, Zhong Jin, Yutaka Ishikawa, Fred Johnson, Sanjay Kale, Richard Kenway, David E. Keyes, Bill Kramer, Jesús Labarta, Alain Lichnewsky, Thomas Lippert, Bob Lucas, Barney Maccabe, Satoshi Matsuoka, Paul Messina, Peter Michielse, Bernd Mohr, Matthias S. Müller, Wolfgang E. Nagel, Hiroshi Nakashima, Michael E. Papka, Daniel A. Reed, Mitsuhisa Sato, Edward Seidel, John Shalf, David Skinner, Marc Snir, Thomas L. Sterling, Rick Stevens, Frederick H. Streitz, Bob Sugar, Shinji Sumimoto, William M. Tang, John A. Taylor, Rajeev Thakur, Anne E. Trefethen, Mateo Valero, Aad J. van der Steen, Jeffrey S. Vetter, Peg Williams, Robert W. Wisniewski, Katherine A. Yelick
2011 B conf
Trace-driven simulation of multithreaded applications.
ISPASS
Alejandro Rico, Alejandro Duran, Felipe Cabarcas, Yoav Etsion, Alex Ramírez, Mateo Valero
2011 B conf
Using a Reconfigurable L1 Data Cache for Efficient Version Management in Hardware Transactional Memory.
PACT
Adrià Armejach, Azam Seyedi, J. Rubén Titos Gil, Ibrahim Hur, Adrián Cristal, Osman S. Unsal, Mateo Valero
2010 C conf
A Simulation Framework to Automatically Analyze the Communication-Computation Overlap in Scientific Applications.
CLUSTER
Vladimir Subotic, José Carlos Sancho, Jesús Labarta, Mateo Valero
2010 A conf
Adapting cache partitioning algorithms to pseudo-LRU replacement policies.
IPDPS
Kamil Kedzierski, Miquel Moretó, Francisco J. Cazorla, Mateo Valero
2010 A* conf
Architectural Support for Fair Reader-Writer Locking.
MICRO
Enrique Vallejo, Ramón Beivide, Adrián Cristal, Tim Harris, Fernando Vallejo, Osman S. Unsal, Mateo Valero
2010 — conf
BSLD threshold driven power management policy for HPC centers.
IPDPS Workshops
Maja Etinski, Julita Corbalán, Jesús Labarta, Mateo Valero
2010 — conf
Comparing last-level cache designs for CMP architectures.
IFMT
Augusto Vega, Alejandro Rico, Felipe Cabarcas, Alex Ramírez, Mateo Valero
2010 B conf
Debugging programs that use atomic blocks and transactional memory.
PPoPP
Ferad Zyulkyarov, Tim Harris, Osman S. Unsal, Adrián Cristal, Mateo Valero
2010 C conf
Designing OS for HPC Applications: Scheduling.
CLUSTER
Roberto Gioiosa, Sally A. McKee, Mateo Valero
2010 B conf
Discovering and understanding performance bottlenecks in transactional applications.
PACT
Ferad Zyulkyarov, Srdjan Stipic, Tim Harris, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Mateo Valero
2010 B conf
Effective communication and computation overlap with hybrid MPI/SMPSs.
PPoPP
Vladimir Marjanovic, Jesús Labarta, Eduard Ayguadé, Mateo Valero
2010 B conf
Efficient runahead threads.
PACT
Tanausú Ramírez, Alex Pajuelo, Oliverio J. Santana, Onur Mutlu, Mateo Valero
2010 — conf
Exploiting Inactive Rename Slots for Detecting Soft Errors.
ARCS
Mehmet Kayaalp, Oguz Ergin, Osman S. Ünsal, Mateo Valero
2010 — conf
Load balancing using dynamic cache allocation.
Conf. Computing Frontiers
Miquel Moretó, Francisco J. Cazorla, Rizos Sakellariou, Mateo Valero
2010 — conf
Long DNA Sequence Comparison on Multicore Architectures.
Euro-Par (2)
Friman Sánchez, Felipe Cabarcas, Alex Ramírez, Mateo Valero
2010 J jnl
Multicore: The View from Europe.
IEEE Micro
Mateo Valero, Nacho Navarro
2010 J jnl
On the Problem of Evaluating the Performance of Multiprogrammed Workloads.
IEEE Trans. Computers
Francisco J. Cazorla, Alex Pajuelo, Oliverio J. Santana, Enrique Fernández, Mateo Valero
2010 — conf
Optimizing job performance under a given power constraint in HPC centers.
Green Computing Conference
Maja Etinski, Julita Corbalán, Jesús Labarta, Mateo Valero
2010 A conf
Overlapping communication and computation by using a hybrid MPI/SMPSs approach.
ICS
Vladimir Marjanovic, Jesús Labarta, Eduard Ayguadé, Mateo Valero
2010 — conf
Power and performance aware reconfigurable cache for CMPs.
IFMT
Kamil Kedzierski, Francisco J. Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu, Mateo Valero
2010 B conf
Power and thermal characterization of POWER6 system.
PACT
Víctor Jiménez, Francisco J. Cazorla, Roberto Gioiosa, Mateo Valero, Carlos Boneti, Eren Kursun, Chen-Yong Cher, Canturk Isci, Alper Buyuktosunoglu, Pradip Bose
2010 Misc conf
Scalability Analysis of Progressive Alignment on a Multicore.
CISIS
Sebastián Isaza, Friman Sánchez, Georgi Gaydadjiev, Alex Ramírez, Mateo Valero
2010 B conf
Simulation environment for studying overlap of communication and computation.
ISPASS
Vladimir Subotic, Jesús Labarta, Mateo Valero
2010 A* conf
Task Superscalar: An Out-of-Order Task Pipeline.
MICRO
Yoav Etsion, Felipe Cabarcas, Alejandro Rico, Alex Ramírez, Rosa M. Badia, Eduard Ayguadé, Jesús Labarta, Mateo Valero
2010 B conf
Thread to strand binding of parallel network applications in massive multi-threaded systems.
PPoPP
Petar Radojkovic, Vladimir Cakarevic, Javier Verdú, Alex Pajuelo, Francisco J. Cazorla, Mario Nemirovsky, Mateo Valero
2010 C conf
Trends and techniques for energy efficient architectures.
VLSI-SoC
Víctor Jiménez, Roberto Gioiosa, Eren Kursun, Francisco J. Cazorla, Chen-Yong Cher, Alper Buyuktosunoglu, Pradip Bose, Mateo Valero
2010 J jnl
Utilization driven power-aware parallel job scheduling.
Comput. Sci. Res. Dev.
Maja Etinski, Julita Corbalán, Jesús Labarta, Mateo Valero
2009 A conf
A european perspective on supercomputing.
ICS
Mateo Valero
2009 J jnl
An Analyzable Memory Controller for Hard Real-Time CMPs.
IEEE Embed. Syst. Lett.
Marco Paolieri, Eduardo Quiñones, Francisco J. Cazorla, Mateo Valero
2009 B conf
Atomic quake: using transactional memory in an interactive multiplayer game server.
PPoPP
Ferad Zyulkyarov, Vladimir Gajinov, Osman S. Unsal, Adrián Cristal, Eduard Ayguadé, Tim Harris, Mateo Valero
2009 J jnl
Available task-level parallelism on the Cell BE.
Sci. Program.
Alejandro Rico, Alex Ramírez, Mateo Valero
2009 J jnl
BSC Vision Towards Exascale.
Int. J. High Perform. Comput. Appl.
Jesús Labarta, Eduard Ayguadé, Mateo Valero
2009 J jnl
CPU Accounting in CMP Processors.
IEEE Comput. Archit. Lett.
Carlos Luque, Miquel Moretó, Francisco J. Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu, Mateo Valero
2009 A* conf
Characterizing the resource-sharing levels in the UltraSPARC T2 processor.
MICRO
Vladimir Cakarevic, Petar Radojkovic, Javier Verdú, Alex Pajuelo, Francisco J. Cazorla, Mario Nemirovsky, Mateo Valero
2009 A conf
Clock gate on abort: Towards energy-efficient hardware Transactional Memory.
IPDPS
Sutirtha Sanyal, Sourav Roy, Adrián Cristal, Osman S. Unsal, Mateo Valero
2009 B conf
Code Semantic-Aware Runahead Threads.
ICPP
Tanausú Ramírez, Alex Pajuelo, Oliverio J. Santana, Mateo Valero
2009 J jnl
DIA: A Complexity-Effective Decoding Architecture.
IEEE Trans. Computers
Oliverio J. Santana, Ayose Falcón, Alex Ramírez, Mateo Valero
2009 C conf
Dynamically Filtering Thread-Local Variables in Lazy-Lazy Hardware Transactional Memory.
HPCC
Sutirtha Sanyal, Sourav Roy, Adrián Cristal, Osman S. Unsal, Mateo Valero
2009 A* conf
EazyHTM: eager-lazy hardware transactional memory.
MICRO
Sasa Tomic, Cristian Perfumo, Chinmay Eishan Kulkarni, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Tim Harris, Mateo Valero
2009 J jnl
Evaluación del rendimiento paralelo en el nivel macro bloque del decodificador H.264 en una arquitectura multiprocesador cc-NUMA.
Rev. Avances en Sistemas Informática
Mauricio Alvarez, Alex Ramírez, Mateo Valero, Arnaldo Azevedo, Cor Meenderinck
2009 A conf
Exploring pattern-aware routing in generalized fat tree networks.
ICS
Germán Rodríguez, Ramón Beivide, Cyriel Minkenberg, Jesús Labarta, Mateo Valero
2009 J jnl
FlexDCP: a QoS framework for CMP architectures.
ACM SIGOPS Oper. Syst. Rev.
Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Rizos Sakellariou, Mateo Valero
2009 A* conf
Hardware support for WCET analysis of hard real-time multicore systems.
ISCA
Marco Paolieri, Eduardo Quiñones, Francisco J. Cazorla, Guillem Bernat, Mateo Valero
2009 B conf
ITCA: Inter-task Conflict-Aware CPU Accounting for CMPs.
PACT
Carlos Luque, Miquel Moretó, Francisco J. Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu, Mateo Valero
2009 C conf
Oblivious routing schemes in extended generalized Fat Tree networks.
CLUSTER
Germán Rodríguez, Cyriel Minkenberg, Ramón Beivide, Ronald P. Luijten, Jesús Labarta, Mateo Valero
2009 A conf
Power-aware load balancing of large scale MPI applications.
IPDPS
Maja Etinski, Julita Corbalán, Jesús Labarta, Mateo Valero, Alexander V. Veidenbaum
2009 A conf
QuakeTM: parallelizing a complex sequential application using transactional memory.
ICS
Vladimir Gajinov, Ferad Zyulkyarov, Osman S. Unsal, Adrián Cristal, Eduard Ayguadé, Tim Harris, Mateo Valero
2009 — conf
Quantitative analysis of sequence alignment applications on multiprocessor architectures.
Conf. Computing Frontiers
Friman Sánchez, Alex Ramírez, Mateo Valero
2009 B conf
Scalability of Macroblock-level Parallelism for H.264 Decoding.
ICPADS
Mauricio Alvarez-Mesa, Alex Ramírez, Arnaldo Azevedo, Cor Meenderinck, Ben H. H. Juurlink, Mateo Valero
2009 A conf
Taking the heat off transactions: Dynamic selection of pessimistic concurrency control.
IPDPS
Nehir Sönmez, Tim Harris, Adrián Cristal, Osman S. Unsal, Mateo Valero
2009 J jnl
The International Exascale Software Project: a Call To Cooperative Action By the Global High-Performance Community.
Int. J. High Perform. Comput. Appl.
Jack J. Dongarra, Peter H. Beckman, Patrick Aerts, Franck Cappello, Thomas Lippert, Satoshi Matsuoka, Paul Messina, Terry Moore, Rick Stevens, Anne E. Trefethen, Mateo Valero
2009 C conf
Thread to Core Assignment in SMT On-Chip Multiprocessors.
SBAC-PAD
Carmelo Acosta, Francisco J. Cazorla, Alex Ramírez, Mateo Valero
2009 B conf
Turbocharging boosted transactions or: how i learnt to stop worrying and love longer transactions.
PPoPP
Chinmay Eishan Kulkarni, Osman S. Unsal, Adrián Cristal, Eduard Ayguadé, Mateo Valero
2008 A* conf
A Two-Level Load/Store Queue Based on Execution Locality.
ISCA
Miquel Pericàs, Adrián Cristal, Francisco J. Cazorla, Rubén González, Alexander V. Veidenbaum, Daniel A. Jiménez, Mateo Valero
2008 A* conf
A distributed processor state management architecture for large-window processors.
MICRO
Isidro Gonzalez, Marco Galluzzi, Alexander V. Veidenbaum, Marco Antonio Ramírez, Adrián Cristal, Mateo Valero
2008 A conf
A dynamic scheduler for balancing HPC applications.
SC
Carlos Boneti, Roberto Gioiosa, Francisco J. Cazorla, Mateo Valero
2008 — conf
Architecture Performance Prediction Using Evolutionary Artificial Neural Networks.
EvoWorkshops
Pedro A. Castillo, Antonio Miguel Mora, Juan Julián Merelo Guervós, Juan Luis Jiménez Laredo, Miquel Moretó, Francisco J. Cazorla, Mateo Valero, Sally A. McKee
2008 A conf
Balancing HPC applications through smart allocation of resources in MT processors.
IPDPS
Carlos Boneti, Roberto Gioiosa, Francisco J. Cazorla, Julita Corbalán, Jesús Labarta, Mateo Valero
2008 B conf
Evolutionary system for prediction and optimization of hardware architecture performance.
IEEE Congress on Evolutionary Computation
Pedro Ángel Castillo Valdivieso, Juan Julián Merelo Guervós, Miquel Moretó, Francisco J. Cazorla, Mateo Valero, Antonio Miguel Mora, Juan Luis Jiménez Laredo, Sally A. McKee
2008 — conf
LPA: A First Approach to the Loop Processor Architecture.
HiPEAC
Alejandro García, Oliverio J. Santana, Enrique Fernández, Pedro Medina, Mateo Valero
2008 B conf
MFLUSH: Handling Long-Latency Loads in SMT On-Chip Multiprocessors.
ICPP
Carmelo Acosta, Francisco J. Cazorla, Alex Ramírez, Mateo Valero
2008 — conf
MLP-Aware Dynamic Cache Partitioning.
HiPEAC
Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero
2008 C conf
Measuring Operating System Overhead on CMT Processors.
SBAC-PAD
Petar Radojkovic, Vladimir Cakarevic, Javier Verdú, Alejandro Pajuelo, Roberto Gioiosa, Francisco J. Cazorla, Mario Nemirovsky, Mateo Valero
2008 — conf
MultiLayer processing - an execution model for parallel stateful packet processing.
ANCS
Javier Verdú, Mario Nemirovsky, Mateo Valero
2008 J jnl
Multicore Resource Management.
IEEE Micro
Kyle J. Nesbit, Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero, James E. Smith
2008 J jnl
Nebelung: Execution Environment for Transactional OpenMP.
Int. J. Parallel Program.
Milos Milovanovic, Roger Ferrer, Vladimir Gajinov, Osman S. Unsal, Adrián Cristal, Eduard Ayguadé, Mateo Valero
2008 J jnl
Power-efficient VLIW design using clustering and widening.
Int. J. Embed. Syst.
Miquel Pericàs, Eduard Ayguadé, Javier Zalamea, Josep Llosa, Mateo Valero
2008 — conf
Preliminary Analysis of the Cell BE Processor Limitations for Sequence Alignment Applications.
SAMOS
Sebastián Isaza, Friman Sánchez, Georgi Gaydadjiev, Alex Ramírez, Mateo Valero
2008 A* conf
Runahead Threads to improve SMT performance.
HPCA
Tanausú Ramírez, Alex Pajuelo, Oliverio J. Santana, Mateo Valero
2008 C conf
Selection of the Register File Size and the Resource Allocation Policy on SMT Processors.
SBAC-PAD
Jesús Alastruey, Teresa Monreal, Francisco J. Cazorla, Víctor Viñals, Mateo Valero
2008 — conf
Soft Real-Time Scheduling on SMT Processors with Explicit Resource Allocation.
ARCS
Carlos Boneti, Francisco J. Cazorla, Roberto Gioiosa, Mateo Valero
2008 A* conf
Software-Controlled Priority Characterization of POWER5 Processor.
ISCA
Carlos Boneti, Francisco J. Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu, Chen-Yong Cher, Mateo Valero
2008 — conf
Supercomputing for the Future, Supercomputing from the Past (Keynote).
HiPEAC
Mateo Valero, Jesús Labarta
2008 — conf
The limits of software transactional memory (STM): dissecting Haskell STM applications on a many-core environment.
Conf. Computing Frontiers
Cristian Perfumo, Nehir Sönmez, Srdjan Stipic, Osman S. Unsal, Adrián Cristal, Tim Harris, Mateo Valero
2008 — conf
Vectorized AES Core for High-throughput Secure Environments.
VECPAR
Miquel Pericàs, Ricardo Chaves, Georgi Gaydadjiev, Stamatis Vassiliadis, Mateo Valero
2008 — conf
WormBench: a configurable workload for evaluating transactional memory systems.
MEDEA@PACT
Ferad Zyulkyarov, Adrián Cristal, Sanja Cvijic, Eduard Ayguadé, Mateo Valero, Osman S. Unsal, Tim Harris
2007 B conf
A Flexible Heterogeneous Multi-Core Architecture.
PACT
Miquel Pericàs, Adrián Cristal, Francisco J. Cazorla, Rubén González, Daniel A. Jiménez, Mateo Valero
2007 J jnl
Energy saving through a simple load control mechanism.
SIGARCH Comput. Archit. News
Tanausú Ramírez, Alex Pajuelo, Oliverio J. Santana, Mateo Valero
2007 J jnl
Enlarging Instruction Streams.
IEEE Trans. Computers
Oliverio J. Santana, Alex Ramírez, Mateo Valero
2007 J jnl
Explaining Dynamic Cache Partitioning Speed Ups.
IEEE Comput. Archit. Lett.
Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero
2007 B conf
FAME: FAirly MEasuring Multithreaded Architectures.
PACT
Javier Vera, Francisco J. Cazorla, Alex Pajuelo, Oliverio J. Santana, Enrique Fernández, Mateo Valero
2007 — conf
HD-VideoBench. A Benchmark for Evaluating High Definition Digital Video Applications.
IISWC
Mauricio Alvarez, Esther Salamí, Alex Ramírez, Mateo Valero
2007 — conf
Hardware Transactional Memory with Operating System Support, HTMOS.
Euro-Par Workshops
Sasa Tomic, Adrián Cristal, Osman S. Unsal, Mateo Valero
2007 — conf
Implicit Transactional Memory in Kilo-Instruction Multiprocessors.
Asia-Pacific Computer Systems Architecture Conference
Marco Galluzzi, Enrique Vallejo, Adrián Cristal, Fernando Vallejo, Ramón Beivide, Per Stenström, James E. Smith, Mateo Valero
2007 B conf
MLP-Aware Dynamic Cache Partitioning.
PACT
Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero
2007 A conf
Microarchitectural Support for Speculative Register Renaming.
IPDPS
Jesús Alastruey, Teresa Monreal, Víctor Viñals, Mateo Valero
2007 — conf
Multithreaded software transactional memory and OpenMP.
MEDEA@PACT
Milos Milovanovic, Roger Ferrer, Vladimir Gajinov, Osman S. Unsal, Adrián Cristal, Eduard Ayguadé, Mateo Valero
2007 — conf
On the Problem of Minimizing Workload Execution Time in SMT Processors.
ICSAMOS
Francisco J. Cazorla, Enrique Fernández, Peter M. W. Knijnenburg, Alex Ramírez, Rizos Sakellariou, Mateo Valero
2007 — conf
Online Prediction of Applications Cache Utility.
ICSAMOS
Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero
2007 B conf
Performance Impact of Unaligned Memory Operations in SIMD Extensions for Video Codec Applications.
ISPASS
Mauricio Alvarez, Esther Salamí, Alex Ramírez, Mateo Valero
2007 B conf
Runahead Threads: Reducing Resource Contention in SMT Processors.
PACT
Tanausú Ramírez, Alex Pajuelo, Oliverio J. Santana, Mateo Valero
2007 — conf
Transactional Memory and OpenMP.
IWOMP
Milos Milovanovic, Roger Ferrer, Osman S. Unsal, Adrián Cristal, Xavier Martorell, Eduard Ayguadé, Jesús Labarta, Mateo Valero
2007 J jnl
Transactional Memory: An Overview.
IEEE Micro
Tim Harris, Adrián Cristal, Osman S. Unsal, Eduard Ayguadé, Fabrizio Gagliardi, Burton Smith, Mateo Valero
2007 — conf
unreadTVar: Extending Haskell Software Transactional Memory for Performance.
Trends in Functional Programming
Nehir Sönmez, Cristian Perfumo, Srdjan Stipic, Adrián Cristal, Osman S. Unsal, Mateo Valero
2006 J jnl
A DRAM/SRAM Memory Scheme for Fast Packet Buffers.
IEEE Trans. Computers
Jorge García-Vidal, Maribel March, Llorenç Cerdà, Jesús Corbal, Mateo Valero
2006 A* conf
A decoupled KILO-instruction processor.
HPCA
Miquel Pericàs, Adrián Cristal, Rubén González, Daniel A. Jiménez, Mateo Valero
2006 — conf
A simple speculative load control mechanism for energy saving.
MEDEA@PACT
Tanausú Ramírez, Alex Pajuelo, Oliverio J. Santana, Mateo Valero
2006 B conf
Branch predictor guided instruction decoding.
PACT
Oliverio J. Santana, Ayose Falcón, Alex Ramírez, Mateo Valero
2006 — conf
Kilo-instruction processors, runahead and prefetching.
Conf. Computing Frontiers
Tanausú Ramírez, Alex Pajuelo, Oliverio J. Santana, Mateo Valero
2006 — conf
Performance Analysis of Sequence Alignment Applications.
IISWC
Friman Sánchez, Esther Salamí, Alex Ramírez, Mateo Valero
2006 J jnl
Performance, power efficiency and scalability of asymmetric cluster chip multiprocessors.
IEEE Comput. Archit. Lett.
Tomer Y. Morad, Uri C. Weiser, A. Kolodnyt, Mateo Valero, Eduard Ayguadé
2006 J jnl
Predictable Performance in SMT Processors: Synergy between the OS and SMTs.
IEEE Trans. Computers
Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero
2006 — conf
Speculative early register release.
Conf. Computing Frontiers
Jesús Alastruey, Teresa Monreal, Víctor Viñals, Mateo Valero
2006 J jnl
The impact of traffic aggregation on the memory performance of networking applications.
J. Embed. Comput.
Javier Verdú, Jorge García-Vidal, Mario Nemirovsky, Mateo Valero
2005 B conf
A Complexity-Effective Simultaneous Multithreading Architecture.
ICPP
Carmelo Acosta, Ayose Falcón, Alex Ramírez, Mateo Valero
2005 C conf
A New Pointer-based Instruction Queue Design and Its Power-Performance Evaluation.
ICCD
Marco Antonio Ramírez, Adrián Cristal, Mateo Valero, Alexander V. Veidenbaum, Luis Villa
2005 B conf
A Vector-µSIMD-VLIW Architecture for Multimedia Applications.
ICPP
Esther Salamí, Mateo Valero
2005 A conf
An asymmetric clustered processor based on value content.
ICS
Rubén González, Adrián Cristal, Miquel Pericàs, Mateo Valero, Alexander V. Veidenbaum
2005 — conf
Architectural impact of stateful networking applications.
ANCS
Javier Verdú, Jorge García-Vidal, Mario Nemirovsky, Mateo Valero
2005 Misc conf
Architectural support for real-time task scheduling in SMT processors.
CASES
Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero
2005 J jnl
Better Branch Prediction Through Prophet/Critic Hybrids.
IEEE Micro
Ayose Falcón, Jared Stark, Alex Ramírez, Konrad K. Lai, Mateo Valero
2005 A conf
Control-Flow Independence Reuse via Dynamic Vectorization.
IPDPS
Alex Pajuelo, Antonio González, Mateo Valero
2005 — conf
Decoupled State-Execute Architecture.
ISHPC
Miquel Pericàs, Adrián Cristal, Rubén González, Alexander V. Veidenbaum, Mateo Valero
2005 J jnl
Dynamic memory interval test vs. interprocedural pointer analysis in multimedia applications.
ACM Trans. Archit. Code Optim.
Esther Salamí, Mateo Valero
2005 A conf
Effective Instruction Prefetching via Fetch Prestaging.
IPDPS
Ayose Falcón, Alex Ramírez, Mateo Valero
2005 — conf
Exploiting Execution Locality with a Decoupled Kilo-Instruction Processor.
ISHPC
Miquel Pericàs, Adrián Cristal, Rubén González, Daniel A. Jiménez, Mateo Valero
2005 J jnl
Fuzzy Memoization for Floating-Point Multimedia Applications.
IEEE Trans. Computers
Carlos Álvarez, Jesús Corbal, Mateo Valero
2005 J jnl
Hardware support for early register release.
Int. J. High Perform. Comput. Netw.
Teresa Monreal, Víctor Viñals, Antonio González, Mateo Valero
2005 — ed.
High Performance Embedded Architectures and Compilers, First International Conference, HiPEAC 2005, Barcelona, Spain, November 17-18, 2005, Proceedings
HiPEAC
Thomas M. Conte, Nacho Navarro, Wen-mei W. Hwu, Mateo Valero, Theo Ungerer
2005 — conf
Implementing Kilo-Instruction Multiprocessors.
ICPS
Enrique Vallejo, Marco Galluzzi, Adrián Cristal, Fernando Vallejo, Ramón Beivide, Per Stenström, James E. Smith, Mateo Valero
2005 J jnl
Kilo-Instruction Processors: Overcoming the Memory Wall.
IEEE Micro
Adrián Cristal, Oliverio J. Santana, Francisco J. Cazorla, Marco Galluzzi, Tanausú Ramírez, Miquel Pericàs, Mateo Valero
2005 — conf
Multiple Stream Prediction.
ISHPC
Oliverio J. Santana, Alex Ramírez, Mateo Valero
2005 B conf
On the Scalability of 1- and 2-Dimensional SIMD Extensions for Multimedia Applications.
ISPASS
Friman Sánchez, Mauricio Alvarez, Esther Salamí, Alex Ramírez, Mateo Valero
2005 B conf
Performance Analysis of a New Packet Trace Compressor based on TCP Flow Clustering.
ISPASS
Raimir Holanda, Javier Verdú, Jorge García-Vidal, Mateo Valero
2005 — ed.
Proceedings of the Second Conference on Computing Frontiers, 2005, Ischia, Italy, May 4-6, 2005
Conf. Computing Frontiers
Nader Bagherzadeh, Mateo Valero, Alex Ramírez
2005 J jnl
Software Trace Cache.
IEEE Trans. Computers
Alex Ramírez, Josep Lluís Larriba-Pey, Mateo Valero
2005 J jnl
Speculative execution for hiding memory latency.
SIGARCH Comput. Archit. News
Alex Pajuelo, Antonio González, Mateo Valero
2005 J jnl
The impact of traffic aggregation on the memory performance of networking applications.
SIGARCH Comput. Archit. News
Javier Verdú, Jorge García-Vidal, Mario Nemirovsky, Mateo Valero
2005 — conf
Workload Characterization of Stateful Networking Applications.
ISHPC
Javier Verdú, Mario Nemirovsky, Jorge García-Vidal, Mateo Valero
2004 A* conf
A Content Aware Integer Register File Organization.
ISCA
Rubén González, Adrián Cristal, Daniel Ortega, Alexander V. Veidenbaum, Mateo Valero
2004 A* conf
A Low-Complexity, High-Performance Fetch Unit for Simultaneous Multithreading Processors.
HPCA
Ayose Falcón, Alex Ramírez, Mateo Valero
2004 J jnl
A case for resource-conscious out-of-order processors: towards kilo-instruction in-flight processors.
SIGARCH Comput. Archit. News
Adrián Cristal, José F. Martínez, Josep Llosa, Mateo Valero
2004 J jnl
A comprehensive description of kilo-instructions processors.
Res. Comput. Sci.
Adrián Cristal, Mateo Valero, Oliverio J. Santana
2004 — conf
A first glance at Kilo-instruction based multiprocessors.
Conf. Computing Frontiers
Marco Galluzzi, Valentin Puente, Adrián Cristal, Ramón Beivide, José-Ángel Gregorio, Mateo Valero
2004 J jnl
A latency-conscious SMT branch prediction architecture.
Int. J. High Perform. Comput. Netw.
Ayose Falcón, Oliverio J. Santana, Alex Ramírez, Mateo Valero
2004 J jnl
A low-complexity fetch architecture for high-performance superscalar processors.
ACM Trans. Archit. Code Optim.
Oliverio J. Santana, Alex Ramírez, Josep Lluís Larriba-Pey, Mateo Valero
2004 J jnl
A partitioned instruction queue to reduce instruction wakeup energy.
Int. J. High Perform. Comput. Netw.
Marco Antonio Ramírez, Adrián Cristal, Mateo Valero, Alexander V. Veidenbaum, Luis Villa
2004 — conf
An Optimized Front-End Physical Register File with Banking and Writeback Filtering.
PACS
Miquel Pericàs, Rubén González, Adrián Cristal, Alexander V. Veidenbaum, Mateo Valero
2004 A conf
DCache Warn: An I-Fetch Policy to Increase SMT Efficiency.
IPDPS
Francisco J. Cazorla, Alex Ramírez, Mateo Valero, Enrique Fernández
2004 J jnl
Dynamic Memory Instruction Bypassing.
Int. J. Parallel Program.
Daniel Ortega, Mateo Valero, Eduard Ayguadé
2004 A* conf
Dynamically Controlled Resource Allocation in SMT Processors.
MICRO
Francisco J. Cazorla, Alex Ramírez, Mateo Valero, Enrique Fernández
2004 — conf
Enabling SMT for real-time embedded systems.
EUSIPCO
Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero
2004 — conf
Evaluating kilo-instruction multiprocessors.
WMPI
Marco Galluzzi, Ramón Beivide, Valentin Puente, José-Ángel Gregorio, Adrián Cristal, Mateo Valero
2004 — conf
Feasibility of QoS for SMT.
Euro-Par
Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero
2004 J jnl
Future ILP processors.
Int. J. High Perform. Comput. Netw.
Adrián Cristal, Josep Llosa, Mateo Valero, Daniel Ortega
2004 J jnl
High-performance and low-power VLIW cores for numerical computations.
Int. J. High Perform. Comput. Netw.
Miquel Pericàs, Eduard Ayguadé, Javier Zalamea, Josep Llosa, Mateo Valero
2004 C conf
Implicit vs. Explicit Resource Allocation in SMT Processors.
DSD
Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero
2004 — conf
Initial Evaluation of Multimedia Extensions on VLIW Architectures.
SAMOS
Esther Salamí, Mateo Valero
2004 J jnl
Instructions-Wake-Up mechanism: Power and Timing Evaluation.
Res. Comput. Sci.
Adrián Cristal, Alexander V. Veidenbaum, Luis Villa, Marco A. Ramírez, Mateo Valero
2004 J jnl
Late Allocation and Early Release of Physical Registers.
IEEE Trans. Computers
Teresa Monreal, Víctor Viñals, José González, Antonio González, Mateo Valero
2004 — conf
Maintaining Thousands of In-flight Instructions.
Euro-Par
Adrián Cristal, Oliverio J. Santana, Mateo Valero
2004 J jnl
Optimising long-latency-load-aware fetch policies for SMT processors.
Int. J. High Perform. Comput. Netw.
Francisco J. Cazorla, Alex Ramírez, Mateo Valero, Enrique Fernández
2004 A* conf
Out-of-Order Commit Processors.
HPCA
Adrián Cristal, Daniel Ortega, Josep Llosa, Mateo Valero
2004 — conf
Performance and Power Evaluation of Clustered VLIW Processors with Wide Functional Units.
SAMOS
Miquel Pericàs, Eduard Ayguadé, Javier Zalamea, Josep Llosa, Mateo Valero
2004 — conf
Predictable performance in SMT processors.
Conf. Computing Frontiers
Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero
2004 A* conf
Prophet/Critic Hybrid Branch Prediction.
ISCA
Ayose Falcón, Jared Stark, Alex Ramírez, Konrad Lai, Mateo Valero
2004 J jnl
QoS for High-Performance SMT Processors in Embedded Systems.
IEEE Micro
Francisco J. Cazorla, Alex Ramírez, Mateo Valero, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández
2004 — conf
Reducing Fetch Architecture Complexity Using Procedure Inlining.
Interaction between Compilers and Computer Architectures
Oliverio J. Santana, Alex Ramírez, Mateo Valero
2004 J jnl
Register Constrained Modulo Scheduling.
IEEE Trans. Parallel Distributed Syst.
Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero
2004 J jnl
Software and Hardware Techniques to Optimize Register File Utilization in VLIW Architectures.
Int. J. Parallel Program.
Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero
2004 — conf
Speculative execution for hiding memory latency.
MEDEA@PACT
Alex Pajuelo, Antonio González, Mateo Valero
2004 — conf
The impact of traffic aggregation on the memory performance of networking applications.
MEDEA@PACT
Javier Verdú, Jorge García, Mario Nemirovsky, Mateo Valero
2004 J jnl
Toward kilo-instruction processors.
ACM Trans. Archit. Code Optim.
Adrián Cristal, Oliverio J. Santana, Mateo Valero, José F. Martínez
2003 J jnl
A Case for Resource-conscious Out-of-order Processors.
IEEE Comput. Archit. Lett.
Adrián Cristal, José F. Martínez, Josep Llosa, Mateo Valero
2003 J jnl
A Cost-Effective Architecture for Vectorizable Numerical and Multimedia Applications.
Theory Comput. Syst.
Francisca Quintana, Jesús Corbal, Roger Espasa, Mateo Valero
2003 — conf
A Simple Low-Energy Instruction Wakeup Mechanism.
ISHPC
Marco Antonio Ramírez, Adrián Cristal, Alexander V. Veidenbaum, Luis Villa, Mateo Valero
2003 B conf
A conflict-free memory banking architecture for fast VOQ packet buffers.
GLOBECOM
Jorge Garcia, Llorenç Cerdà, Jesús Corbal, Mateo Valero
2003 B conf
An MPEG-4 performance study for non-SIMD, general purpose architectures.
ISPASS
Sally A. McKee, Zhen Fang, Mateo Valero
2003 A* conf
Design and Implementation of High-Performance Memory Systems for Future Packet Buffers.
MICRO
Jorge García-Vidal, Jesús Corbal, Llorenç Cerdà, Mateo Valero
2003 A conf
Dynamic memory instruction bypassing.
ICS
Daniel Ortega, Eduard Ayguadé, Mateo Valero
2003 A conf
Hierarchical Clustered Register File Organization for VLIW Processors.
IPDPS
Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero
2003 — conf
Improving Memory Latency Aware Fetch Policies for SMT Processors.
ISHPC
Francisco J. Cazorla, Enrique Fernández, Alex Ramírez, Mateo Valero
2003 — conf
Kilo-instruction Processors.
ISHPC
Adrián Cristal, Daniel Ortega, Josep Llosa, Mateo Valero
2003 — conf
Power-Performance Trade-Offs in Wide and Clustered VLIW Cores for Numerical Codes.
ISHPC
Miquel Pericàs, Eduard Ayguadé, Javier Zalamea, Josep Llosa, Mateo Valero
2003 — conf
Tolerating Branch Predictor Latency on SMT.
ISHPC
Ayose Falcón, Oliverio J. Santana, Alex Ramírez, Mateo Valero
2002 — conf
A Comparative Study of Redundancy in Trace Caches (Research Note).
Euro-Par
Hans Vandierendonck, Alex Ramírez, Koenraad De Bosschere, Mateo Valero
2002 — conf
A Comprehensive Analysis of Indirect Branch Prediction.
ISHPC
Oliverio J. Santana, Ayose Falcón, Enrique Fernández, Pedro Medina, Alex Ramírez, Mateo Valero
2002 Misc conf
Cost effective memory disambiguation for multimedia codes.
CASES
Esther Salamí, Jesús Corbal, Carlos Álvarez, Mateo Valero
2002 — conf
Cost-Effective Compiler Directed Memory Prefetching and Bypassing.
IEEE PACT
Daniel Ortega, Eduard Ayguadé, Jean-Loup Baer, Mateo Valero
2002 J jnl
Errata on "Measuring Experimental Error in Microprocessor Simulation".
SIGARCH Comput. Archit. News
Rajagopalan Desikan, Doug Burger, Stephen W. Keckler, José-Lorenzo Cruz, Fernando Latorre, Antonio González, Mateo Valero
2002 A* conf
Fetching instruction streams.
MICRO
Alex Ramírez, Oliverio J. Santana, Josep Lluís Larriba-Pey, Mateo Valero
2002 B conf
Hardware Schemes for Early Register Release.
ICPP
Teresa Monreal, Víctor Viñals, Antonio González, Mateo Valero
2002 J jnl
Initial Results on Fuzzy Floating Point Computation for Multimedia Processors.
IEEE Comput. Archit. Lett.
Carlos Álvarez, Jesús Corbal, Esther Salamí, Mateo Valero
2002 J jnl
Software Trace Cache for Commercial Applications.
Int. J. Parallel Program.
Alex Ramírez, Josep Lluís Larriba-Pey, Carlos Navarro, Mateo Valero, Josep Torrellas
2002 A* conf
Speculative Dynamic Vectorization.
ISCA
Alex Pajuelo, Antonio González, Mateo Valero
2002 — conf
Studying New Ways for Improving Adaptive History Length Branch Predictors.
ISHPC
Ayose Falcón, Oliverio J. Santana, Pedro Medina, Enrique Fernández, Alex Ramírez, Mateo Valero
2002 A* conf
Three-dimensional memory vectorization for high bandwidth media memory systems.
MICRO
Jesús Corbal, Roger Espasa, Mateo Valero
2001 B conf
A cost effective architecture for vectorizable numerical and multimedia applications.
SPAA
Francisca Quintana, Jesús Corbal, Roger Espasa, Mateo Valero
2001 A conf
A novel renaming mechanism that boosts software prefetching.
ICS
Daniel Ortega, Mateo Valero, Eduard Ayguadé
2001 — conf
Branch Prediction Using Profile Data.
Euro-Par
Alex Ramírez, Josep Lluís Larriba-Pey, Mateo Valero
2001 A* conf
Code layout optimizations for transaction processing workloads.
ISCA
Alex Ramírez, Luiz André Barroso, Kourosh Gharachorloo, Robert S. Cohn, Josep Lluís Larriba-Pey, P. Geoffrey Lowney, Mateo Valero
2001 J jnl
Cost-Conscious Strategies to Increase Performance of Numerical Programs on Aggressive VLIW Architectures.
IEEE Trans. Computers
David López, Josep Llosa, Mateo Valero, Eduard Ayguadé
2001 A* conf
DLP + TLP Processors for the Next Generation of Media Workloads.
HPCA
Jesús Corbal, Roger Espasa, Mateo Valero
2001 J jnl
Early 21st Century Processors - Guest Editors' Introduction.
Computer
Sriram Vajapeyam, Mateo Valero
2001 J jnl
Instruction fetch architectures and code layout optimizations.
Proc. IEEE
Alex Ramírez, Josep Lluís Larriba-Pey, Mateo Valero
2001 J jnl
Lifetime-Sensitive Modulo Scheduling in a Production Environment.
IEEE Trans. Computers
Josep Llosa, Eduard Ayguadé, Antonio González, Mateo Valero, Jason Eckhardt
2001 A* conf
Modulo scheduling with integrated register spilling for clustered VLIW architectures.
MICRO
Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero
2001 — conf
On the Efficiency of Reductions in µ-SIMD Media Extensions.
IEEE PACT
Jesús Corbal, Roger Espasa, Mateo Valero
2001 A conf
On the potential of tolerant region reuse for multimedia applications.
ICS
Carlos Álvarez, Jesús Corbal, Esther Salamí, Mateo Valero
2001 J jnl
Parallel architecture and compilation techniques: selection of workshop papers, guests' editors introduction.
SIGARCH Comput. Archit. News
Sandro Bartolini, Roberto Giorgi, Jelica Protic, Cosimo Antonio Prete, Mateo Valero
2001 B ed.
Proceedings of the 2001 International Conference on Parallel Processing, ICPP 2002, 3-7 September 2001, Valencia, Spain
ICPP
Lionel M. Ni, Mateo Valero
2001 — conf
Topic 15+20: Multimedia and Embedded Systems.
Euro-Par
Stamatis Vassiliadis, Francky Catthoor, Mateo Valero, Sorin Cotofana
2000 — conf
Architectures for One Billion of Transistors.
ISSS
Mateo Valero
2000 J jnl
Dynamic Register Renaming Through Virtual-Physical Registers.
J. Instr. Level Parallelism
Teresa Monreal, Antonio González, Mateo Valero, José González, Víctor Viñals
2000 Misc ed.
High Performance Computing - HiPC 2000, 7th International Conference, Bangalore, India, December 17-20, 2000, Proceedings
HiPC
Mateo Valero, Viktor K. Prasanna, Sriram Vajapeyam
2000 — ed.
High Performance Computing, Third International Symposium, ISHPC 2000, Tokyo, Japan, October 16-18, 2000. Proceedings
ISHPC
Mateo Valero, Kazuki Joe, Masaru Kitsuregawa, Hidehiko Tanaka
2000 A* conf
Improved spill code generation for software pipelined loops.
PLDI
Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero
2000 A* conf
Multiple-banked register file architectures.
ISCA
José-Lorenzo Cruz, Antonio González, Mateo Valero, Nigel P. Topham
2000 — conf
On the Performance of Fetch Engines Running DSS Workloads.
Euro-Par
Carlos Navarro, Alex Ramírez, Josep Lluís Larriba-Pey, Mateo Valero
2000 — conf
Parallel Computer Architecture.
Euro-Par
Silvia M. Müller, Per Stenström, Mateo Valero, Stamatis Vassiliadis
2000 — conf
The Effect of Code Reordering on Branch Prediction.
IEEE PACT
Alex Ramírez, Josep Lluís Larriba-Pey, Mateo Valero
2000 A* conf
Trace Cache Redundancy: Red & Blue Traces.
HPCA
Alex Ramírez, Josep Lluís Larriba-Pey, Mateo Valero
2000 A* conf
Two-level hierarchical register file organization for VLIW processors.
MICRO
Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero
1999 J jnl
A Simulation Study of Decoupled Vector Architectures.
J. Supercomput.
Roger Espasa, Mateo Valero
1999 A conf
Adding a vector unit to a superscalar processor.
International Conference on Supercomputing
Francisca Quintana, Jesús Corbal, Roger Espasa, Mateo Valero
1999 A* conf
Delaying Physical Register Allocation through Virtual-Physical Registers.
MICRO
Teresa Monreal, Antonio González, Mateo Valero, José González, Víctor Viñals
1999 J jnl
Enhancing and Exploiting the Locality.
IEEE Trans. Computers
Veljko M. Milutinovic, Mateo Valero
1999 A* conf
Exploiting a New Level of DLP in Multimedia Applications.
MICRO
Jesús Corbal, Roger Espasa, Mateo Valero
1999 B conf
Impact on Performance of Fused Multiply-Add Units in Aggressive VLIW Architectures.
ICPP
David López, Josep Llosa, Eduard Ayguadé, Mateo Valero
1999 A conf
Increasing effective IPC by exploiting distant parallelism.
International Conference on Supercomputing
Ivan Martel, Daniel Ortega, Eduard Ayguadé, Mateo Valero
1999 — conf
Instruction-Level Parallelism and Uniprocessor Architecture - Introduction.
Euro-Par
Pascal Sainrat, Mateo Valero
1999 A conf
MOM: a Matrix SIMD Instruction Set Architecture for Multimedia Applications.
SC
Jesús Corbal, Roger Espasa, Mateo Valero
1999 B conf
Optimization of Instruction Fetch for Decision Support Workloads.
ICPP
Alex Ramírez, Josep Lluís Larriba-Pey, Carlos Navarro, Xavi Serrano, Mateo Valero, Josep Torrellas
1999 A ed.
Proceedings of the 13th international conference on Supercomputing, ICS 1999, Rhodes, Greece, June 20-25, 1999
ICS
Theodore S. Papatheodorou, Mateo Valero, Constantine D. Polychronopoulos, Yoichi Muraoka, Jesús Labarta
1999 — conf
Quantifying the Benefits of SPECint Distant Parallelism in Simultaneous Multi-Threading Architectures.
IEEE PACT
Daniel Ortega, Ivan Martel, Venkata Krishnan, Eduard Ayguadé, Mateo Valero
1999 A conf
Software trace cache.
International Conference on Supercomputing
Alex Ramírez, Josep Lluís Larriba-Pey, Carlos Navarro, Josep Torrellas, Mateo Valero
1998 A conf
A Performance Study of Out-of-order Vector Architectures and Short Registers.
International Conference on Supercomputing
Luis Villa, Roger Espasa, Mateo Valero
1998 C conf
A case for merging the ILP and DLP paradigms.
PDP
Francisca Quintana, Roger Espasa, Mateo Valero
1998 — conf
An ISA Comparison Between Superscalar and Vector Processors.
VECPAR
Francisca Quintana, Roger Espasa, Mateo Valero
1998 — conf
Command Vector Memory Systems: High Performance at Low Cost.
IEEE PACT
Jesús Corbal, Roger Espasa, Mateo Valero
1998 C conf
Effective usage of vector registers in decoupled vector architectures.
PDP
Luis Villa, Roger Espasa, Mateo Valero
1998 J jnl
Modulo Scheduling with Reduced Register Pressure.
IEEE Trans. Computers
Josep Llosa, Mateo Valero, Eduard Ayguadé, Antonio González
1998 A* ed.
Proceedings of the 25th Annual International Symposium on Computer Architecture, ISCA 1998, Barcelona, Spain, June 27 - July 1, 1998
ISCA
Mateo Valero, Gurindar S. Sohi, Doug DeGroot
1998 J jnl
Quantitative Evaluation of Register Pressure on Software Pipelined Loops.
Int. J. Parallel Program.
Josep Llosa, Eduard Ayguadé, Mateo Valero
1998 — conf
Registers Size Influence on Vector Architectures.
VECPAR
Luis Villa, Roger Espasa, Mateo Valero
1998 A conf
Resource Widening Versus Replication: Limits and Performance-cost Trade-off.
International Conference on Supercomputing
David López, Josep Llosa, Mateo Valero, Eduard Ayguadé
1998 A conf
Vector Architectures: Past, Present and Future.
International Conference on Supercomputing
Roger Espasa, Mateo Valero, James E. Smith
1998 A* conf
Virtual-Physical Registers.
HPCA
Antonio González, José González, Mateo Valero
1998 A* conf
Widening Resources: A Cost-effective Technique for Aggressive ILP Architectures.
MICRO
David López, Josep Llosa, Mateo Valero, Eduard Ayguadé
1997 A conf
A Victim Cache for Vector Registers.
International Conference on Supercomputing
Roger Espasa, Mateo Valero
1997 — conf
Effective Usage of Vector Registers in Advanced Vector Architectures.
IEEE PACT
Luis Villa, Roger Espasa, Mateo Valero
1997 A conf
Eliminating Cache Conflict Misses through XOR-Based Placement Functions.
International Conference on Supercomputing
Antonio González, Mateo Valero, Nigel P. Topham, Joan-Manuel Parcerisa
1997 J jnl
Exploiting instruction- and data-level parallelism.
IEEE Micro
Roger Espasa, Mateo Valero
1997 A conf
Increasing Memory Bandwidth with Wide Buses: Compiler, Hardware and Performance Trade-Offs.
International Conference on Supercomputing
David López, Mateo Valero, Josep Llosa, Eduard Ayguadé
1997 A* conf
Multithreaded Vector Architectures.
HPCA
Roger Espasa, Mateo Valero
1997 A* conf
Out-of-Order Vector Architectures.
MICRO
Roger Espasa, Mateo Valero, James E. Smith
1997 Misc conf
Simultaneous multithreaded vector architecture: merging ILP and DLP for high performance.
HiPC
Roger Espasa, Mateo Valero
1997 — conf
Static Locality Analysis for Cache Management.
IEEE PACT
F. Jesús Sánchez, Antonio González, Mateo Valero
1997 Misc conf
Virtual registers.
HiPC
Antonio González, Mateo Valero, José González, Teresa Monreal Arnal
1996 A* conf
Decoupled Vector Architectures.
HPCA
Roger Espasa, Mateo Valero
1996 A* conf
Heuristics for Register-Constrained Software Pipelining.
MICRO
Josep Llosa, Mateo Valero, Eduard Ayguadé
1996 C conf
Loop Parallelization: Revisiting Framework of Unimodular Transformations.
PDP
Jordi Torres, Eduard Ayguadé, Jesús Labarta, Mateo Valero
1996 — conf
Swing module scheduling: a lifetime-sensitive approach.
IEEE PACT
Josep Llosa, Antonio González, Eduard Ayguadé, Mateo Valero
1995 A conf
A Data Cache with Multiple Caching Strategies Tuned to Different Types of Locality.
International Conference on Supercomputing
Antonio González, Carlos Aliagas, Mateo Valero
1995 J jnl
Analyzing reference patterns in automatic data distribution tools.
Int. J. Parallel Program.
Eduard Ayguadé, Jesús Labarta, Jordi Garcia, Mercè Gironés, Mateo Valero
1995 B conf
Automatic generation of loop scheduling for VLIW.
PACT
Cristina Barrado, Jesús Labarta, Eduard Ayguadé, Mateo Valero
1995 J jnl
Conflict-Free Access for Streams in Multimodule Memories.
IEEE Trans. Computers
Mateo Valero, Tomás Lang, Montse Peiron, Eduard Ayguadé
1995 A* conf
Hypernode reduction modulo scheduling.
MICRO
Josep Llosa, Mateo Valero, Eduard Ayguadé, Antonio González
1995 A* conf
Non-Consistent Dual Register Files to Reduce Register Pressure.
HPCA
Josep Llosa, Mateo Valero, Eduard Ayguadé
1995 A ed.
Proceedings of the 9th international conference on Supercomputing, ICS 1995, Barcelona, Spain, July 3-7, 1995
ICS
Mateo Valero
1995 C conf
Quantitative analysis of vector code.
PDP
Roger Espasa, Mateo Valero, David A. Padua, Marta Jiménez, Eduard Ayguadé
1995 A* conf
Vector Multiprocessors with Arbitrated Memory Access.
ISCA
Montse Peiron, Mateo Valero, Eduard Ayguadé, Tomás Lang
1994 C conf
Access To Vectors In Multi-module Memories.
PDP
Mateo Valero, Montse Peiron, Eduard Ayguadé
1994 — conf
Detecting and Using Affinity in an Automatic Data Distribution Tool.
LCPC
Eduard Ayguadé, Jordi Garcia, Mercè Gironés, Jesús Labarta, Jordi Torres, Mateo Valero
1994 — conf
Memory Access Synchronization in Vector Multiprocessors.
CONPAR
Mateo Valero, Montse Peiron, Eduard Ayguadé
1994 J jnl
Network Synchronization and Out-of-Order Access to Vectors.
Parallel Process. Lett.
Mateo Valero, Eduard Ayguadé, Montse Peiron
1994 A conf
Synchronized access to streams in SIMD vector multiprocessors.
International Conference on Supercomputing
Montse Peiron, Mateo Valero, Eduard Ayguadé
1994 — conf
Using Sacks to Organize Registers in VLIW Machines.
CONPAR
Josep Llosa, Mateo Valero, José A. B. Fortes, Eduard Ayguadé
1993 C conf
Access to streams in multiprocessor systems.
PDP
Mateo Valero, Montse Peiron, Eduard Ayguadé
1993 — conf
Align and Distribute-based Linear Loop Transformations.
LCPC
Jordi Torres, Eduard Ayguadé, Jesús Labarta, Mateo Valero
1993 J jnl
Chairmen's introduction.
Microprocess. Microprogramming
Mateo Valero, Jordi Cortadella, Antonio González
1993 J jnl
Conflict-free access to streams in multiprocessor systems.
Microprocess. Microprogramming
Montse Peiron, Mateo Valero, Eduard Ayguadé, Tomás Lang
1992 J jnl
A method for implementation of one-dimensional systolic algorithms with data contraflow using pipelined functional units.
J. VLSI Signal Process.
Miguel Valero-García, Juan J. Navarro, José María Llabería, Mateo Valero, Tomás Lang
1992 A conf
Conflict-free access of vectors with power-of-two strides.
ICS
Mateo Valero, Tomás Lang, Eduard Ayguadé
1992 A* conf
Increasing the Number of Strides for Conflict-Free Vector Access.
ISCA
Mateo Valero, Tomás Lang, José M. Llabería, Montse Peiron, Eduard Ayguadé, Juan J. Navarro
1991 — conf
Balanced Loop Partitioning Using GTS.
LCPC
Jesús Labarta, Eduard Ayguadé, Jordi Torres, Mateo Valero, José M. Llabería
1991 J jnl
Conflict-Free Strides for Vectors in Matched Memories.
Parallel Process. Lett.
Mateo Valero, Tomás Lang, José María Llabería, Montse Peiron, Juan J. Navarro, Eduard Ayguadé
1991 — conf
Mapping QR decomposition of a banded matrix on a ID systolic array with data contraflow and pipelined functional units.
Algorithms and Parallel VLSI Architectures
Miguel Valero-García, Juan J. Navarro, José J. M. Liabería, Mateo Valero, Tomás Lang
1991 — conf
On Automatic Loop Data-Mapping for Distributed-Memory Multiprocessors.
EDMCC
Jordi Torres, Eduard Ayguadé, Jesús Labarta, José M. Llabería, Mateo Valero
1990 — conf
Implementation of systolic algorithms using pipelined functional units.
ASAP
Miguel Valero-García, Juan J. Navarro, José M. Llabería, Mateo Valero
1989 J jnl
A block algorithm and optimal fixed-size systolic array processor for the algebraic path problem.
J. VLSI Signal Process.
Fernando J. Nuñez, Mateo Valero
1989 A* conf
Systematic Hardware Adaptation of Systolic Algorithms.
ISCA
Miguel Valero-García, Juan J. Navarro, José M. Llabería, Mateo Valero
1987 J jnl
A Discrete Optimization Problem in Local Networks and Data Alignment.
IEEE Trans. Computers
Miguel Angel Fiol, J. Luis A. Yebra, Ignacio Alegre, Mateo Valero
1987 J jnl
Partitioning: An Essential Step in Mapping Algorithms Into Systolic Array Processors.
Computer
Juan J. Navarro, José M. Llabería, Mateo Valero
1986 A* conf
Computing Size-Independent Matrix Problems on Systolic Array Processors.
ISCA
Juan J. Navarro, José M. Llabería, Mateo Valero
1986 B conf
Solving Matrix Problems with No Size Restriction on a Systolic Array Processor.
ICPP
Juan J. Navarro, José M. Llabería, Mateo Valero
1985 A* conf
Analysis and Simulation of Multiplexed Single-Bus Networks With and Without Buffering.
ISCA
José M. Llabería, Mateo Valero, Enrique Herrada Lillo, Jesús Labarta
1983 A* conf
A performance evaluation of the multiple bus network for multiprocessor systems.
SIGMETRICS
Mateo Valero, José María Llabería, Jesús Labarta, Emilio Sanvicente, Tomás Lang
1983 J jnl
Reduction of Connections for Multibus Organization.
IEEE Trans. Computers
Tomás Lang, Mateo Valero, Miguel Angel Fiol
1982 J jnl
Bandwidth of Crossbar and Multiple-Bus Connections for Multiprocessors.
IEEE Trans. Computers
Tomás Lang, Mateo Valero, Ignacio Alegre