Masumi Saitoh

12 papers Journal 2Unranked 10
YearRankTypeTitle / Venue / Authors
2025 — conf
Cycling Induced Imprint Phenomenon at Intermediate State used for Multi-Level Operation in HfO2-FeFET.
IRPS
Viktoria Schlykow, Kunifumi Suzuki, Yoko Yoshimura, Hidesato Ishida, Kiwamu Sakuma, Kazuhiro Matsuo, Masumi Saitoh, Reika Ichihara
2024 — conf
A Vertical Channel-All-Around FeFET with Thermally Stable Oxide Semiconductor Achieving High ΔIon> 2µA/cell for 3D Stackable 4F
VLSI Technology and Circuits
Shoichi Kabuyanagi, Takamasa Hamai, Masayuki Murase, Takeru Maeda, Masumi Saitoh, Shosuke Fujii
2023 — conf
Comprehensive Analysis of Hole-Trapping in SiN Films with a Wide Range of Time Constants Based on Dynamic C-V.
IRPS
Harumi Seki, Reika Ichihara, Yusuke Higashi, Yasushi Nakasaki, Masumi Saitoh, Masamichi Suzuki
2023 — conf
Novel Operation Scheme for Suppressing Disturb in HfO2-based FeFET Considering Charge- Trapping-Coupled Polarization Dynamics.
IRPS
Takamasa Hamai, Kunifumi Suzuki, Reika Ichihara, Yusuke Higashi, Yoko Yoshimura, Kiwamu Sakuma, Kensuke Ota, Kota Takahashi, Kazuhiro Matsuo, Shosuke Fujii, Masumi Saitoh
2020 — conf
Breakdown Lifetime Analysis of HfO2-based Ferroelectric Tunnel Junction (FTJ) Memory for In-Memory Reinforcement Learning.
IRPS
Marina Yamaguchi, Shosuke Fujii, Kensuke Ota, Masumi Saitoh
2019 — conf
Ag Ionic Memory Cell Technology for Terabit-Scale High-DensityApplication.
VLSI Circuits
Shosuke Fujii, Reika Ichihara, Takuya Konno, Marina Yamaguchi, Harumi Seki, Hiroki Tanaka, Dandan Zhao, Yoko Yoshimura, Masumi Saitoh, Masato Koyama
2018 — conf
Emerging Non-Volatile Memory and Thin-Film Transistor Technologies for Future 3D-LSI.
ESSDERC
Masumi Saitoh, Shosuke Fujii, Minoru Oda, Marina Yamaguchi, Shoichi Kabuyanagi, Yoko Yoshimura, Kensuke Ota, Kiwamu Sakuma, Yuuichi Kamimuta
2018 — conf
Hot carrier degradation, TDDB, and 1/f noise in Poly-Si Tri-gate nanowire transistor.
IRPS
Yoko Yoshimura, Kensuke Ota, Masumi Saitoh
2018 — conf
Impact of specific failure mechanisms on endurance improvement for HfO2-based ferroelectric tunnel junction memory.
IRPS
Marina Yamaguchi, Shosuke Fujii, Yuuichi Kamimuta, Shoichi Kabuyanagi, Tsunehiro Ino, Yasushi Nakasaki, Riichiro Takaishi, Reika Ichihara, Masumi Saitoh
2016 J jnl
BSIM4 parameter extraction for tri-gate Si nanowire transistors.
Microelectron. J.
Chika Tanaka, Masumi Saitoh, Kensuke Ota, Takayuki Ishikawa, Toshinori Numata
2015 — conf
New layout design methodology for monolithically integrated 3D CMOS logic circuits based on parasitics engineering.
ESSDERC
Chika Tanaka, Keiji Ikeda, Masumi Saitoh
2006 J jnl
Emerging nanoscale silicon devices taking advantage of nanostructure physics.
IBM J. Res. Dev.
Toshiro Hiramoto, Masumi Saitoh, Gen Tsutsui