Masud H. Chowdhury

125 papers A* 2A 2C 29Journal 28Unranked 63

Year	Rank	Type	Title / Venue / Authors
2022	J	`jnl`	Design of novel 3T ternary DRAM with single word-line using CNTFET. Microelectron. J. Zarin Tasnim Sandhie, Farid Uddin Ahmed, Masud H. Chowdhury
2022	J	`jnl`	Investigation of Multiple-valued Logic Technologies for Beyond-binary Era. ACM Comput. Surv. Zarin Tasnim Sandhie, Jill Arvindbhai Patel, Farid Uddin Ahmed, Masud H. Chowdhury
2021	J	`jnl`	A Brief Overview of On-Chip Voltage Regulation in High-Performance and High-Density Integrated Circuits. IEEE Access Farid Uddin Ahmed, Zarin Tasnim Sandhie, Liaquat Ali, Masud H. Chowdhury
2021	J	`jnl`	Design of Novel 3T Ternary DRAM with Single Word-Line using CNTFET. CoRR Zarin Tasnim Sandhie, Farid Uddin Ahmed, Masud H. Chowdhury
2021	J	`jnl`	FinFET based SRAMs in Sub-10nm domain. Microelectron. J. Mahmood Uddin Mohammed, Athiya Nizam, Liaquat Ali, Masud H. Chowdhury
2021	J	`jnl`	SecNVM: Power Side-Channel Elimination Using On-Chip Capacitors for Highly Secure Emerging NVM. IEEE Trans. Very Large Scale Integr. Syst. Karthikeyan Nagarajan, Farid Uddin Ahmed, Mohammad Nasim Imtiaz Khan, Asmit De, Masud H. Chowdhury, Swaroop Ghosh
2020	C	`conf`	An Implementation of External Capacitor-less Low-DropOut Voltage Regulator in 45nm Technology with Output Voltage Ranging from 0.4V-1.2V. ICCD Farid Uddin Ahmed, Zarin Tasnim Sandhie, Masud H. Chowdhury
2020	—	`conf`	Design of Ternary Master-Slave D-Flip Flop using MOS-GNRFET. MWSCAS Zarin Tasnim Sandhie, Farid Uddin Ahmed, Masud H. Chowdhury
2020	—	`conf`	GNRFET based Ternary Logic - Prospects and Potential Implementation. LASCAS Zarin Tasnim Sandhie, Farid Uddin Ahmed, Masud H. Chowdhury
2019	C	`conf`	A Low Leakage SRAM Bitcell Design Based on MOS-Type Graphene Nano-Ribbon FET. ISCAS Mahmood Uddin Mohammed, Athiya Nizam, Liaquat Ali, Masud H. Chowdhury
2019	C	`conf`	Design of Energy Efficient SRAM Cell Based on Double Gate Schottky-Barrier-Type GNRFET with Minimum Dimer Lines. ISCAS Mahmood Uddin Mohammed, Masud H. Chowdhury
2018	—	`conf`	A Disturb Free Read Port 8T SRAM Bitcell Circuit Design with Virtual Ground Scheme. MWSCAS Mahmood Uddin Mohammed, Nahid M. Hossain, Masud H. Chowdhury
2018	J	`jnl`	A New Power Gating Circuit Design Approach Using Double-Gate FDSOI. IEEE Trans. Circuits Syst. II Express Briefs Emeshaw Ashenafi, Masud H. Chowdhury
2018	—	`conf`	An Asynchronous Reconfigurable Switched Capacitor Voltage Regulator. MWSCAS Farid Uddin Ahmed, Masud H. Chowdhury
2018	C	`conf`	Capacitor-less Low-Dropout Regulator (LDO) with Improved PSRR and Enhanced Slew-Rate. ISCAS Marouf Khan, Masud H. Chowdhury
2018	C	`conf`	Failure Analysis of the Through Silicon Via in Three-dimensional Integrated Circuit (3D-IC). ISCAS Nahid M. Hossain, Ritesh Kumar Reddy Kuchukulla, Masud H. Chowdhury
2018	J	`jnl`	Investigation and Optimization of Spiral Inductor Design for On-Chip Buck Converter. J. Low Power Electron. Emeshaw Ashenafi, Abdul Hamid Bin Yousuf, Masud H. Chowdhury
2018	—	`conf`	Novel CNTFET and Memristor based Unbalanced Ternary Logic Gate. MWSCAS Mahmood Uddin Mohammed, Rakesh Vijjapuram, Masud H. Chowdhury
2018	J	`jnl`	Reliability and Energy Efficiency of the Tunneling Transistor-Based 6T SRAM Cell in Sub-10 nm Domain. IEEE Trans. Circuits Syst. II Express Briefs Mahmood Uddin Mohammed, Masud H. Chowdhury
2018	—	`conf`	Ternary Device using Graphene Memcapacitor for Post Binary Era. MWSCAS Jill Arvindbhai Patel, Zarin Tasnim Sandhie, Masud H. Chowdhury
2017	J	`jnl`	Analysis of device capacitance and subthreshold behavior of Tri-gate SOI FinFET. Microelectron. J. Azzedin D. Es-Sakhi, Masud H. Chowdhury
2017	J	`jnl`	Analytical Models of High-Speed RLC Interconnect Delay for Complex and Real Poles. IEEE Trans. Very Large Scale Integr. Syst. Muhammad Sana Ullah, Masud H. Chowdhury
2017	—	`conf`	BPSK modulation based exact BER computation for network intra-chip RF interconnect. ICM Muhammad Sana Ullah, Abdullah G. Alharbi, Masud H. Chowdhury
2017	J	`jnl`	Editorial. IEEE Trans. Very Large Scale Integr. Syst. Krishnendu Chakrabarty, Massimo Alioto, Bevan M. Baas, Chirn Chye Boon, Meng-Fan Chang, Naehyuck Chang, Yao-Wen Chang, Chip-Hong Chang, Shih-Chieh Chang, Poki Chen, Masud H. Chowdhury, Pasquale Corsonello, Ibrahim Abe M. Elfadel, Said Hamdioui, Masanori Hashimoto, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Rajiv V. Joshi, Tanay Karnik, Mehran Mozaffari Kermani, Chulwoo Kim, Tae-Hyoung Kim, Jaydeep P. Kulkarni, Eren Kursun, Erik Larsson, Hai (Helen) Li, Huawei Li, Patrick P. Mercier, Prabhat Mishra, Makoto Nagata, Arun S. Natarajan, Koji Nii, Partha Pratim Pande, Ioannis Savidis, Mingoo Seok, Sheldon X.-D. Tan, Mark Tehranipoor, Aida Todri-Sanial, Miroslav N. Velev, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Stacey Weber Jackson
2017	J	`jnl`	Electrical Nonlinearity Emulation Technique for Current-Controlled Memristive Devices. IEEE Access Abdullah G. Alharbi, Mohammed E. Fouda, Zainulabideen J. Khalifa, Masud H. Chowdhury
2017	—	`conf`	Emerging STT-MRAM circuit and architecture co-design in 45nm technology. MWSCAS Lohith Kumar Vemula, Nahid M. Hossain, Masud H. Chowdhury
2017	—	`conf`	Error free sense amplifier circuit design for STT-MRAM nonvolatile memory. MWSCAS Lohith Kumar Vemula, Nahid M. Hossain, Masud H. Chowdhury
2017	C	`conf`	Impacts of different shapes of through-silicon-via core on 3D IC performance. ISCAS Abdul Hamid Bin Yousuf, Nahid M. Hossain, Masud H. Chowdhury
2017	—	`conf`	Multilayer graphene nanoribbon based BioFET sensor design. MWSCAS Nahid M. Hossain, Emeshaw Ashenafi, Moqbull Hossen, Azzedin D. Es-Sakhi, Masud H. Chowdhury
2017	C	`conf`	Nodal thermal analysis for multi-VT SOFFET based subthreshold circuits. ISCAS Emeshaw Ashenafi, Azzedin D. Es-Sakhi, Masud H. Chowdhury
2017	C	`conf`	Noise voltage analysis of spiral inductor for on-chip buck converter design. ISCAS Emeshaw Ashenafi, Masud H. Chowdhury
2017	—	`conf`	Optimization of subthreshold swing for multilayer MoS2 tunnel transistor. MWSCAS Muhammad Sana Ullah, Masud H. Chowdhury
2017	—	`conf`	Tunneling transistor based 6T SRAM bitcell circuit design in sub-10nm domain. MWSCAS Nahid M. Hossain, Arif Iqbal, Hemanshu Shishupal, Masud H. Chowdhury
2016	J	`jnl`	Comprehensive doping scheme for MOSFETs in ultra-low-power subthreshold circuits design. Microelectron. J. MunEm Hossain, Masud H. Chowdhury
2016	C	`conf`	Detection of biochemical molecules using CM-SOFFET based biosensor. ISCAS Emeshaw Ashenafi, Azzedin D. Es-Sakhi, Masud H. Chowdhury
2016	—	`conf`	Innovative device source/drain and channel implantation for MOS transistors in ultra low power subthreshold circuit applications. NEWCAS MunEm Hossain, Masud H. Chowdhury
2016	—	`conf`	Low voltage Flash memory design based on floating gate SOFFET. SoCC Emeshaw Ashenafi, Azzedin D. Es-Sakhi, Masud H. Chowdhury
2016	—	`conf`	Simple generic memristor emulator for voltage-controlled models. MWSCAS Abdullah G. Alharbi, Mohammed E. Fouda, Zainulabideen J. Khalifa, Masud H. Chowdhury
2015	—	`conf`	A new simple emulator circuit for current controlled memristor. ICECS Abdullah G. Alharbi, Zainulabideen J. Khalifa, Mohamed E. Fouda, Masud H. Chowdhury
2015	—	`conf`	A novel memristor emulator based only on an exponential amplifier and CCII+. ICECS Abdullah G. Alharbi, Mohamed E. Fouda, Masud H. Chowdhury
2015	C	`conf`	Analysis of radiation effect on the threshold voltage of flash memory device. ISCAS Nahid M. Hossain, Jitendra Koppu, Masud H. Chowdhury
2015	C	`conf`	Analysis of subthreshold swing in multichannel tunneling carbon nanotube field effect transistor (MT-CNTFET). ISCAS Azzedin D. Es-Sakhi, Masud H. Chowdhury
2015	—	`conf`	Analytical analysis of the contact resistance (Rc) of metal-MoS2 interface. MWSCAS MunEm Hossain, Muhammad Sana Ullah, Abdul Hamid Bin Yousuf, Azzedin Es-Saki, Masud H. Chowdhury
2015	—	`conf`	Current voltage characteristics of Partially Depleted Silicon on Ferroelectric Insulator Field Effect Transistor (PD-SOFFET). MWSCAS Azzedin D. Es-Sakhi, Masud H. Chowdhury
2015	—	`conf`	High-speed graphene based quantum-optical interconnect design. MWSCAS Ritesh Chowdri, Nahid M. Hossain, Masud H. Chowdhury
2015	J	`jnl`	Improved Model for Wire-Length Estimation in Stochastic Wiring Distribution. CoRR Mohamed S. Hefeida, Masud H. Chowdhury
2015	—	`conf`	Memristor emulator based on practical current controlled model. MWSCAS Abdullah G. Alharbi, Mohammed E. Fouda, Masud H. Chowdhury
2015	—	`conf`	Memristor emulator based on single CCII. ICM Abdullah G. Alharbi, Zainulabideen J. Khalifa, Mohammed E. Fouda, Masud H. Chowdhury
2015	J	`jnl`	Multilayer Graphene Nanoribbon and Carbon Nanotube Based Floating Gate Transistor for Nonvolatile Flash Memory. ACM J. Emerg. Technol. Comput. Syst. Nahid M. Hossain, Masud H. Chowdhury
2015	C	`conf`	Multilayer molybdenum disulfide (MoS2) based tunnel transistor. ISCAS Muhammad Sana Ullah, Masud H. Chowdhury
2015	—	`conf`	New three dimensional doping profile for devices in subthreshold circuit. MWSCAS MunEm Hossain, Masud H. Chowdhury
2015	—	`conf`	Optimization of ON current in multilayer Molybdenum Disulfide (MoS2) based tunnel field effect transistor. MWSCAS Muhammad Sana Ullah, Masud H. Chowdhury
2015	J	`jnl`	Partially Depleted Silicon-on-Ferroelectric Insulator Field Effect Transistor- Parametrization & Design Optimization for Minimum Subthreshold Swing. Microelectron. J. Azzedin D. Es-Sakhi, Masud H. Chowdhury
2015	—	`conf`	Partially depleted silicon-on-ferroelectric insulator field effect transistor (PD-SOFFET). ISQED Azzedin D. Es-Sakhi, Masud H. Chowdhury
2015	C	`conf`	Performance analysis of through silicon via (TSV) and through glass via (TGV) for different materials. ISCAS Abdul Hamid Bin Yousuf, Nahid M. Hossain, Masud H. Chowdhury
2015	—	`conf`	Subthreshold swing characteristics of multilayer MoS2 tunnel FET. MWSCAS Muhammad Sana Ullah, Masud H. Chowdhury
2014	—	`conf`	A new real pole delay model for RLC interconnect using second order approximation. MWSCAS Muhammad Sana Ullah, Masud H. Chowdhury
2014	C	`conf`	Analysis of RLC interconnect delay model using second order approximation. ISCAS Muhammad Sana Ullah, Masud H. Chowdhury
2014	—	`conf`	Analysis of the current-voltage characteristics of Silicon on Ferroelectric Insulator Field Effect Transistor (SOF-FET). SoCC Azzedin D. Es-Sakhi, Masud H. Chowdhury
2014	—	`conf`	Graphene and CNT based flash memory: Impacts of scaling control and tunnel oxide thickness. MWSCAS Nahid M. Hossain, Masud H. Chowdhury
2014	—	`conf`	Multichannel Tunneling Carbon Nanotube Field Effect Transistor (MT-CNTFET). SoCC Azzedin D. Es-Sakhi, Masud H. Chowdhury
2014	C	`conf`	Multilayer graphene nanoribbon floating gate transistor for flash memory. ISCAS Nahid M. Hossain, Masud H. Chowdhury
2014	—	`conf`	Multilayer layer graphene nanoribbon flash memory: Analysis of programming and erasing operation. SoCC Nahid M. Hossain, Md Belayat Hossain, Masud H. Chowdhury
2014	—	`conf`	Neural network based classification of stressed speech using nonlinear spectral and cepstral features. NEWCAS Muhammad Sana Ullah, Masud H. Chowdhury
2014	—	`conf`	Transistor doping profile optimization for low power subthreshold circuits. MWSCAS MunEm Hossain, Masud H. Chowdhury
2013	—	`conf`	Active on-chip voltage regulator based on second generation current conveyor. ICECS Emeshaw Ashenafi, Masud H. Chowdhury
2013	—	`conf`	Analysis of the properties of ZnO nanoparticle for emerging applications in nanoscale domains. MWSCAS Md Nahid Hossain, Masud H. Chowdhury, Md. Jahidul Islam, Tajmeri Selina Akhter
2013	—	`conf`	Analytical model to estimate the subthreshold swing of SOI FinFET. ICECS Azzedin D. Es-Sakhi, Masud H. Chowdhury
2013	—	`conf`	Heat transfer simulations for pulsed laser annealing of silicon thin film. MWSCAS MunEm Hossain, Masud H. Chowdhury
2013	—	`conf`	Implementation of active floating inductor based on second generation current conveyor for on chip voltage regulator. MWSCAS Emeshaw Ashenafi, Masud H. Chowdhury
2013	—	`conf`	Silicon on ferroelectric insulator field effect transistor (SOF-FET) for ultra low power design. MWSCAS Azzedin D. Es-Sakhi, Masud H. Chowdhury
2013	—	`conf`	Thermal aware Graphene based Through Silicon Via design for 3D IC. 3DIC Nahid M. Hossain, MunEm Hossain, Abdul Hamid Bin Yousuf, Masud H. Chowdhury
2012	C	`conf`	Exploiting negative quantum capacitance of carbon nanotube FETs for low power applications. ISCAS Md. Sajjad Rahaman, Masud H. Chowdhury
2012	—	`conf`	On-chip voltage regulator without physical inductor. NEWCAS Md. Tanim Humayun, Juliana Gjanci, Masud H. Chowdhury
2011	J	`jnl`	A Hybrid Scheme for On-Chip Voltage Regulation in System-On-a-Chip (SOC). IEEE Trans. Very Large Scale Integr. Syst. Juliana Gjanci, Masud H. Chowdhury
2011	C	`conf`	A circuit implementation for dynamic thermal management techniques. ISCAS Pritesh Vora, Masud H. Chowdhury
2011	C	`conf`	Addressing crosstalk issue in on-chip carbon nanotube interconnects using negative capacitance. ISCAS Md. Khaled Hassan, Md. Sajjad Rahaman, Masud H. Chowdhury
2011	J	`jnl`	An Innovative Power-Gating Technique for Leakage and Ground Bounce Control in System-on-a-Chip (SOC). Circuits Syst. Signal Process. Masud H. Chowdhury, Pervez Khaled, Juliana Gjanci
2011	J	`jnl`	Fast Waveform Estimation (FWE) for Timing Analysis. IEEE Trans. Very Large Scale Integr. Syst. Jingye Xu, Masud H. Chowdhury
2011	C	`conf`	Spatial- and temporal-reliability aware design for nano-scale VLSI circuits. ISCAS Md. Sajjad Rahaman, Qing Duan, Masud H. Chowdhury
2010	J	`jnl`	Analysis of the Impacts of Signal Slew and Skew on the Behavior of Coupled RLC Interconnects for Different Switching Patterns. IEEE Trans. Very Large Scale Integr. Syst. Abinash Roy, Jingye Xu, Masud H. Chowdhury
2010	J	`jnl`	Energy efficiency of error control coding in intra-chip RF/wireless interconnect systems. Microelectron. J. Md. Sajjad Rahaman, Masud H. Chowdhury
2009	—	`ed.`	CSIE 2009, 2009 WRI World Congress on Computer Science and Information Engineering, March 31 - April 2, 2009, Los Angeles, California, USA, 7 Volumes CSIE Mark Burgin, Masud H. Chowdhury, Chan H. Ham, Simone A. Ludwig, Weilian Su, Sumanth Yenduri
2009	C	`conf`	Crosstalk Avoidance and Error-correction Coding for Coupled RLC Interconnects. ISCAS Md. Sajjad Rahaman, Masud H. Chowdhury
2009	J	`jnl`	Investigation and a practical compact network model of thermal stress in integrated circuits. Integr. Comput. Aided Eng. Shriram Krishnamoorthy, Masud H. Chowdhury
2009	—	`conf`	VSIB: A Sensor Bus Architecture for Smart-Sensor Network. CSIE (3) Md. Sajjad Rahaman, Masud H. Chowdhury, Irfan Nasir, Lih-Tyng Hwang
2008	C	`conf`	Analysis of the impacts of signal rise/fall time and skew variations in coupled-RLC interconnects. ISCAS Abinash Roy, Masud H. Chowdhury
2008	—	`conf`	BER performance comparison between CDMA and UWB for RF/wireless interconnect application. EIT Md. Sajjad Rahaman, Masud H. Chowdhury
2008	—	`conf`	Compact thermal network model: Realization and reduction. EIT Shriram Krishnamoorthy, Masud H. Chowdhury
2008	J	`jnl`	Compound noise separation in digital circuits using blind source separation. Microelectron. J. Jingye Xu, Vivek Nigam, Abinash Roy, Masud H. Chowdhury
2008	—	`conf`	Controlling Ground Bounce Noise in Power Gating Scheme for System-on-a-Chip. ISVLSI Masud H. Chowdhury, Juliana Gjanci, Pervez Khaled
2008	—	`conf`	Fast bus waveform estimation at the presence of coupling noise. ACM Great Lakes Symposium on VLSI Jingye Xu, Pervez Khaled, Masud H. Chowdhury
2008	C	`conf`	Full waveform accuracy to estimate delay in coupled digital circuits. ISCAS Jingye Xu, Pervez Khaled, Masud H. Chowdhury
2008	—	`conf`	Impacts of signal slew and skew variations on delay uncertainty and crosstalk noise in coupled RLC global interconnects. ICECS Abinash Roy, Jingye Xu, Masud H. Chowdhury
2008	—	`conf`	Improved ber performance in intra-chip rf/wireless interconnect systems. ACM Great Lakes Symposium on VLSI Md. Sajjad Rahaman, Masud H. Chowdhury
2008	C	`conf`	Innovative power gating for leakage reduction. ISCAS Masud H. Chowdhury, Juliana Gjanci, Pervez Khaled
2008	J	`jnl`	Noise separation in analog integrated circuits using independent component analysis technique. Integr. Comput. Aided Eng. Jingye Xu, Abinash Roy, Masud H. Chowdhury
2008	C	`conf`	Optimization technique for flip-flop inserted global interconnect. ISCAS Jingye Xu, Abinash Roy, Masud H. Chowdhury
2008	C	`conf`	Time diversity approach for intra-chip RF/wireless interconnect systems. ISCAS Md. Sajjad Rahaman, Masud H. Chowdhury
2007	—	`conf`	Accurate Analysis of Switching Patterns in High Speed On-chip Global Interconnects. ICECS Abinash Roy, Sharada Jha, Masud H. Chowdhury
2007	—	`conf`	Accurate Delay Estimation in the Presence of Coupling Noise using Complete Waveform Accuracy. ICECS Jingye Xu, Masud H. Chowdhury
2007	—	`conf`	Analysis of Spatial Temperature Distribution in ICs. ICECS Shriram Krishnamoorthy, Masud H. Chowdhury
2007	C	`conf`	Delay and Clock Skew Variation due to Coupling Capacitance and Inductance. ISCAS Abinash Roy, Noha H. Mahmoud, Masud H. Chowdhury
2007	A*	`conf`	Effects of Coupling Capacitance and Inductance on Delay Uncertainty and Clock Skew. DAC Abinash Roy, Noha H. Mahmoud, Masud H. Chowdhury
2007	C	`conf`	Global Interconnect Optimization in the Presence of On-chip Inductance. ISCAS Abinash Roy, Masud H. Chowdhury
2007	A	`conf`	Interactive presentation: Analysis of power consumption and BER of flip-flop based interconnect pipelining. DATE Jingye Xu, Abinash Roy, Masud H. Chowdhury
2007	—	`conf`	Multi-Carrier CDMA-Interconnect for Inter- and Intra-ULSI Communications. ICECS Md. Sajjad Rahaman, Masud H. Chowdhury
2007	C	`conf`	Power Consumption Analysis of Flip-flop Based Interconnect Pipelining. ISCAS Jingye Xu, Abinash Roy, Masud H. Chowdhury
2007	J	`jnl`	Power Consumption and BER of Flip-Flop Inserted Global Interconnect. VLSI Design Jingye Xu, Abinash Roy, Masud H. Chowdhury
2006	—	`conf`	Bit Error Rate Analysis for Flip-flop and Latch Based Interconnect Pipelining. ICECS Jingye Xu, Masud H. Chowdhury
2006	C	`conf`	Compound noise analysis in digital circuits using blind source separation. ISCAS Vivek Nigam, Masud H. Chowdhury, Roland Priemer
2006	—	`conf`	Impacts of Inductance on the Figures of Merit to Optimize Global Interconnect. APCCAS Abinash Roy, Masud H. Chowdhury
2006	—	`conf`	Optical Interconnect Technology; Photons Based Signal Communication. APCCAS Geetanjali Kshirsagar, Masud H. Chowdhury
2006	—	`conf`	Prospects and Challenges of Handling Power Bus Modeling and Supply Noise in Package-Chip C0-design Approach. APCCAS Pervez Khaled, Masud H. Chowdhury
2006	J	`jnl`	Realistic scalability of noise in dynamic circuits. IEEE Trans. Very Large Scale Integr. Syst. Masud H. Chowdhury, Yehea I. Ismail
2006	—	`conf`	Separation of Individual Noise Sources from Compound Noise Measurements in Digital Circuits. APCCAS Vivek Nigam, Masud H. Chowdhury, Roland Priemer
2006	—	`conf`	Simultaneous Analysis of Capacitive Coupling and Leakage Noise in Nanometer Scale Circuits. APCCAS Chuen M. Tan, Masud H. Chowdhury
2005	A	`conf`	Engineering Over-Clocking: Reliability-Performance Trade-Offs for High-Performance Register Files. DSN Gokhan Memik, Masud H. Chowdhury, Arindam Mallik, Yehea I. Ismail
2005	J	`jnl`	Realizable reduction of interconnect circuits including self and mutual inductances. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chirayu S. Amin, Masud H. Chowdhury, Yehea I. Ismail
2004	—	`conf`	Analysis of coupling noise and it's scalability in dynamic circuits [dynamic logic CMOS ICs]. CICC Masud H. Chowdhury, Yehea I. Ismail
2004	—	`conf`	Possible Noise Failure Modes in Static and Dynamic Circuits. IWSOC Masud H. Chowdhury, Yehea I. Ismail
2003	—	`conf`	Analysis of Coupling Noise in Dynamic Circuit. IWSOC Masud H. Chowdhury, Yehea I. Ismail
2003	A*	`conf`	Realizable RLCK circuit crunching. DAC Chirayu S. Amin, Masud H. Chowdhury, Yehea I. Ismail
2003	—	`conf`	Realizable reduction of RLC circuits using node elimination. ISCAS (3) Masud H. Chowdhury, Chirayu S. Amin, Yehea I. Ismail, Chandramouli V. Kashyap, Byron Krauter
2002	—	`conf`	Performance analysis of deep sub micron VLSI circuits in the presence of self and mutual inductance. ISCAS (4) Masud H. Chowdhury, Yehea I. Ismail, Chandramouli V. Kashyap, Byron Krauter