Massimo Pozzoni

13 papers Journal 5Unranked 8
YearRankTypeTitle / Venue / Authors
2019 J jnl
A 64 Gb/s Low-Power Transceiver for Short-Reach PAM-4 Electrical Links in 28-nm FDSOI CMOS.
IEEE J. Solid State Circuits
Emanuele Depaoli, Hongyang Zhang, Marco Mazzini, Walter Audoglio, Augusto Andrea Rossi, Guido Albasini, Massimo Pozzoni, Simone Erba, Enrico Temporiti, Andrea Mazzanti
2018 — conf
A 4.9pJ/b 16-to-64Gb/s PAM-4 VSR transceiver in 28nm FDSOI CMOS.
ISSCC
Emanuele Depaoli, Enrico Monaco, Giovanni Steffan, Marco Mazzini, Hongyang Zhang, Walter Audoglio, Oscar Belotti, Augusto Andrea Rossi, Guido Albasini, Massimo Pozzoni, Simone Erba, Andrea Mazzanti
2013 — conf
A 6-bit 6-GS/s 95mW background calibrated flash ADC with integrating preamplifiers and half-rate comparators in 32nm LP CMOS.
ESSCIRC
Francesco Radice, Melchiorre Bruccoleri, Marcello Ganzerli, Giorgio Spelgatti, Davide Sanzogni, Massimo Pozzoni, Andrea Mazzanti
2011 J jnl
A Wideband Receiver for Multi-Gbit/s Communications in 65 nm CMOS.
IEEE J. Solid State Circuits
Federico Vecchi, Stefano Bozzola, Enrico Temporiti, Davide Guermandi, Massimo Pozzoni, Matteo Repossi, Marco Cusmai, Ugo Decanis, Andrea Mazzanti, Francesco Svelto
2010 — conf
A 12Gb/s 39dB loss-recovery unclocked-DFE receiver with bi-dimensional equalization.
ISSCC
Massimo Pozzoni, Simone Erba, Davide Sanzogni, Marcello Ganzerli, Paolo Viola, Daniele Baldi, Matteo Repossi, Giorgio Spelgatti, Francesco Svelto
2010 — conf
A 13.1% tuning range 115GHz frequency generator based on an injection-locked frequency doubler in 65nm CMOS.
ISSCC
Andrea Mazzanti, Enrico Monaco, Massimo Pozzoni, Francesco Svelto
2010 — conf
A wideband mm-Wave CMOS receiver for Gb/s communications employing interstage coupled resonators.
ISSCC
Federico Vecchi, Stefano Bozzola, Massimo Pozzoni, Davide Guermandi, Enrico Temporiti, Matteo Repossi, Ugo Decanis, Andrea Mazzanti, Francesco Svelto
2010 J jnl
Injection-Locked CMOS Frequency Doublers for μ -Wave and mm-Wave Applications.
IEEE J. Solid State Circuits
Enrico Monaco, Massimo Pozzoni, Francesco Svelto, Andrea Mazzanti
2009 J jnl
A Multi-Standard 1.5 to 10 Gb/s Latch-Based 3-Tap DFE Receiver With a SSC Tolerant CDR for Serial Backplane Communication.
IEEE J. Solid State Circuits
Massimo Pozzoni, Simone Erba, Paolo Viola, Matteo Pisati, Emanuele Depaoli, Davide Sanzogni, Riccardo Brama, Daniele Baldi, Matteo Repossi, Francesco Svelto
2009 — conf
A sliding IF receiver for mm-wave WLANs in 65nm CMOS.
CICC
Stefano Bozzola, Davide Guermandi, Federico Vecchi, Matteo Repossi, Massimo Pozzoni, Andrea Mazzanti, Francesco Svelto
2008 — conf
A 10Gb/s receiver with linear backplane equalization and mixer-based self-aligned CDR.
CICC
Simone Erba, Massimo Pozzoni, Matteo Pisati, Riccardo Brama, Davide Sanzogni, Emanuele Depaoli, Paolo Viola, Francesco Svelto
2005 J jnl
A 10-Gb/s CMU/CDR chip-set in SiGe BiCMOS commercial technology with multistandard capability.
IEEE Trans. Very Large Scale Integr. Syst.
Francesco Centurelli, Alessandro Golfarelli, Jesus Guinea, Leonardo Masini, Damiana Morigi, Massimo Pozzoni, Giuseppe Scotti, Alessandro Trifiletti
2004 — conf
A high-speed low-voltage phase detector for clock recovery from NRZ data.
ISCAS (4)
Francesco Centurelli, Massimo Pozzoni, Giuseppe Scotti, Alessandro Trifiletti