Massimo Poli

26 papers C 4Journal 8Unranked 13
YearRankTypeTitle / Venue / Authors
2011 J jnl
Optimized design of parallel carry-select adders.
Integr.
Massimo Alioto, Gaetano Palumbo, Massimo Poli
2010 J jnl
A General Power Model of Differential Power Analysis Attacks to Static Logic Circuits.
IEEE Trans. Very Large Scale Integr. Syst.
Massimo Alioto, Massimo Poli, Santina Rocchi
2010 J jnl
Differential Power Analysis Attacks to Precharged Buses: A General Analysis for Symmetric-Key Cryptographic Algorithms.
IEEE Trans. Dependable Secur. Comput.
Massimo Alioto, Massimo Poli, Santina Rocchi
2010 J jnl
Simple and accurate modeling of the output transition time in nanometer CMOS gates.
Int. J. Circuit Theory Appl.
Massimo Alioto, Gaetano Palumbo, Massimo Poli
2009 J jnl
Analysis and Modeling of Energy Consumption in RLC Tree Circuits.
IEEE Trans. Very Large Scale Integr. Syst.
Massimo Alioto, Gaetano Palumbo, Massimo Poli
2008 C conf
A general model for differential power analysis attacks to static logic circuits.
ISCAS
Massimo Alioto, Massimo Poli, Santina Rocchi
2008 — conf
Energy evaluation in RLC tree circuits with exponential input.
ICECS
Massimo Alioto, Gaetano Palumbo, Massimo Poli
2008 C conf
Explicit energy evaluation in RLC tree circuits with ramp inputs.
ISCAS
Massimo Alioto, Massimo Poli, Gaetano Palumbo
2007 — conf
A General Model of DPA Attacks to Precharged Busses in Symmetric-Key Cryptographic Algorithms.
ECCTD
Massimo Alioto, Massimo Poli, Santina Rocchi, Valerio Vignoli
2007 — conf
Efficient and Accurate Models of Output Transition Time in CMOS Logic.
ICECS
Massimo Alioto, Massimo Poli, Gaetano Palumbo
2007 — conf
Energy consumption in RLC tree circuits.
ECCTD
Massimo Alioto, Gaetano Palumbo, Massimo Poli
2007 C conf
Mixed Techniques to Protect Precharged Busses against Differential Power Analysis Attacks.
ISCAS
Massimo Alioto, Massimo Poli, Santina Rocchi, Valerio Vignoli
2007 J jnl
Propagation Delay of an
IEEE Trans. Circuits Syst. II Express Briefs
Rosario Mita, Gaetano Palumbo, Massimo Poli
2007 — conf
System-Level Design for Nano-Electronics.
ICECS
David Atienza, Shashikanth Bobba, Massimo Poli, Giovanni De Micheli, Luca Benini
2006 C conf
Efficient output transition time modeling in CMOS gates with ramp/exponential inputs.
ISCAS
Massimo Alioto, Gaetano Palumbo, Massimo Poli
2006 J jnl
Energy Consumption in RC Tree Circuits.
IEEE Trans. Very Large Scale Integr. Syst.
Massimo Alioto, Gaetano Palumbo, Massimo Poli
2006 — —
Modellazione dinamica ed energetica delle reti RC nei sistemi VLSI.
Massimo Poli
2006 — conf
Power Modeling of Precharged Address Bus and Application to Multi-bit DPA Attacks to DES Algorithm.
PATMOS
Massimo Alioto, Massimo Poli, Santina Rocchi, Valerio Vignoli
2006 — conf
RC-Chain: a Simple Model of Delay with a Ramp Input.
ICECS
Giuseppe Di Cataldo, Rosario Mita, Gaetano Palumbo, Massimo Poli
2006 — conf
Techniques to Enhance the Resistance of Precharged Busses to Differential Power Analysis.
PATMOS
Massimo Alioto, Massimo Poli, Santina Rocchi, Valerio Vignoli
2005 — conf
Energy Consumption in RC Tree Circuits with Exponential Inputs: An Analytical Model.
PATMOS
Massimo Alioto, Gaetano Palumbo, Massimo Poli
2004 — conf
A gate-level strategy to design Carry Select Adders.
ISCAS (2)
Massimo Alioto, Gaetano Palumbo, Massimo Poli
2004 J jnl
Evaluation of energy consumption in RC ladder circuits driven by a ramp input.
IEEE Trans. Very Large Scale Integr. Syst.
Massimo Alioto, Gaetano Palumbo, Massimo Poli
2002 — conf
A novel pseudo random bit generator for cryptography applications.
ICECS
Rosario Mita, Gaetano Palumbo, Salvatore Pennisi, Massimo Poli
2002 — conf
An Approach to Energy Consumption Modeling in RC Ladder Circuits.
PATMOS
Massimo Alioto, Gaetano Palumbo, Massimo Poli
2002 — conf
Propagation delay model of current driven RC chain.
ICECS
Gaetano Palumbo, Massimo Poli