Massimo Bombana

14 papers A* 1A 2C 1Journal 3Unranked 7
YearRankTypeTitle / Venue / Authors
2004 A conf
A Design Methodology for the Exploitation of High Level Communication Synthesis.
DATE
Francesco Bruschi, Massimo Bombana
2003 A conf
SystemC-VHDL Co-Simulation and Synthesis in the HW Domain.
DATE
Massimo Bombana, Francesco Bruschi
2000 J jnl
A Case Study in Design Space Exploration: The Tosca Environment Applied to a Telecommunication Link Controller.
IEEE Des. Test Comput.
Alberto Allara, Massimo Bombana, William Fornaciari, Fabio Salice
1998 — conf
ATM Cell Modelling using Objective VHDL.
ASP-DAC
Alberto Allara, Massimo Bombana, Patrizia Cavalloro, Wolfgang Nebel, Wolfram Putzke-Röming, Martin Radetzki
1998 — conf
IP-based design of custom field programmable network processors.
ICECS
Massimo Bombana, Nikolay Fominykh, Giulio Gorla, Alexander Kriajev, Boris Krivosheyin, Juri Rytchagov
1997 — conf
Property verification in the design of telecom applications.
ASP-DAC
Massimo Bombana, Patrizia Cavalloro, Fabrizio Ferrandi
1995 A* conf
Design-Flow and Synthesis for ASICs: A Case Study.
DAC
Massimo Bombana, Patrizia Cavalloro, Salvatore Conigliaro, Roger B. Hughes, Gerry Musgrave, Giuseppe Zaza
1994 J jnl
ALADIN: a multilevel testability analyzer for VLSI system design.
IEEE Trans. Very Large Scale Integr. Syst.
Massimo Bombana, Giacomo Buonanno, Patrizia Cavalloro, Fabrizio Ferrandi, Donatella Sciuto, Giuseppe Zaza
1994 — conf
Quantitative Evaluation of Formal Based Synthesis in ASIC Design.
TPCD
G. Bezzi, Massimo Bombana, Patrizia Cavalloro, Salvatore Conigliaro, Giuseppe Zaza
1993 J jnl
A design methodology for the correct specification of VLSI systems.
Microprocess. Microprogramming
Cristiana Bolchini, Massimo Bombana, Patrizia Cavalloro, Claudio Costi, Franco Fummi, Giuseppe Zaza
1993 C conf
An Expert Solution to Functional Testability Analysis of VLSI Circuits.
SEKE
Massimo Bombana, Giacomo Buonanno, Patrizia Cavalloro, Fabrizio Ferrandi, Donatella Sciuto, Giuseppe Zaza
1993 — conf
Reduction of Fault Detection Costs through Testable Design of Sequential Architectures with Signal Feedbacks.
DFT
Massimo Bombana, Giacomo Buonanno, Patrizia Cavalloro, Fabrizio Ferrandi, Donatella Sciuto, Giuseppe Zaza
1992 — conf
A multi level testability assistant for VLSI design.
EURO-DAC
Massimo Bombana, Giacomo Buonanno, Patrizia Cavalloro, Donatella Sciuto, Giuseppe Zaza
1992 — conf
Specification and Formal Synthesis of Digital Circuits.
TPHOLs
Massimo Bombana, Patrizia Cavalloro, Giuseppe Zaza