Massimo Alioto

321 papers A* 1A 2C 52Misc 2Journal 133Unranked 129
YearRankTypeTitle / Venue / Authors
2026 — conf
35.5 Fully Integrated Backscattered WiFi 802.11b Transmitter with Active Harmonics and Image Rejection for 30dB IRR and 36dB HRR at ${0. 8 8} {\mu} \mathrm{W}$.
ISSCC
Ruiyuan Yang, Karim Ali, Massimo Alioto
2026 — conf
Highly-Integrated Light-Sensing System with RF Harvesting and Transmission in Commercial N-Type IGZO Flexible Technology.
ISSCC
Marco Privitera, Muhammad Zahid Naveed, Andrea Ballo, Gianluca Giustolisi, Alfio Dario Grasso, Massimo Alioto
2026 J jnl
Laser Voltage Probing Attack Detection via Leakage Shift Monitoring Without Dedicated Sensors at 4.35% Area Overhead.
IEEE J. Solid State Circuits
Hui Zhang, Longyang Lin, Dingyi Xiong, Massimo Alioto
2026 J jnl
SRAM Static Entropy Extraction From Every Single Transistor in Unmodified Bitcell and Data Fingerprinting for Provenance Assurance.
IEEE J. Solid State Circuits
Tianqi Wang, Joydeep Basu, Viveka Konandur Rajanna, Massimo Alioto
2026 J jnl
Two-Stage Inverter-Based OTA With 56-dB Gain and Digitally Reconfigurable GBW/SR for PVT-Resiliency.
IEEE Trans. Circuits Syst. I Regul. Pap.
Riccardo Della Sala, Marco Privitera, Giuseppe Scotti, Alfio Dario Grasso, Massimo Alioto
2025 — conf
${\mathrm{V}}_{\text {DD }}$-Scalable and Reference-Less Body-Biased Inverter-Based OTA Exploiting Improved Composite Transistors for ULV/ULP Applications.
NewCAS
Marco Privitera, Luis Henrique Radovalho, Orazio Aiello, Alfio Dario Grasso, Massimo Alioto
2025 J jnl
0.4-V nW-Power High-Gain Bulk-Driven Two-Stage OTA With Self-Cascode Composite Transistors and Intrinsic Current-Buffer Miller Compensation.
IEEE Trans. Circuits Syst. I Regul. Pap.
Muhammad Omer Shah, Marco Privitera, Andrea Ballo, Massimo Alioto, Salvatore Pennisi
2025 J jnl
Never Compromise to Vulnerabilities: A Comprehensive Survey on AI Governance.
CoRR
Yuchu Jiang, Jian Zhao, Yuchen Yuan, Tianle Zhang, Yao Huang, Yanghao Zhang, Yan Wang, Yanshu Li, Xizhong Guo, Yusheng Zhao, Jun Zhang, Zhi Zhang, Xiaojian Lin, Yixiu Zou, Haoxuan Ma, Yuhu Shang, Yuzhi Hu, Keshu Cai, Ruochen Zhang, Boyuan Chen, Yilan Gao, Ziheng Jiao, Yi Qin, Shuangjun Du, Xiao Tong, Zhekun Liu, Yu Chen, Xuankun Rong, Rui Wang, Yejie Zheng, Zhaoxin Fan, Murat Sensoy, Hongyuan Zhang, Pan Zhou, Lei Jin, Hao Zhao, Xu Yang, Jiaojiao Zhao, Jianshu Li, Joey Tianyi Zhou, Zhi-Qi Cheng, Longtao Huang, Zhiyi Liu, Zheng Zhu, Jianan Li, Gang Wang, Qi Li, Xu-Yao Zhang, Yaodong Yang, Mang Ye, Wenqi Ren, Zhaofeng He, Hang Su, Rongrong Ni, Liping Jing, Xingxing Wei, Junliang Xing, Massimo Alioto, Shengmei Shen, Petia Radeva, Dacheng Tao, Ya-Qin Zhang, Shuicheng Yan, Chi Zhang, Zhongjiang He, Xuelong Li
2025 — conf
On-Chip Circuit Harness Enabling Probe-Less, Position-Invariant and Massive Testing of Chiplets via Die Front/Back-Side Capacitive Coupling.
CICC
Neelkamal Semwal, Luigi Fassio, Massimo Alioto
2025 J jnl
Sub- μ W Battery-Less and Oscillator-Less Wi-Fi Backscattering Transmitter Reusing RF Signal for Harvesting, Communications, and Motion Detection.
CoRR
Marco Privitera, Andrea Ballo, Karim Ali Ahmed, Alfio Dario Grasso, Massimo Alioto
2025 J jnl
Sub- μ W Battery-Less and Oscillator-Less Wi-Fi Backscattering Transmitter Reusing RF Signal for Harvesting, Communications, and Motion Detection.
IEEE J. Solid State Circuits
Marco Privitera, Andrea Ballo, Karim Ali, Alfio Dario Grasso, Massimo Alioto
2024 — conf
122.7 TOPS/W Stdcell-Based DNN Accelerator Based on Transition Density Data Representation, Clock-Less MAC Operation, Pseudo-Sparsity Exploitation in 40 nm.
VLSI Technology and Circuits
Animesh Gupta, Japesh Vohra, Viveka Konandur Rajanna, Massimo Alioto
2024 — conf
6.3 Imager with In-Sensor Event Detection and Morphological Transformations with 2.9pJ/pixel×frame Object Segmentation FOM for Always-On Surveillance in 40nm.
ISSCC
Japesh Vohra, Animesh Gupta, Massimo Alioto
2024 C conf
A 15-nA quiescent current capacitor-less LDO for sub-1V μW-powered fully-harvested systems.
ISCAS
Marco Privitera, Andrea Ballo, Alfio Dario Grasso, Massimo Alioto
2024 — conf
CogniVision: A mW Power envelope SoC for Always-on Smart Vision in 40nm.
HCS
Animesh Gupta, Japesh Vohra, Massimo Alioto
2024 — conf
CogniVision: End-to-End SoC for Always-on Smart Vision with mW Power in 40nm.
VLSI Technology and Circuits
Animesh Gupta, Japesh Vohra, Massimo Alioto
2024 — conf
E-Textile Battery-Less Walking Step Counting System with <23 pW Power, Dual-Function Harvesting from Breathing, and No High-Voltage CMOS Process.
VLSI Technology and Circuits
Anil Kumar Gundu, Luigi Fassio, Massimo Alioto
2024 J jnl
Guest Editorial Introduction to the Special Section on the 2023 IEEE International Solid-State Circuits Conference (ISSCC).
IEEE J. Solid State Circuits
Mike Shuo-Wei Chen, Visvesh S. Sathe, Massimo Alioto, Jae-sun Seo, Hidehiro Shiga
2024 A* conf
Multi-Stage Face-Voice Association Learning with Keynote Speaker Diarization.
ACM Multimedia
Ruijie Tao, Zhan Shi, Yidi Jiang, Duc-Tuan Truong, Eng Siong Chng, Massimo Alioto, Haizhou Li
2024 J jnl
Picowatt-Power Super-Cutoff Analog Building Blocks and 78-pW Battery-Less Wake-Up Receiver for Light-Harvested Near-Always-On Operation.
IEEE J. Solid State Circuits
Joydeep Basu, Luigi Fassio, Karim Ali, Massimo Alioto
2024 — conf
SRAM Physically Unclonable Function Extracting Static Entropy from Every Bitcell Transistor for 6 bit/bitcell and Data Fingerprinting Capability for Provenance Assurance.
A-SSCC
Tianqi Wang, Joydeep Basu, Viveka Konandur Rajanna, Massimo Alioto
2023 — conf
38.4-pW, 0.14-mm
VLSI Technology and Circuits
Luigi Fassio, Orazio Aiello, Massimo Alioto
2023 — conf
55pW/pixel Peak Power Imager with Near-Sensor Novelty/Edge Detection and DC-DC Converter-Less MPPT for Purely Harvested Sensor Nodes.
ISSCC
Karim Ali Ahmed, Hayate Okuhara, Massimo Alioto
2023 — conf
A 0.4V 12b Comparator Offset Injection Assisted SAR ADC achieving 0.425 fJ/conv-step.
ESSCIRC
Japesh Vohra, Karim Ali Ahmed, Massimo Alioto
2023 — conf
A Resistor/Trimming-Less Self-Biased Current Reference Class with Area Down to $3,500\ \mu \mathrm{m}^{2}$, 42.8 pW Power and 10.4% Accuracy across Corner Wafers in 180 nm.
A-SSCC
Luigi Fassio, Hoang Hong Hanh, Massimo Alioto
2023 J jnl
Capacitance-to-Digital Converter for Harvested Systems Down to 0.3 V With No Trimming, Reference, and Voltage Regulation.
IEEE Trans. Circuits Syst. I Regul. Pap.
Orazio Aiello, Paolo Stefano Crovetti, Massimo Alioto
2023 — conf
ECC-Less Multi-Level SRAM Physically Unclonable Function and 127% PUF-to-Memory Capacity Ratio with No Bitcell Modification in 28nm.
VLSI Technology and Circuits
Joydeep Basu, Sachin Taneja, Viveka Konandur Rajanna, Tianqi Wang, Massimo Alioto
2023 J jnl
Guest Editorial IEEE 2022 European Solid-State Circuits Conference.
IEEE J. Solid State Circuits
Makoto Nagata, Massimo Alioto
2023 J jnl
Laser Voltage Probing Attack Detection With 100% Area/Time Coverage at Above/Below the Bandgap Wavelength and Fully-Automated Design.
IEEE J. Solid State Circuits
Hui Zhang, Longyang Lin, Qiang Fang, Massimo Alioto
2023 J jnl
Opening of the 2023 Editorial Year - This Coda as Prelude of Next TVLSI Cycle With Sustained Growth.
IEEE Trans. Very Large Scale Integr. Syst.
Massimo Alioto
2023 — conf
Self-Referenced Design-Agnostic Laser Voltage Probing Attack Detection with 100% Protection Coverage, 58% Area Overhead for Automated Design.
VLSI Technology and Circuits
Hui Zhang, Longyang Lin, Qiang Fang, Udara Samurdhi Harshanga Kalingage, Massimo Alioto
2023 — conf
Single-Antenna Backscattered BLE5 Transmitter with up to 97m Range, 10.6 μW Peak Power for Purely-Harvested Green Systems.
ESSCIRC
Karim Ali Ahmed, Ruiyuan Yang, Praveenakumar Shivappa Salamani, Viveka Konandur Rajanna, Massimo Alioto
2023 — conf
Super-Cutoff Analog Building Blocks for pW/Stage Operation and Demonstration of 78-pW Battery-Less Light-Harvested Wake-Up Receiver down to Moonlight.
VLSI Technology and Circuits
Joydeep Basu, Luigi Fassio, Karim Ali, Massimo Alioto
2023 — conf
Temporal Similarity-Based Computation Reduction for Video Transformers in Edge Camera Nodes.
AICAS
Udari De Alwis, Zhongheng Xie, Massimo Alioto
2023 — conf
Visual Content-Agnostic Novelty Detection Engine with 2.4 pJ/pixel Energy and Two-Order of Magnitude DNN Activity Reduction in 40 nm.
VLSI Technology and Circuits
Animesh Gupta, Sayan Kumar, Viveka Konandur Rajanna, Sachin Taneja, Massimo Alioto
2023 J jnl
Voltage Reference With Corner-Aware Replica Selection/Merging for 1.4-mV Accuracy in Harvested Systems Down to 3.9 pW, 0.2 V.
IEEE Access
Luigi Fassio, Longyang Lin, Raffaele De Rose, Marco Lanuzza, Felice Crupi, Massimo Alioto
2023 — conf
Voltage Scaling-Agnostic Counteraction of Side-Channel Neural Net Reverse Engineering via Machine Learning Compensation and Multi-Level Shuffling.
VLSI Technology and Circuits
Qiang Fang, Longyang Lin, Hui Zhang, Tianqi Wang, Massimo Alioto
2022 — conf
Architecture for 3D Convolutional Neural Networks Based on Temporal Similarity Removal.
ICECS 2022
Udari De Alwis, Massimo Alioto
2022 — conf
Capacitance-Based Voltage Regulation- and Reference-Free Temperature-to-Digital Converter down to 0.3 V and 2.5 nW for Direct Harvesting.
ESSCIRC
Orazio Aiello, Massimo Alioto
2022 — conf
Circuits and Architectures for Next-generation Attentive & Intelligent Systems.
VLSI-DAT
Massimo Alioto
2022 — conf
Conversion Time-Power Tradeoff in Capacitance-to-Digital Converters with Dual-Mode Logic.
SBCCI
Orazio Aiello, Paolo Crovetti, Massimo Alioto
2022 — conf
DDPMnet: All-Digital Pulse Density-Based DNN Architecture with 228 Gate Equivalents/MAC Unit, 28-TOPS/W and 1.5-TOPS/mm2 in 40nm.
CICC
Animesh Gupta, Viveka Konandur Rajanna, Thoithoi Salam, Saurabh Jain, Orazio Aiello, Paolo Crovetti, Massimo Alioto
2022 J jnl
Editorial Opening of the 2022 TVLSI Editorial Year - Connecting Trends From Society to VLSI Systems.
IEEE Trans. Very Large Scale Integr. Syst.
Massimo Alioto
2022 — conf
From Less Batteries to Battery-Less: Enabling A Greener World through Ultra-Wide Power-Performance Adaptation down to pWs.
ESSCIRC
Massimo Alioto
2022 — conf
Fully-Digital Broadband Calibration-Less Impedance Monitor for Probe Insertion Detection against Power Analysis Attacks.
VLSI Technology and Circuits
Viveka Konandur Rajanna, Himadri Singh Raghav, Tianqi Wang, Massimo Alioto
2022 — conf
Imager with Dynamic LSB Adaptation and Ratiometric Readout for Low-Bit Depth 5-μW Peak Power in Purely-Harvested Systems.
VLSI Technology and Circuits
Karim Ali Ahmed, Longyang Lin, Praveenakumar Shivappa Salamani, Massimo Alioto
2022 J jnl
In-Memory Unified TRNG and Multi-Bit PUF for Ubiquitous Hardware Security.
IEEE J. Solid State Circuits
Sachin Taneja, Viveka Konandur Rajanna, Massimo Alioto
2022 — conf
On-Chip Laser Voltage Probing Attack Detection with 100% Area Coverage at Above/Below the Bandgap Wavelength and Fully-Automated Design.
VLSI Technology and Circuits
Hui Zhang, Longyang Lin, Qiang Fang, Massimo Alioto
2022 J jnl
STT-BNN: A Novel STT-MRAM In-Memory Computing Macro for Binary Neural Networks.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Thi-Nhan Pham, Quang-Kien Trinh, Ik-Joon Chang, Massimo Alioto
2022 — conf
Side-Channel Attack Counteraction via Machine Learning-Targeted Power Compensation for Post-Silicon HW Security Patching.
ISSCC
Qiang Fang, Longyang Lin, Yao Zu Wong, Hui Zhang, Massimo Alioto
2022 — conf
Temporal Redundancy-Based Computation Reduction for 3D Convolutional Neural Networks.
AICAS
Udari De Alwis, Massimo Alioto
2021 — conf
36.1 Unified In-Memory Dynamic TRNG and Multi-Bit Static PUF Entropy Generation for Ubiquitous Hardware Security.
ISSCC
Sachin Taneja, Viveka Konandur Rajanna, Massimo Alioto
2021 J jnl
A 0.6-to-1.8V CMOS Current Reference With Near-100% Power Utilization.
IEEE Trans. Circuits Syst. II Express Briefs
Luigi Fassio, Longyang Lin, Raffaele De Rose, Marco Lanuzza, Felice Crupi, Massimo Alioto
2021 — conf
A 1448-Mpixel/s, 84-pJ/Pixel Display Stream Compression Encoder in 28 nm for 4K Video Resolution.
A-SSCC
Shifu Wu, K. De Silva, Snehlata Gutgutia, Bevan M. Baas, Massimo Alioto
2021 — conf
A 3.2-pW, 0.2-V Trimming-Less Voltage Reference with 1.4-mV Across-Wafer Total Accuracy.
ESSCIRC
Luigi Fassio, Longyang Lin, Raffaele De Rose, Marco Lanuzza, Felice Crupi, Massimo Alioto
2021 J jnl
A 300mV-Supply, Sub-nW-Power Digital-Based Operational Transconductance Amplifier.
IEEE Trans. Circuits Syst. II Express Briefs
Pedro Toledo, Paolo Crovetti, Hamilton Klimach, Sergio Bampi, Orazio Aiello, Massimo Alioto
2021 J jnl
A Robust, High-Speed and Energy-Efficient Ultralow-Voltage Level Shifter.
IEEE Trans. Circuits Syst. II Express Briefs
Luigi Fassio, Francesco Settino, Longyang Lin, Raffaele De Rose, Marco Lanuzza, Felice Crupi, Massimo Alioto
2021 — conf
Battery-Less IoT Sensor Node with PLL-Less WiFi Backscattering Communications in a 2.5-μW Peak Power Envelope.
VLSI Circuits
Longyang Lin, Karim Ali Ahmed, Praveenakumar Shivappa Salamani, Massimo Alioto
2021 — conf
Capacitance-to-Digital Converter for Operation Under Uncertain Harvested Voltage down to 0.3V with No Trimming, Reference and Voltage Regulation.
ISSCC
Orazio Aiello, Paolo Crovetti, Massimo Alioto
2021 J jnl
Design of Digital OTAs With Operation Down to 0.3 V and nW Power for Direct Harvesting.
IEEE Trans. Circuits Syst. I Regul. Pap.
Pedro Toledo, Paolo Crovetti, Orazio Aiello, Massimo Alioto
2021 — conf
F4: Electronics for a Quantum World.
ISSCC
Edoardo Charbon, Alicia Klinefelter, Massimo Alioto, Yao-Hong Liu, Munehiko Nagatani, Arijit Raychowdhury, Andreia Cathelin, Boris Murmann
2021 J jnl
From Less Batteries to Battery-Less Alert Systems with Wide Power Adaptation down to nWs - Toward a Smarter, Greener World.
IEEE Des. Test
Massimo Alioto
2021 J jnl
Fully Synthesizable Unified True Random Number Generator and Cryptographic Core.
IEEE J. Solid State Circuits
Sachin Taneja, Massimo Alioto
2021 — conf
Fully-Digital Self-Calibrating Decoder with Sub-µW, 1.6fJ/convstep and 0.0075mm
VLSI Circuits
Prachi Agarwal, Viveka Konandur Rajanna, Toh Wei Da, Benjamin C. K. Tee, Massimo Alioto
2021 — conf
Last-Round and Joint First/Last-Round Power Analysis Attacks on PRESENT.
AsianHOST
Qiang Fang, Massimo Alioto
2021 J jnl
On-Chip Links With Energy-Quality Tradeoff in Error-Resilient and Machine Learning Applications.
IEEE J. Solid State Circuits
Viveka Konandur Rajanna, Massimo Alioto
2021 J jnl
Opening of the 2021 Editorial Year - Overture for a New Year of Change.
IEEE Trans. Very Large Scale Integr. Syst.
Massimo Alioto
2021 J jnl
PUF Architecture with Run-Time Adaptation for Resilient and Energy-Efficient Key Generation via Sensor Fusion.
IEEE J. Solid State Circuits
Sachin Taneja, Massimo Alioto
2021 J jnl
Rail-to-Rail Dynamic Voltage Comparator Scalable Down to pW-Range Power and 0.15-V Supply.
IEEE Trans. Circuits Syst. II Express Briefs
Orazio Aiello, Paolo Crovetti, Pedro Toledo, Massimo Alioto
2021 — conf
SRAM with In-Memory Inference and 90% Bitline Activity Reduction for Always-On Sensing with 109 TOPS/mm
ESSCIRC
Viveka Konandur Rajanna, Sachin Taneja, Massimo Alioto
2021 — conf
SRAM with In-Memory Inference and 90% Bitline Activity Reduction for Always-On Sensing with 109 TOPS/mm
ESSDERC
Viveka Konandur Rajanna, Sachin Taneja, Massimo Alioto
2021 C conf
STT-MRAM Architecture with Parallel Accumulator for In-Memory Binary Neural Networks.
ISCAS
Thi-Nhan Pham, Kien Trinh Quang, Ik-Joon Chang, Massimo Alioto
2021 J jnl
Second Quarter of the 2021 Editorial Year - A Year in Crescendo.
IEEE Trans. Very Large Scale Integr. Syst.
Massimo Alioto
2021 — conf
Session 36 Overview: Hardware Security Digital Architectures and Systems Subcommittee.
ISSCC
Hirofumi Shinohara, Massimo Alioto, Ingrid Verbauwhede
2021 J jnl
Sub-nW Microcontroller With Dual-Mode Logic and Self-Startup for Battery-Indifferent Sensor Nodes.
IEEE J. Solid State Circuits
Longyang Lin, Saurabh Jain, Massimo Alioto
2021 J jnl
TempDiff: Feature Map-Level CNN Sparsity Enhancement at Near-Zero Memory Overhead via Temporal Difference.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Udari De Alwis, Massimo Alioto
2021 — conf
TempDiff: Temporal Difference-Based Feature Map-Level Sparsity Induction in CNNs with <4% Memory Overhead.
AICAS
Udari De Alwis, Massimo Alioto
2021 J jnl
Trimming-Less Voltage Reference for Highly Uncertain Harvesting Down to 0.25 V, 5.4 pW.
IEEE J. Solid State Circuits
Luigi Fassio, Longyang Lin, Raffaele De Rose, Marco Lanuzza, Felice Crupi, Massimo Alioto
2021 J jnl
±CIM SRAM for Signed In-Memory Broad-Purpose Computing From DSP to Neural Processing.
IEEE J. Solid State Circuits
Saurabh Jain, Longyang Lin, Massimo Alioto
2020 — conf
A 0.25-V, 5.3-pW Voltage Reference with 25-μV/°C Temperature Coefficient, 140-μV/V Line Sensitivity and 2, 200-μm
VLSI Circuits
Luigi Fassio, Longyang Lin, Raffaele De Rose, Marco Lanuzza, Felice Crupi, Massimo Alioto
2020 J jnl
Approximate Multipliers With Dynamic Truncation for Energy Reduction via Graceful Quality Degradation.
IEEE Trans. Circuits Syst.
Fabio Frustaci, Stefania Perri, Pasquale Corsonello, Massimo Alioto
2020 J jnl
Automated Design of Reconfigurable Microarchitectures for Accelerators Under Wide-Voltage Scaling.
IEEE Trans. Very Large Scale Integr. Syst.
Saurabh Jain, Longyang Lin, Massimo Alioto
2020 C conf
Automated Design of Reconfigurable Microarchitectures for Accelerators under Wide-Voltage Scaling.
ISCAS
Saurabh Jain, Longyang Lin, Massimo Alioto
2020 C conf
Deep Sub-pJ/Bit Low-Area Energy-Security Scalable SIMON Crypto-Core in 40 nm.
ISCAS
Sachin Taneja, Massimo Alioto
2020 J jnl
Editorial on the Conclusion of the 2020 Editorial Year - The Climactic Finale of a Peculiar Year.
IEEE Trans. Very Large Scale Integr. Syst.
Massimo Alioto
2020 J jnl
Editorial on the Opening of the New Editorial Year - The State of the IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
IEEE Trans. Very Large Scale Integr. Syst.
Massimo Alioto
2020 — conf
Enabling Always-On Sensor Nodes Entirely Powered by Sustainable Energy Sources - Making Our World Smarter and Greener.
iSES
Massimo Alioto
2020 J jnl
Energy-Quality Scalable Memory-Frugal Feature Extraction for Always-On Deep Sub-mW Distributed Vision.
IEEE Access
Anastacia B. Alvarez, Gopalakrishnan Ponnusamy, Massimo Alioto
2020 J jnl
Fully Synthesizable Low-Area Analogue-to-Digital Converters With Minimal Design Effort Based on the Dyadic Digital Pulse Modulation.
IEEE Access
Orazio Aiello, Paolo Crovetti, Massimo Alioto
2020 J jnl
Integrated Power Management for Battery-Indifferent Systems With Ultra-Wide Adaptation Down to nW.
IEEE J. Solid State Circuits
Longyang Lin, Saurabh Jain, Massimo Alioto
2020 J jnl
Low-Energy Voice Activity Detection via Energy-Quality Scaling From Data Conversion to Machine Learning.
IEEE Trans. Circuits Syst. I Fundam. Theory Appl.
Jinq Horng Teo, Shuai Cheng, Massimo Alioto
2020 — conf
Multi-Sensor Platform with Five-Order-of-Magnitude System Power Adaptation down to 3.1nW and Sustained Operation under Moonlight Harvesting.
VLSI Circuits
Longyang Lin, Saurabh Jain, Massimo Alioto
2020 J jnl
Processor Energy-Performance Range Extension Beyond Voltage Scaling via Drop-In Methodologies.
IEEE J. Solid State Circuits
Saurabh Jain, Longyang Lin, Massimo Alioto
2020 — conf
Voice Activity Detection with >83% Accuracy under SNR down to -3dB at $1.19\mu \mathrm{W}$ and 0.07mm
A-SSCC
Jinq Horng Teo, K. Ali, Massimo Alioto
2019 J jnl
A pW-Power Hz-Range Oscillator Operating With a 0.3-1.8-V Unregulated Supply.
IEEE J. Solid State Circuits
Orazio Aiello, Paolo Crovetti, Longyang Lin, Massimo Alioto
2019 — conf
An Energy Aware Variation-Tolerant Writing Termination Control for STT-based Non Volatile Flip-Flops.
ICECS
Marco Lanuzza, Raffaele De Rose, Felice Crupi, Massimo Alioto
2019 — conf
Drop-In Energy-Performance Range Extension in Microcontrollers Beyond VDD Scaling.
A-SSCC
Saurabh Jain, Longyang Lin, Massimo Alioto
2019 J jnl
Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory.
IEEE Trans. Very Large Scale Integr. Syst.
Massimo Alioto, Magdy S. Abadir, Tughrul Arslan, Chirn Chye Boon, Andreas Burg, Chip-Hong Chang, Meng-Fan Chang, Yao-Wen Chang, Poki Chen, Pasquale Corsonello, Paolo Crovetti, Shiro Dosho, Rolf Drechsler, Ibrahim Abe M. Elfadel, Ruonan Han, Masanori Hashimoto, Chun-Huat Heng, Deukhyoun Heo, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Ajay Joshi, Rajiv V. Joshi, Tanay Karnik, Chulwoo Kim, Tony Tae-Hyoung Kim, Jaydeep P. Kulkarni, Volkan Kursun, Yoonmyung Lee, Hai Helen Li, Huawei Li, Prabhat Mishra, Baker Mohammad, Mehran Mozaffari Kermani, Makoto Nagata, Koji Nii, Partha Pratim Pande, Bipul C. Paul, Vasilis F. Pavlidis, José Pineda de Gyvez, Ioannis Savidis, Patrick Schaumont, Fabio Sebastiano, Anirban Sengupta, Mingoo Seok, Mircea R. Stan, Mark Tehranipoor, Aida Todri-Sanial, Marian Verhelst, Valerio Vignoli, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Jun Zhou, Mark Zwolinski, Stacey Weber
2019 J jnl
Editorial: TVLSI Keynote Papers Enriching Our Transactions With Invited Contributions.
IEEE Trans. Very Large Scale Integr. Syst.
Massimo Alioto
2019 — conf
Enabling Ubiquitous Hardware Security via Energy-Efficient Primitives and Systems : (Invited Paper).
CICC
Massimo Alioto, Sachin Taneja
2019 J jnl
Energy-Quality Scalable Adders Based on Nonzeroing Bit Truncation.
IEEE Trans. Very Large Scale Integr. Syst.
Fabio Frustaci, Stefania Perri, Pasquale Corsonello, Massimo Alioto
2019 — conf
Energy-Quality Scalable Analog-to-Digital Conversion and Machine Learning Engine in a 51.9 nJ/frame Voice Activity Detector.
ICECS
Jinq Horng Teo, Shuai Cheng, Massimo Alioto
2019 J jnl
Fully Synthesizable Low-Area Digital-to-Analog Converter With Graceful Degradation and Dynamic Power-Resolution Scaling.
IEEE Trans. Circuits Syst. I Regul. Pap.
Orazio Aiello, Paolo Stefano Crovetti, Massimo Alioto
2019 — conf
Fully-Synthesizable Current-Input ADCs for Ultra-Low Area and Minimal Design Effort.
ICECS
Orazio Aiello, Paolo Crovetti, Ayushparth Sharma, Massimo Alioto
2019 — conf
Integrated Power Management and Microcontroller for Ultra-Wide Power Adaptation down to nW.
VLSI Circuits
Longyang Lin, Saurabh Jain, Massimo Alioto
2019 — conf
Low-Swing Links with Dynamic Energy-Quality Trade-off for Error-Resilient Applications.
CICC
Viveka Konandur Rajanna, Massimo Alioto
2019 — conf
Minimum-Effort Design of Ultra-Low Power Interfaces for the Internet of Things.
ICECS
Orazio Aiello, Paolo Crovetti, Massimo Alioto
2019 — conf
PUF-based Key Generation with Design Margin Reduction via In-Situ and PVT Sensor Fusion.
ESSCIRC
Sachin Taneja, Massimo Alioto
2019 J jnl
Reconfigurable Clock Networks for Wide Voltage Scaling.
IEEE J. Solid State Circuits
Longyang Lin, Saurabh Jain, Massimo Alioto
2019 J jnl
Standard Cell-Based Ultra-Compact DACs in 40-nm CMOS.
IEEE Access
Orazio Aiello, Paolo Crovetti, Massimo Alioto
2019 — conf
Thursday Keynote: Survival of The Fittest: Circuits and Architectures for Computation with Wide Power- Performance Adaptation Beyond Voltage Scaling.
SoCC
Massimo Alioto
2019 J jnl
Token-Based Security for the Internet of Things With Dynamic Energy-Quality Tradeoff.
IEEE Internet Things J.
Muhammad Naveed Aman, Sachin Taneja, Biplab Sikdar, Kee Chaing Chua, Massimo Alioto
2019 C conf
Wake-Up Oscillators with pW Power Consumption in Dynamic Leakage Suppression Logic.
ISCAS
Orazio Aiello, Paolo Crovetti, Massimo Alioto
2018 — conf
A 595pW 14pJ/Cycle microcontroller with dual-mode standard cells and self-startup for battery-indifferent distributed sensing.
ISSCC
Longyang Lin, Saurabh Jain, Massimo Alioto
2018 — conf
A Sub-Leakage PW-Power HZ-Range Relaxation Oscillator Operating with 0.3V-1.8V Unregulated Supply.
VLSI Circuits
Orazio Aiello, Paolo Crovetti, Massimo Alioto
2018 J jnl
A Variation-Aware Timing Modeling Approach for Write Operation in Hybrid CMOS/STT-MTJ Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap.
Raffaele De Rose, Marco Lanuzza, Felice Crupi, Giulio Siracusano, Riccardo Tomasello, Giovanni Finocchio, Mario Carpentieri, Massimo Alioto
2018 C conf
Design-Space Exploration of Pareto-Optimal Architectures for Deep Learning with DVFS.
ISCAS
Giulia Santoro, Mario R. Casu, Valentino Peluso, Andrea Calimera, Massimo Alioto
2018 Misc conf
Display Stream Compression Encoder Architectures for Real-time 4K and 8K Video Encoding.
ACSSC
Shifu Wu, Snehlata Gutgutia, Massimo Alioto, Bevan M. Baas
2018 J jnl
Dynamic Reference Voltage Sensing Scheme for Read Margin Improvement in STT-MRAMs.
IEEE Trans. Circuits Syst. I Regul. Pap.
Kien Trinh Quang, Sergio Ruocco, Massimo Alioto
2018 J jnl
Dynamically Adaptable Pipeline for Energy-Efficient Microarchitectures Under Wide Voltage Scaling.
IEEE J. Solid State Circuits
Saurabh Jain, Longyang Lin, Massimo Alioto
2018 J jnl
Energy-Quality Scalable Integrated Circuits and Systems: Continuing Energy Scaling in the Twilight of Moore's Law.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Massimo Alioto, Vivek De, Andrea Marongiu
2018 A conf
Energy-performance design exploration of a low-power microprogrammed deep-learning accelerator.
DATE
Giulia Santoro, Mario R. Casu, Valentino Peluso, Andrea Calimera, Massimo Alioto
2018 J jnl
Fully Synthesizable PUF Featuring Hysteresis and Temperature Compensation for 3.2% Native BER and 1.02 fJ/b in 40 nm.
IEEE J. Solid State Circuits
Sachin Taneja, Anastacia B. Alvarez, Massimo Alioto
2018 C conf
Fully Synthesizable, Rail-to-Rail Dynamic Voltage Comparator for Operation down to 0.3 V.
ISCAS
Orazio Aiello, Paolo Crovetti, Massimo Alioto
2018 J jnl
Guest Editorial Energy-Quality Scalable Circuits and Systems for Sensing and Computing: From Approximate to Communication-Inspired and Learning-Based.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Massimo Alioto, Vivek De, Andrea Marongiu
2018 J jnl
Guest Editorial Special Issue on Selected Papers from PRIME 2017 and SMACD 2017.
Integr.
Giulia Di Capua, Nuno Horta, Francisco V. Fernández, Günhan Dündar, Salvatore Pennisi, Gaetano Palumbo, Massimo Alioto, Gianluca Giustolisi
2018 C conf
Novel Time-Based Sensing Scheme for STT-MRAMs.
ISCAS
Kien Trinh Quang, Sergio Ruocco, Massimo Alioto
2018 C conf
Project-Based Learning in Digital Fundamentals Course Using FPGAs.
FIE
Dingjuan Chua, Jieyi Gao, Massimo Alioto, Yong Ping Xu, Sangit Sasidhar
2018 J jnl
The Internet of Things on Its Edge: Trends Toward Its Tipping Point.
IEEE Consumer Electron. Mag.
Massimo Alioto, Mohsen Shahghasemi
2018 J jnl
Time-Based Sensing for Reference-Less and Robust Read in STT-MRAM Memories.
IEEE Trans. Circuits Syst. I Regul. Pap.
Kien Trinh Quang, Sergio Ruocco, Massimo Alioto
2018 J jnl
Ultra-Low Power Crypto-Engine Based on Simon 32/64 for Energy- and Area-Constrained Integrated Systems.
CoRR
Sachin Taneja, Massimo Alioto
2018 J jnl
iRazor: Current-Based Error Detection and Correction Scheme for PVT Variation in 40-nm ARM Cortex-R4 Processor.
IEEE J. Solid State Circuits
Yiqun Zhang, Mahmood Khayatzadeh, Kaiyuan Yang, Mehdi Saligane, Nathaniel Ross Pinckney, Massimo Alioto, David T. Blaauw, Dennis Sylvester
2017 — conf
26.3 Reconfigurable clock networks for random skew mitigation from subthreshold to nominal voltage.
ISSCC
Longyang Lin, Saurabh Jain, Massimo Alioto
2017 — ed.
30th IEEE International System-on-Chip Conference, SOCC 2017, Munich, Germany, September 5-8, 2017
SOCC
Massimo Alioto, Hai Helen Li, Jürgen Becker, Ulf Schlichtmann, Ramalingam Sridhar
2017 J jnl
A Novel Framework to Estimate the Path Delay Variability On the Back of an Envelope via the Fan-Out-of-4 Metric.
IEEE Trans. Circuits Syst. I Regul. Pap.
Massimo Alioto, Giuseppe Scotti, Alessandro Trifiletti
2017 — conf
A fully-synthesizable C-element based PUF featuring temperature variation compensation with native 2.8% BER, 1.02fJ/b at 0.8-1.0V in 40nm.
A-SSCC
Sachin Taneja, Anastacia B. Alvarez, Gopalakrishnan Sadagopan, Massimo Alioto
2017 C conf
A variation-aware simulation framework for hybrid CMOS/spintronic circuits.
ISCAS
Raffaele De Rose, Marco Lanuzza, Felice Crupi, Giulio Siracusano, Riccardo Tomasello, Giovanni Finocchio, Mario Carpentieri, Massimo Alioto
2017 J jnl
Design-Oriented Energy Models for Wide Voltage Scaling Down to the Minimum Energy Point.
IEEE Trans. Circuits Syst. I Regul. Pap.
Saurabh Jain, Longyang Lin, Massimo Alioto
2017 C conf
Design-oriented models for quick estimation of path delay variability via the fan-out-of-4 metric.
ISCAS
Massimo Alioto, Giuseppe Scotti, Alessandro Trifiletti
2017 — conf
EQSCALE: Energy-quality scalable feature extraction engine for Sub-mW real-time video processing with 0.55 mm
A-SSCC
Anastacia B. Alvarez, Gopalakrishnan Ponnusamy, Massimo Alioto
2017 J jnl
Editorial.
IEEE Trans. Very Large Scale Integr. Syst.
Krishnendu Chakrabarty, Massimo Alioto, Bevan M. Baas, Chirn Chye Boon, Meng-Fan Chang, Naehyuck Chang, Yao-Wen Chang, Chip-Hong Chang, Shih-Chieh Chang, Poki Chen, Masud H. Chowdhury, Pasquale Corsonello, Ibrahim Abe M. Elfadel, Said Hamdioui, Masanori Hashimoto, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Rajiv V. Joshi, Tanay Karnik, Mehran Mozaffari Kermani, Chulwoo Kim, Tae-Hyoung Kim, Jaydeep P. Kulkarni, Eren Kursun, Erik Larsson, Hai (Helen) Li, Huawei Li, Patrick P. Mercier, Prabhat Mishra, Makoto Nagata, Arun S. Natarajan, Koji Nii, Partha Pratim Pande, Ioannis Savidis, Mingoo Seok, Sheldon X.-D. Tan, Mark Tehranipoor, Aida Todri-Sanial, Miroslav N. Velev, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Stacey Weber Jackson
2017 J jnl
Editorial.
IEEE Trans. Very Large Scale Integr. Syst.
Krishnendu Chakrabarty, Massimo Alioto, Rajiv V. Joshi
2017 A conf
Energy-quality scalable adaptive VLSI circuits and systems beyond approximate computing.
DATE
Massimo Alioto
2017 J jnl
Guest Editorial Special Issue on Circuits and Systems for the Internet of Things - From Sensing to Sensemaking.
IEEE Trans. Circuits Syst. I Regul. Pap.
Massimo Alioto, Edgar Sánchez-Sinencio, Alberto L. Sangiovanni-Vincentelli
2017 C conf
Power-precision scalable latch memories.
ISCAS
Darjn Esposito, Antonio G. M. Strollo, Massimo Alioto
2017 — conf
STT-MRAM memories for IoT applications: Challenges and opportunities at circuit level and above.
VLSI-DAT
Massimo Alioto
2017 C conf
Transistor sizing strategy for simultaneous energy-delay optimization in CMOS buffers.
ISCAS
Longyang Lin, Kien Trinh Quang, Massimo Alioto
2016 — conf
17.3 A reconfigurable dual-port memory with error detection and correction in 28nm FDSOI.
ISSCC
Mahmood Khayatzadeh, Mehdi Saligane, Jingcheng Wang, Massimo Alioto, David T. Blaauw, Dennis Sylvester
2016 — ed.
29th IEEE International System-on-Chip Conference, SOCC 2016, Seattle, WA, USA, September 6-9, 2016
SOCC
Karan S. Bhatia, Massimo Alioto, Danella Zhao, Andrew Marshall, Ramalingam Sridhar
2016 — conf
8.8 iRazor: 3-transistor current-based error detection and correction in an ARM Cortex-R4 processor.
ISSCC
Yiqun Zhang, Mahmood Khayatzadeh, Kaiyuan Yang, Mehdi Saligane, Nathaniel Ross Pinckney, Massimo Alioto, David T. Blaauw, Dennis Sylvester
2016 — conf
A closed-form energy model for VLSI circuits under wide voltage scaling.
ICECS
Saurabh Jain, Massimo Alioto
2016 J jnl
Approximate SRAMs With Dynamic Energy-Quality Management.
IEEE Trans. Very Large Scale Integr. Syst.
Fabio Frustaci, David T. Blaauw, Dennis Sylvester, Massimo Alioto
2016 — conf
Beyond Ideal DVFS Through Ultra-Fine Grain Vdd-Hopping.
VLSI-SoC (Selected Papers)
Valentino Peluso, Roberto Giorgio Rizzo, Andrea Calimera, Enrico Macii, Massimo Alioto
2016 C conf
Boosted sensing for enhanced read stability in STT-MRAMs.
ISCAS
Kien Trinh Quang, Sergio Ruocco, Massimo Alioto
2016 J jnl
Editorial First TVLSI Best AE and Reviewer Awards.
IEEE Trans. Very Large Scale Integr. Syst.
Krishnendu Chakrabarty, Massimo Alioto
2016 J jnl
Novel Boosted-Voltage Sensing Scheme for Variation-Resilient STT-MRAM Read.
IEEE Trans. Circuits Syst. I Regul. Pap.
Kien Trinh Quang, Sergio Ruocco, Massimo Alioto
2016 C conf
STT-MRAM write energy minimization via area optimization under dynamic voltage Scaling.
ISCAS
Kien Trinh Quang, Sergio Ruocco, Massimo Alioto
2016 J jnl
Static Physically Unclonable Functions for Secure Chip Identification With 1.9-5.8% Native Bit Instability at 0.6-1 V and 15 fJ/bit in 65 nm.
IEEE J. Solid State Circuits
Anastacia B. Alvarez, Wenfeng Zhao, Massimo Alioto
2016 C conf
Ultra-Fine Grain Vdd-Hopping for energy-efficient Multi-Processor SoCs.
VLSI-SoC
Valentino Peluso, Andrea Calimera, Enrico Macii, Massimo Alioto
2016 — conf
Ultra-low voltage standard cell libraries: Design strategies and a case study.
ICECS
Somayeh Timarchi, Massimo Alioto
2016 J jnl
Voltage Scaled STT-MRAMs Towards Minimum-Energy Write Access.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Kien Trinh Quang, Sergio Ruocco, Massimo Alioto
2015 — conf
14.3 15fJ/b static physically unclonable functions for secure chip identification with <2% native bit instability and 140× Inter/Intra PUF hamming distance separation in 65nm.
ISSCC
Anastacia B. Alvarez, Wenfeng Zhao, Massimo Alioto
2015 — conf
A reconfigurable sense amplifier with 3X offset reduction in 28nm FDSOI CMOS.
VLSIC
Mahmood Khayatzadeh, Fabio Frustaci, David T. Blaauw, Dennis Sylvester, Massimo Alioto
2015 C conf
AES architectures for minimum-energy operation and silicon demonstration in 65nm with lowest energy per encryption.
ISCAS
Wenfeng Zhao, Yajun Ha, Massimo Alioto
2015 J jnl
Analysis and Characterization of Variability in Subthreshold Source-Coupled Logic Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap.
Mahsa Shoaran, Armin Tajalli, Massimo Alioto, Alexandre Schmid, Yusuf Leblebici
2015 — conf
Better-than-voltage scaling energy reduction in approximate SRAMs via bit dropping and bit reuse.
PATMOS
Fabio Frustaci, David T. Blaauw, Dennis Sylvester, Massimo Alioto
2015 — conf
Comparative analysis of the robustness of master-slave flip-flops against variations.
ICECS
Massimo Alioto, Elio Consoli, Gaetano Palumbo
2015 C conf
Jitter analysis and measurement in subthreshold source-coupled differential ring oscillators.
ISCAS
Mahsa Shoaran, Armin Tajalli, Massimo Alioto, Yusuf Leblebici
2015 C conf
Modeling the impact of dynamic voltage scaling on 1T-1J STT-RAM write energy and performance.
ISCAS
Kien Trinh Quang, Sergio Ruocco, Massimo Alioto
2015 J jnl
Novel Self-Body-Biasing and Statistical Design for Near-Threshold Circuits With Ultra Energy-Efficient AES as Case Study.
IEEE Trans. Very Large Scale Integr. Syst.
Wenfeng Zhao, Yajun Ha, Massimo Alioto
2015 — conf
PVT variations in differential flip-flops: A comparative analysis.
ECCTD
Massimo Alioto, Gaetano Palumbo, Elio Consoli
2015 J jnl
SRAM for Error-Tolerant Applications With Dynamic Energy-Quality Management in 28 nm CMOS.
IEEE J. Solid State Circuits
Fabio Frustaci, Mahmood Khayatzadeh, David T. Blaauw, Dennis Sylvester, Massimo Alioto
2015 — conf
Variability budgetin pulsed flip-flops.
NEWCAS
Massimo Alioto, Gaetano Palumbo, Elio Consoli
2015 J jnl
Variations in Nanometer CMOS Flip-Flops: Part I - Impact of Process Variations on Timing.
IEEE Trans. Circuits Syst. I Regul. Pap.
Massimo Alioto, Elio Consoli, Gaetano Palumbo
2015 J jnl
Variations in Nanometer CMOS Flip-Flops: Part II - Energy Variability and Impact of Other Sources of Variations.
IEEE Trans. Circuits Syst. I Regul. Pap.
Massimo Alioto, Elio Consoli, Gaetano Palumbo
2014 — conf
13.8 A 32kb SRAM for error-free and error-tolerant applications with dynamic energy-quality management in 28nm CMOS.
ISSCC
Fabio Frustaci, Mahmood Khayatzadeh, David T. Blaauw, Dennis Sylvester, Massimo Alioto
2014 J jnl
A 346 µm 2 VCO-Based, Reference-Free, Self-Timed Sensor Interface for Cubic-Millimeter Sensor Nodes in 28 nm CMOS.
IEEE J. Solid State Circuits
Laura Fick, David Fick, Massimo Alioto, David T. Blaauw, Dennis Sylvester
2014 J jnl
Comparative soft error evaluation of layout cells in FinFET technology.
Microelectron. Reliab.
Laurent Artola, Guillaume Hubert, Massimo Alioto
2014 — conf
Device-circuit co-design and comparison of ultra-low voltage Tunnel-FET and CMOS digital circuits.
NEWCAS
David Esseni, Massimo Alioto
2014 J jnl
Effectiveness of Leakage Power Analysis Attacks on DPA-Resistant Logic Styles Under Process Variations.
IEEE Trans. Circuits Syst. I Regul. Pap.
Massimo Alioto, Simone Bongiovanni, Milena Djukanovic, Giuseppe Scotti, Alessandro Trifiletti
2014 J jnl
Enhancing the Static Noise Margins by Upsizing Length for Ultra-Low Voltage/Power/Energy Gates.
J. Low Power Electron.
Mihai Tache, Valeriu Beiu, Walid Ibrahim, Fekri Kharbash, Massimo Alioto
2014 — conf
Leakage Power Analysis attacks against a bit slice implementation of the Serpent block cipher.
MIXDES
Massimo Alioto, Simone Bongiovanni, Giuseppe Scotti, Alessandro Trifiletti
2014 J jnl
Novel Class of Energy-Efficient Very High-Speed Conditional Push-Pull Pulsed Latches.
IEEE Trans. Very Large Scale Integr. Syst.
Elio Consoli, Gaetano Palumbo, Jan M. Rabaey, Massimo Alioto
2014 — conf
Performance and Impact of Process Variations in Tunnel-FET Ultra-Low Voltage Digital Circuits.
SBCCI
Massimo Alioto, David Esseni
2014 J jnl
Tunnel FETs for Ultra-Low Voltage Digital VLSI Circuits: Part II-Evaluation at Circuit Level and Design Perspectives.
IEEE Trans. Very Large Scale Integr. Syst.
Massimo Alioto, David Esseni
2014 J jnl
Tunnel FETs for Ultralow Voltage Digital VLSI Circuits: Part I - Device-Circuit Interaction and Evaluation at Device Level.
IEEE Trans. Very Large Scale Integr. Syst.
David Esseni, Manuel Guglielmini, Bernard Kapidani, Tommaso Rollo, Massimo Alioto
2014 — conf
Ultra-low power design approaches for IoT.
Hot Chips Symposium
Massimo Alioto
2013 J jnl
"EChO" Reconfigurable Power Management Unit for Energy Reduction in Sleep-Active Transitions.
IEEE J. Solid State Circuits
Massimo Alioto, Elio Consoli, Jan M. Rabaey
2013 — conf
45pW ESD clamp circuit for ultra-low power applications.
CICC
Yen-Po Chen, Yoonmyung Lee, Jae-Yoon Sim, Massimo Alioto, David T. Blaauw, Dennis Sylvester
2013 — conf
Enabling sizing for enhancing the static noise margins.
ISQED
Valeriu Beiu, Azam Beg, Walid Ibrahim, Fekri Kharbash, Massimo Alioto
2013 Misc conf
New topic session 7B: Challenges and directions for ultra-low voltage VLSI circuits and systems: CMOS and beyond.
VTS
Bozena Kaminska, Bernard Courtois, Massimo Alioto
2012 J jnl
A Simple Circuit Approach to Reduce Delay Variations in Domino Logic Gates.
IEEE Trans. Circuits Syst. I Regul. Pap.
Gaetano Palumbo, Melita Pennisi, Massimo Alioto
2012 C conf
A simple keeper topology to reduce delay variations in nanometer domino logic.
ISCAS
Massimo Alioto, Gaetano Palumbo, Melita Pennisi
2012 — conf
Active RFID: Perpetual wireless communications platform for sensors.
ESSCIRC
Jesse Richmond, Mervin John, Louis P. Alarcón, Wenting Zhou, Wen Li, Tsung-Te Liu, Massimo Alioto, Seth Sanders, Jan M. Rabaey
2012 J jnl
Buried Silicon-Germanium pMOSFETs: Experimental Analysis in VLSI Logic Circuits Under Aggressive Voltage Scaling.
IEEE Trans. Very Large Scale Integr. Syst.
Felice Crupi, Massimo Alioto, Jacopo Franco, Paolo Magnone, Ben Kaczer, Guido Groeseneken, Jérôme Mitard, Liesbeth Witters, Thomas Y. Hoffmann
2012 — conf
Conditional push-pull pulsed latches with 726fJ·ps energy-delay product in 65nm CMOS.
ISSCC
Elio Consoli, Massimo Alioto, Gaetano Palumbo, Jan M. Rabaey
2012 — conf
EChO power management unit with reconfigurable switched-capacitor converter in 65 nm CMOS.
CICC
Massimo Alioto, Elio Consoli, Jan M. Rabaey
2012 J jnl
From energy-delay metrics to constraints on the design of digital circuits.
Int. J. Circuit Theory Appl.
Massimo Alioto, Elio Consoli, Gaetano Palumbo
2012 J jnl
Guest Editorial for the Special Issue on Ultra-Low-Voltage VLSI Circuits and Systems for Green Computing.
IEEE Trans. Circuits Syst. II Express Briefs
Massimo Alioto
2012 J jnl
Mixed FBB/RBB: A Novel Low-Leakage Technique for FinFET Forced Stacks.
IEEE Trans. Very Large Scale Integr. Syst.
Davide Baccarin, David Esseni, Massimo Alioto
2012 — conf
Reconfigurable sleep transistor for GIDL reduction in ultra-low standby power systems.
CICC
Suyoung Bang, David T. Blaauw, Dennis Sylvester, Massimo Alioto
2012 J jnl
Ultra-Low Power VLSI Circuit Design Demystified and Explained: A Tutorial.
IEEE Trans. Circuits Syst. I Regul. Pap.
Massimo Alioto
2012 J jnl
Understanding the Basic Advantages of Bulk FinFETs for Sub- and Near-Threshold Logic Circuits From Device Measurements.
IEEE Trans. Circuits Syst. II Express Briefs
Felice Crupi, Massimo Alioto, Jacopo Franco, Paolo Magnone, Mitsuhiro Togo, N. Horiguchi, Guido Groeseneken
2011 C conf
A novel back-biasing low-leakage technique for FinFET forced stacks.
ISCAS
Davide Baccarin, David Esseni, Massimo Alioto
2011 J jnl
Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part I - Methodology and Design Strategies.
IEEE Trans. Very Large Scale Integr. Syst.
Massimo Alioto, Elio Consoli, Gaetano Palumbo
2011 J jnl
Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part II - Results and Figures of Merit.
IEEE Trans. Very Large Scale Integr. Syst.
Massimo Alioto, Elio Consoli, Gaetano Palumbo
2011 J jnl
Comparative Evaluation of Layout Density in 3T, 4T, and MT FinFET Standard Cells.
IEEE Trans. Very Large Scale Integr. Syst.
Massimo Alioto
2011 C conf
DET FF topologies: A detailed investigation in the energy-delay-area domain.
ISCAS
Massimo Alioto, Elio Consoli, Gaetano Palumbo
2011 C conf
Experimental analysis of buried SiGe pMOSFETs from the perspective of aggressive voltage scaling.
ISCAS
Felice Crupi, Massimo Alioto, Jacopo Franco, Paolo Magnone, Ben Kaczer, Guido Groeseneken, Jérôme Mitard, Liesbeth Witters, Thomas Y. Hoffmann
2011 — conf
Impact of NMOS/PMOS imbalance in Ultra-Low Voltage CMOS standard cells.
ECCTD
Massimo Alioto
2011 C conf
Leakage Power Analysis attacks: Effectiveness on DPA resistant logic styles under process variations.
ISCAS
Milena Djukanovic, Luca Giancane, Giuseppe Scotti, Alessandro Trifiletti, Massimo Alioto
2011 J jnl
Modeling strategies of the input admittance of RC interconnects for VLSI CAD tools.
Microelectron. J.
Massimo Alioto
2011 — conf
Optimization and evaluation of tapered-VTH approach for energy-efficient CMOS buffers.
ECCTD
Fabio Frustaci, Pasquale Corsonello, Massimo Alioto
2011 J jnl
Optimized design of parallel carry-select adders.
Integr.
Massimo Alioto, Gaetano Palumbo, Massimo Poli
2011 C conf
Tapered-VTH CMOS buffer design for improved energy efficiency in deep nanometer technology.
ISCAS
Fabio Frustaci, Pasquale Corsonello, Massimo Alioto
2011 J jnl
Tapered-Vth Approach for Energy-Efficient CMOS Buffers.
IEEE Trans. Circuits Syst. I Regul. Pap.
Fabio Frustaci, Massimo Alioto, Pasquale Corsonello
2011 J jnl
Understanding the Potential and the Limits of Germanium pMOSFETs for VLSI Circuits From Experimental Measurements.
IEEE Trans. Very Large Scale Integr. Syst.
Paolo Magnone, Felice Crupi, Massimo Alioto, Ben Kaczer, Brice De Jaeger
2010 J jnl
A General Power Model of Differential Power Analysis Attacks to Static Logic Circuits.
IEEE Trans. Very Large Scale Integr. Syst.
Massimo Alioto, Massimo Poli, Santina Rocchi
2010 J jnl
A Variability-Tolerant Feedback Technique for Throughput Maximization of Trbgs with Predefined Entropy.
J. Circuits Syst. Comput.
Tommaso Addabbo, Massimo Alioto, Ada Fort, Santina Rocchi, Valerio Vignoli
2010 C conf
Analysis of layout density in FinFET standard cells and impact of fin technology.
ISCAS
Massimo Alioto
2010 C conf
Clock distribution in clock domains with Dual-Edge-Triggered Flip-Flops to improve energy-efficiency.
ISCAS
Massimo Alioto, Elio Consoli, Gaetano Palumbo
2010 C conf
Closed-form analysis of DC noise immunity in subthreshold CMOS logic circuits.
ISCAS
Massimo Alioto
2010 C conf
Design metrics for RTL level estimation of delay variability due to intradie (random) variations.
ISCAS
Michael Merrett, Yangang Wang, Mark Zwolinski, Koushik Maharatna, Massimo Alioto
2010 J jnl
Differential Power Analysis Attacks to Precharged Buses: A General Analysis for Symmetric-Key Cryptographic Algorithms.
IEEE Trans. Dependable Secur. Comput.
Massimo Alioto, Massimo Poli, Santina Rocchi
2010 C conf
Experimental study of leakage-delay trade-off in Germanium pMOSFETs for logic circuits.
ISCAS
Paolo Magnone, Felice Crupi, Massimo Alioto, Ben Kaczer
2010 C conf
Exploiting locality to improve leakage reduction in embedded drowsy I-caches at same area/speed.
ISCAS
Massimo Alioto, Paolo Bennati, Roberto Giorgi
2010 J jnl
Flip-Flop Energy/Performance Versus Clock Slope and Impact on the Clock Network Design.
IEEE Trans. Circuits Syst. I Regul. Pap.
Massimo Alioto, Elio Consoli, Gaetano Palumbo
2010 J jnl
General Strategies to Design Nanometer Flip-Flops in the Energy-Delay Space.
IEEE Trans. Circuits Syst. I Regul. Pap.
Massimo Alioto, Elio Consoli, Gaetano Palumbo
2010 J jnl
Leakage Power Analysis Attacks: A Novel Class of Attacks to Nanometer Cryptographic Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap.
Massimo Alioto, Luca Giancane, Giuseppe Scotti, Alessandro Trifiletti
2010 J jnl
Leakage-Delay Tradeoff in FinFET Logic Circuits: A Comparative Analysis With Bulk Technology.
IEEE Trans. Very Large Scale Integr. Syst.
Matteo Agostinelli, Massimo Alioto, David Esseni, Luca Selmi
2010 J jnl
Optimization of the wire grid size for differential routing: Analysis and impact on the power-delay-area tradeoff.
Microelectron. J.
Massimo Alioto, Stéphane Badel, Yusuf Leblebici
2010 — conf
Physical Design Aware Comparison of Flip-Flops for High-Speed Energy-Efficient VLSI Circuits.
PATMOS
Massimo Alioto, Elio Consoli, Gaetano Palumbo
2010 J jnl
Simple and accurate modeling of the output transition time in nanometer CMOS gates.
Int. J. Circuit Theory Appl.
Massimo Alioto, Gaetano Palumbo, Massimo Poli
2010 J jnl
Understanding DC Behavior of Subthreshold CMOS Logic Through Closed-Form Analysis.
IEEE Trans. Circuits Syst. I Regul. Pap.
Massimo Alioto
2010 J jnl
Understanding the Effect of Process Variations on the Delay of Static and Domino Logic.
IEEE Trans. Very Large Scale Integr. Syst.
Massimo Alioto, Gaetano Palumbo, Melita Pennisi
2009 C conf
Analysis and Design of Ultra-low Power Subthreshold MCML Gates.
ISCAS
Massimo Alioto, Yusuf Leblebici
2009 J jnl
Analysis and Modeling of Energy Consumption in RLC Tree Circuits.
IEEE Trans. Very Large Scale Integr. Syst.
Massimo Alioto, Gaetano Palumbo, Massimo Poli
2009 — conf
Analysis of the impact of random process variations in CMOS tapered buffers.
ICECS
Massimo Alioto, Gaetano Palumbo, Melita Pennisi
2009 — conf
Correct procedures to evaluate the effect of intradie variations on the delay variability of digital circuits.
ECCTD
Massimo Alioto, Elio Consoli, Gaetano Palumbo, Melita Pennisi
2009 — conf
Impact of clock slope on energy/delay of pulsed flip-flops and optimum clock domain design.
ECCTD
Massimo Alioto, Elio Consoli, Gaetano Palumbo
2009 J jnl
Improving Power-Delay Performance of Ultra-Low-Power Subthreshold SCL Circuits.
IEEE Trans. Circuits Syst. II Express Briefs
Armin Tajalli, Massimo Alioto, Yusuf Leblebici
2009 — conf
Leakage Power Analysis attacks: Theoretical analysis and impact of variations.
ICECS
Massimo Alioto, Luca Giancane, Giuseppe Scotti, Alessandro Trifiletti
2009 C conf
Metrics and Design Considerations on the Energy-delay Tradeoff of Digital Circuits.
ISCAS
Massimo Alioto, Elio Consoli, Gaetano Palumbo
2009 C conf
Optimization of Wire Grid Size for Differential Routing and Impact on the Power-delay-area Tradeoff.
ISCAS
Massimo Alioto, Stéphane Badel, Yusuf Leblebici
2009 — conf
Optimum clock slope for flip-flops within a clock domain: Analysis and a case study.
ICECS
Massimo Alioto, Elio Consoli, Gaetano Palumbo
2009 C conf
Understanding Loading Effects of RC Uniform Interconnects.
ISCAS
Massimo Alioto
2008 C conf
A general model for differential power analysis attacks to static logic circuits.
ISCAS
Massimo Alioto, Massimo Poli, Santina Rocchi
2008 C conf
Analysis and performance evaluation of area-efficient true random bit generators on FPGAs.
ISCAS
Massimo Alioto, Luca Fondelli, Santina Rocchi
2008 — conf
Analysis of the impact of process variations on static logic circuits versus fan-in.
ICECS
Massimo Alioto, Gaetano Palumbo, Melita Pennisi
2008 — conf
Design and Evaluation of Mixed 3T-4T FinFET Stacks for Leakage Reduction.
PATMOS
Matteo Agostinelli, Massimo Alioto, David Esseni, Luca Selmi
2008 — conf
Energy evaluation in RLC tree circuits with exponential input.
ICECS
Massimo Alioto, Gaetano Palumbo, Massimo Poli
2008 C conf
Explicit energy evaluation in RLC tree circuits with ramp inputs.
ISCAS
Massimo Alioto, Massimo Poli, Gaetano Palumbo
2008 — conf
Improving the Power-Delay Performance in Subthreshold Source-Coupled Logic Circuits.
PATMOS
Armin Tajalli, Massimo Alioto, Elizabeth J. Brauer, Yusuf Leblebici
2008 C conf
Improving the power-delay product in SCL circuits using source follower output stage.
ISCAS
Armin Tajalli, Frank K. Gürkaynak, Yusuf Leblebici, Massimo Alioto, Elizabeth J. Brauer
2008 J jnl
Power-Aware Design of Nanometer MCML Tapered Buffers.
IEEE Trans. Circuits Syst. II Express Briefs
Massimo Alioto, Gaetano Palumbo
2008 C conf
Power-delay optimization in MCML tapered buffers.
ISCAS
Massimo Alioto, Gaetano Palumbo
2008 — conf
Understanding the Effect of Intradie Random Process Variations in Nanometer Domino Logic.
PATMOS
Massimo Alioto, Gaetano Palumbo, Melita Pennisi
2007 J jnl
A Class of Maximum-Period Nonlinear Congruential Generators Derived From the Rényi Chaotic Map.
IEEE Trans. Circuits Syst. I Regul. Pap.
Tommaso Addabbo, Massimo Alioto, Ada Fort, Antonio Pasini, Santina Rocchi, Valerio Vignoli
2007 — conf
A General Model of DPA Attacks to Precharged Busses in Symmetric-Key Cryptographic Algorithms.
ECCTD
Massimo Alioto, Massimo Poli, Santina Rocchi, Valerio Vignoli
2007 — conf
A Simple and Accurate Model of Input capacitance for Power Estimation in CMOS logic.
ICECS
Massimo Alioto
2007 C conf
Delay Variability Due to Supply Variations in Transmission-Gate Full Adders.
ISCAS
Massimo Alioto, Gaetano Palumbo
2007 C conf
Design of Fast Large Fan-In CMOS Multiplexers Accounting for Interconnects.
ISCAS
Massimo Alioto, Gaetano Palumbo
2007 — conf
Efficient and Accurate Models of Output Transition Time in CMOS Logic.
ICECS
Massimo Alioto, Massimo Poli, Gaetano Palumbo
2007 — conf
Energy consumption in RLC tree circuits.
ECCTD
Massimo Alioto, Gaetano Palumbo, Massimo Poli
2007 C conf
High-Speed/Low-Power Mixed Full Adder Chains: Analysis and Comparison versus Technology.
ISCAS
Massimo Alioto, Gaetano Palumbo
2007 J jnl
Interconnect-Aware Design of Fast Large Fan-In CMOS Multiplexers.
IEEE Trans. Circuits Syst. II Express Briefs
Massimo Alioto, Gaetano Palumbo
2007 C conf
Maximum-Period PRNGs Derived From A Piecewise Linear One-Dimensional Map.
ISCAS
Tommaso Addabbo, Massimo Alioto, Ada Fort, Santina Rocchi, Valerio Vignoli
2007 J jnl
Mixed Full Adder topologies for high-performance low-power arithmetic circuits.
Microelectron. J.
Massimo Alioto, Giuseppe Di Cataldo, Gaetano Palumbo
2007 C conf
Mixed Techniques to Protect Precharged Busses against Differential Power Analysis Attacks.
ISCAS
Massimo Alioto, Massimo Poli, Santina Rocchi, Valerio Vignoli
2007 J jnl
Power-Delay-Area-Noise Margin Tradeoffs in Positive-Feedback MOS Current-Mode Logic.
IEEE Trans. Circuits Syst. I Regul. Pap.
Massimo Alioto, Luca Pancioni, Santina Rocchi, Valerio Vignoli
2007 — conf
Very high-speed carry computation based on mixed dynamic/transmission-gate Full Adders.
ECCTD
Massimo Alioto, Gaetano Palumbo
2006 — conf
A Design Methodology for High-Speed Low-Power MCML Frequency Dividers.
ICECS
Massimo Alioto, Rosario Mita, Gaetano Palumbo
2006 J jnl
A feedback strategy to improve the entropy of a chaos-based random bit generator.
IEEE Trans. Circuits Syst. I Regul. Pap.
Tommaso Addabbo, Massimo Alioto, Ada Fort, Santina Rocchi, Valerio Vignoli
2006 C conf
A technique to design high entropy chaos-based true random bit generators.
ISCAS
Tommaso Addabbo, Massimo Alioto, Ada Fort, Santina Rocchi, Valerio Vignoli
2006 C conf
Analysis and design of MCML gates with hysteresis.
ISCAS
Massimo Alioto, Luca Pancioni, Santina Rocchi, Valerio Vignoli
2006 C conf
Delay uncertainty due to supply variations in static and dynamic full adders.
ISCAS
Massimo Alioto, Gaetano Palumbo
2006 J jnl
Design of High-Speed Power-Efficient MOS Current-Mode Logic Frequency Dividers.
IEEE Trans. Circuits Syst. II Express Briefs
Massimo Alioto, Rosario Mita, Gaetano Palumbo
2006 J jnl
Design strategies of cascaded CML gates.
IEEE Trans. Circuits Syst. II Express Briefs
Massimo Alioto, Gaetano Palumbo
2006 — conf
Efficient Post-Processing Module for a Chaos-based Random Bit Generator.
ICECS
Tommaso Addabbo, Massimo Alioto, Ada Fort, Santina Rocchi, Valerio Vignoli
2006 C conf
Efficient output transition time modeling in CMOS gates with ramp/exponential inputs.
ISCAS
Massimo Alioto, Gaetano Palumbo, Massimo Poli
2006 J jnl
Energy Consumption in RC Tree Circuits.
IEEE Trans. Very Large Scale Integr. Syst.
Massimo Alioto, Gaetano Palumbo, Massimo Poli
2006 J jnl
Exploiting Hysteresys in MCML Circuits.
IEEE Trans. Circuits Syst. II Express Briefs
Massimo Alioto, Luca Pancioni, Santina Rocchi, Valerio Vignoli
2006 J jnl
Impact of Supply Voltage Variations on Full Adder Delay: Analysis and Comparison.
IEEE Trans. Very Large Scale Integr. Syst.
Massimo Alioto, Gaetano Palumbo
2006 J jnl
Low-hardware complexity PRBGs based on a piecewise-linear chaotic map.
IEEE Trans. Circuits Syst. II Express Briefs
Tommaso Addabbo, Massimo Alioto, Ada Fort, Santina Rocchi, Valerio Vignoli
2006 — conf
Modeling of Delay Variability Due to Supply Variations in Pass-Transistor and Static Full Adders.
ICECS
Massimo Alioto, Gaetano Palumbo
2006 C conf
Nanometer MCML gates: models and design considerations.
ISCAS
Massimo Alioto, Gaetano Palumbo
2006 — conf
Power Modeling of Precharged Address Bus and Application to Multi-bit DPA Attacks to DES Algorithm.
PATMOS
Massimo Alioto, Massimo Poli, Santina Rocchi, Valerio Vignoli
2006 — conf
Techniques to Enhance the Resistance of Precharged Busses to Differential Power Analysis.
PATMOS
Massimo Alioto, Massimo Poli, Santina Rocchi, Valerio Vignoli
2006 J jnl
The Digital Tent Map: Performance Analysis and Optimized Design as a Low-Complexity Source of Pseudorandom Bits.
IEEE Trans. Instrum. Meas.
Tommaso Addabbo, Massimo Alioto, Ada Fort, Santina Rocchi, Valerio Vignoli
2005 — conf
An approach to the design of PFSCL gates.
ISCAS (3)
Massimo Alioto, Ada Fort, Luca Pancioni, Santina Rocchi, Valerio Vignoli
2005 — conf
Design techniques for low-power cascaded CML gates.
ISCAS (5)
Massimo Alioto, Gaetano Palumbo
2005 — conf
Energy Consumption in RC Tree Circuits with Exponential Inputs: An Analytical Model.
PATMOS
Massimo Alioto, Gaetano Palumbo, Massimo Poli
2005 — conf
Long period pseudo random bit generators derived from a discretized chaotic map.
ISCAS (2)
Tommaso Addabbo, Massimo Alioto, Ada Fort, Santina Rocchi, Valerio Vignoli
2005 J jnl
Modelling and design considerations on CML gates under high-current effects.
Int. J. Circuit Theory Appl.
Massimo Alioto, Gaetano Palumbo
2005 J jnl
Power-delay optimization of D-latch/MUX source coupled logic gates.
Int. J. Circuit Theory Appl.
Massimo Alioto, Gaetano Palumbo
2004 — conf
A gate-level strategy to design Carry Select Adders.
ISCAS (2)
Massimo Alioto, Gaetano Palumbo, Massimo Poli
2004 J jnl
An efficient implementation of PRNGs based on the digital sawtooth map.
Int. J. Circuit Theory Appl.
Massimo Alioto, Simone Bernardi, Ada Fort, Santina Rocchi, Valerio Vignoli
2004 J jnl
Evaluation of energy consumption in RC ladder circuits driven by a ramp input.
IEEE Trans. Very Large Scale Integr. Syst.
Massimo Alioto, Gaetano Palumbo, Massimo Poli
2004 — conf
Hardware-efficient PRBGs based on 1-D piecewise linear chaotic maps.
ICECS
Tommaso Addabbo, Massimo Alioto, Simone Bernardi, Ada Fort, Santina Rocchi, Valerio Vignoli
2004 J jnl
Modeling and evaluation of positive-feedback source-coupled logic.
IEEE Trans. Circuits Syst. I Regul. Pap.
Massimo Alioto, Luca Pancioni, Santina Rocchi, Valerio Vignoli
2004 — conf
Positive-Feedback Source-Coupled Logic: a delay model.
ISCAS (2)
Massimo Alioto, Ada Fort, Luca Pancioni, Santina Rocchi, Valerio Vignoli
2003 — conf
Analysis and design of digital PRNGS based on the discretized sawtooth map.
ICECS
Massimo Alioto, Simone Bernardi, Ada Fort, Santina Rocchi, Valerio Vignoli
2003 — conf
Design of MUX, XOR and D-latch SCL gates.
ISCAS (5)
Massimo Alioto, Gaetano Palumbo
2003 J jnl
Performance evaluation of the low-voltage CML D-latch topology.
Integr.
Massimo Alioto, Rosario Mita, Gaetano Palumbo
2002 — conf
An Approach to Energy Consumption Modeling in RC Ladder Circuits.
PATMOS
Massimo Alioto, Gaetano Palumbo, Massimo Poli
2002 — conf
Analysis and comparison of low-voltage CML D-latch.
ICECS
Massimo Alioto, Rosario Mita, Gaetano Palumbo
2002 J jnl
Analysis and comparison on full adder block in submicron technology.
IEEE Trans. Very Large Scale Integr. Syst.
Massimo Alioto, Gaetano Palumbo
2002 — conf
Design guidelines for bipolar frequency dividers.
ICECS
Massimo Alioto, Giuseppe Di Cataldo, Gaetano Palumbo
2002 — conf
Modeling Propagation Delay of MUX, XOR, and D-Latch Source-Coupled Logic Gates.
PATMOS
Massimo Alioto, Gaetano Palumbo
2002 J jnl
Modelling of source-coupled logic gates.
Int. J. Circuit Theory Appl.
Massimo Alioto, Gaetano Palumbo, Salvatore Pennisi
2002 — conf
Power-delay trade-offs in SCL gates.
ISCAS (3)
Massimo Alioto, Gaetano Palumbo
2001 — conf
CML ring oscillators: oscillation frequency.
ISCAS (4)
Massimo Alioto, Giuseppe Di Cataldo, Gaetano Palumbo
2001 — conf
Delay estimation of SCL gates with output buffer.
ICECS
Massimo Alioto, Gaetano Palumbo, Salvatore Pennisi
2001 — conf
Optimized design of high fan-in multiplexers using switches with driving capability.
ICECS
Massimo Alioto, Gaetano Palumbo
2001 J jnl
Power estimation in adiabatic circuits: a simple and accurate model.
IEEE Trans. Very Large Scale Integr. Syst.
Massimo Alioto, Gaetano Palumbo
2000 C conf
Evaluation of power consumption in adiabatic circuits.
ISCAS
Massimo Alioto, Gaetano Palumbo
2000 C conf
High-speed bipolar MUX modeling and design.
ISCAS
Massimo Alioto, Gaetano Palumbo
2000 — conf
Modeling of Power Consumption of Adiabatic Gates versus Fan in and Comparison with Conventional Gates.
PATMOS
Massimo Alioto, Gaetano Palumbo
1999 J jnl
Highly accurate and simple models for CML and ECL gates.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Massimo Alioto, Gaetano Palumbo
1998 — conf
Design of CML gate with the best propagation delay.
ICECS
Massimo Alioto, Gaetano Palumbo
1998 — conf
Novel Simple Models Of Cml Propagation Delay.
Great Lakes Symposium on VLSI
Massimo Alioto, Gaetano Palumbo