Masoud Dehyadegari

19 papers A* 1A 1Misc 1Journal 12Unranked 4
YearRankTypeTitle / Venue / Authors
2025 J jnl
Point cloud downsampling based on the transformer features.
Vis. Comput.
Alireza Dehghanpour, Zahra Sharifi, Masoud Dehyadegari
2024 J jnl
A power-efficient approximate approach to improve the computational complexity of coding tools in versatile video coding.
Multim. Tools Appl.
Sina Shah Oveisi, Hoda Roodaki, Morteza Rezaalipour, Masoud Dehyadegari
2024 J jnl
Genetic Cache: A Machine Learning Approach to Designing DRAM Cache Controllers in HBM Systems.
ACM J. Emerg. Technol. Comput. Syst.
Morteza Amouzegar, Morteza Rezaalipour, Masoud Dehyadegari
2023 J jnl
Accurate Low-Bit Length Floating-Point Arithmetic with Sorting Numbers.
Neural Process. Lett.
Alireza Dehghanpour, Javad Khodamoradi Kordestani, Masoud Dehyadegari
2021 Misc conf
G-Arrays: Geometric Arrays for Efficient Point Cloud Processing.
ICASSP
Hoda Roodaki, Masoud Dehyadegari, Mahdi Nazm Bojnordi
2021 J jnl
Linear-time error calculation for approximate adders.
Comput. Electr. Eng.
Morteza Rezaalipour, Masoud Dehyadegari
2021 A* conf
Memristive Data Ranking.
HPCA
Ananth Krishna Prasad, Morteza Rezaalipour, Masoud Dehyadegari, Mahdi Nazm Bojnordi
2020 J jnl
AxMAP: Making Approximate Adders Aware of Input Patterns.
IEEE Trans. Computers
Morteza Rezaalipour, Mohammad Rezaalipour, Masoud Dehyadegari, Mahdi Nazm Bojnordi
2019 J jnl
Designing energy-efficient imprecise adders with multi-bit approximation.
Microelectron. J.
Sarvenaz Tajasob, Morteza Rezaalipour, Masoud Dehyadegari
2019 J jnl
Enhanced graph processing in PIM accelerators with improved queue management.
Microelectron. J.
Mohammad Amin Mosayebi, Arghavan Mohammadhassani, Masoud Dehyadegari
2019 J jnl
IDrAx: A tool-chain for designing efficient approximate adders.
Microelectron. J.
Morteza Rezaalipour, Mohammad Rezaalipour, Sarvenaz Tajasob, Masoud Dehyadegari
2018 A conf
Designing Efficient Imprecise Adders using Multi-bit Approximate Building Blocks.
ISLPED
Sarvenaz Tajasob, Morteza Rezaalipour, Masoud Dehyadegari, Mahdi Nazm Bojnordi
2015 J jnl
Architecture Support for Tightly-Coupled Multi-Core Clusters with Shared-Memory HW Accelerators.
IEEE Trans. Computers
Masoud Dehyadegari, Andrea Marongiu, Mohammad Reza Kakoee, Siamak Mohammadi, Nasser Yazdani, Luca Benini
2013 J jnl
Distributed fair DRAM scheduling in network-on-chips architecture.
J. Syst. Archit.
Masoud Dehyadegari, Siamak Mohammadi, Nasser Yazdani
2013 J jnl
Fuzzy-based Adaptive Routing Algorithm for Networks-on-Chip.
J. Syst. Archit.
Masoumeh Ebrahimi, Hannu Tenhunen, Masoud Dehyadegari
2012 — conf
A tightly-coupled multi-core cluster with shared-memory HW accelerators.
ICSAMOS
Masoud Dehyadegari, Andrea Marongiu, Mohammad Reza Kakoee, Luca Benini, Siamak Mohammadi, Nasser Yazdani
2011 — conf
An adaptive fuzzy logic-based routing algorithm for networks-on-chip.
AHS
Masoud Dehyadegari, Masoud Daneshtalab, Masoumeh Ebrahimi, Juha Plosila, Siamak Mohammadi
2010 — conf
Dual-purpose custom instruction identification algorithm based on Particle Swarm Optimization.
ASAP
Mehdi Kamal, Neda Kazemian Amiri, Arezoo Kamran, Seyyed Alireza Hoseini, Masoud Dehyadegari, Hamid Noori
2005 — conf
Power and delay optimization for network on chip.
ECCTD
Mohsen Nickray, Masoud Dehyadegari, Ali Afzali-Kusha