Masayuki Terai

17 papers A* 5A 2Journal 8Unranked 2
YearRankTypeTitle / Venue / Authors
2008 J jnl
A Parallel Method to Extract Critical Areas of Net Pairs for Diagnosing Bridge Faults.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Keiichi Suemitsu, Toshiaki Ito, Toshiki Kanamoto, Masayuki Terai, Satoshi Kotani, Shigeo Sawada
2008 J jnl
Delayed-ABC SOI for crosstalk noise repair.
IEICE Electron. Express
Akira Tada, Hiromi Notani, Genichi Tanaka, Toshiaki Iwamatsu, Takashi Ipposhi, Masayuki Terai, Masaaki Iijima, Masahiro Numa
2007 J jnl
A Fast Characterizing Method for Large Embedded Memory Modules on SoC.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Masahiko Omura, Toshiki Kanamoto, Michiko Tsukamoto, Mitsutoshi Shirota, Takashi Nakajima, Masayuki Terai
2005 J jnl
A Method of Precise Estimation of Physical Parameters in LSI Interconnect Structures.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Toshiki Kanamoto, Tetsuya Watanabe, Mitsutoshi Shirota, Masayuki Terai, Tatsuya Kunikiyo, Kiyoshi Ishikawa, Yoshihide Ajioka, Yasutaka Horiba
1998 — conf
A CMOS cell generation system for two-dimensional transistor placement.
CICC
Satoshi Shibatani, Toshiyuki Sadakane, Hiroomi Nakao, Masayuki Terai, Kaoru Okazaki
1998 — conf
A new router for reducing "antenna effect" in ASIC design.
CICC
Hiroshi Shirota, Toshiyuki Sadakane, Masayuki Terai, Kaoru Okazaki
1995 J jnl
Min-cut placement with global objective functions for large scale sea-of-gates arrays.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Kazuhiro Takahashi, Kazuo Nakajima, Masayuki Terai, Koji Sato
1994 J jnl
A new approach to over-the-cell channel routing with three layers.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Masayuki Terai, Kazuo Nakajima, Kazuhiro Takahashi, Koji Sato
1994 A conf
Adaptive cut line selection in min-cut placement for large scale sea-of-gates arrays.
ICCAD
Kazuhiro Takahashi, Kazuo Nakajima, Masayuki Terai, Koji Sato
1991 A conf
A New Model for Over-The-Cell Channel Routing with Three Layers.
ICCAD
Masayuki Terai, Kazuhiro Takahashi, Kazuo Nakajima, Koji Sato
1990 A* conf
A New Min-Cut Placement Algorithm for Timing Assurance Layout Design Meeting Net Length Constraint.
DAC
Masayuki Terai, Kazuhiro Takahashi, Koji Sato
1987 J jnl
Symbolic Layout System: Application Results and Functional Improvements.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Masayuki Terai, Yoshihide Ajioka, Tomoyoshi Noda, Masaru Ozaki, Tsunenori Umeki, Koji Sato
1985 J jnl
A Method of Improving the Terminal Assignment in the Channel Routing for Gate Arrays.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Masayuki Terai
1982 A* conf
A consideration of the number of horizontal grids used in the routing of a masterslice layout.
DAC
Masayuki Terai, Hajime Kanada, Koji Sato, Toshihiko Yahara
1981 A* conf
An integrated computer aided design system for gate array masterslices: Part 1. Logic reorganization system LORES-2.
DAC
Chiyoji Tanaka, Shinichi Murai, Shunichiro Nakamura, Takuji Ogihara, Masayuki Terai, Kozo Kinoshita
1981 A* conf
An integrated computer aided design system for gate array masterslices: Part 2 the layout design system MARS-M3.
DAC
Chiyoji Tanaka, Shinichi Murai, Hiroo Tsuji, Toshihiko Yahara, Kaoru Okazaki, Masayuki Terai, Reiji Katoh, Mikio Tachibana
1978 A* conf
LORES - Logic Reorganization System.
DAC
Shunichiro Nakamura, Shinichi Murai, Chiyoji Tanaka, Masayuki Terai, Hideo Fujiwara, Kozo Kinoshita