Masayuki Shimoda

30 papers A 1B 5C 2Journal 9Unranked 13

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	A Novel Data Representation Towards Efficient FPGA-based Quantum Computer Simulation. ISMVL Haruhiko Hasegawa, Masayuki Shimoda, Hiroki Nakahara, Takefumi Miyoshi
2025	C	`conf`	Gap Channel Routing with Fixed Wires. ISCAS Masayuki Shimoda, Atsushi Takahashi, Kosuke Yanagidaira, Mikiko Hirai, Toshikazu Watanabe, Toshimitsu Iwasawa, Chikaaki Kodama
2025	J	`jnl`	Gridless Gap Channel Routing to Minimize Wirelength. IPSJ Trans. Syst. LSI Des. Methodol. Masayuki Shimoda, Atsushi Takahashi
2025	J	`jnl`	Gridless Gap Channel Routing with Variable-Width Wires. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Masayuki Shimoda, Atsushi Takahashi
2025	J	`jnl`	SDG Channel Routing to Minimize Wirelength for Generalized Channel. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Zezhong Wang, Masayuki Shimoda, Atsushi Takahashi
2025	J	`jnl`	UEO Channel Routing Algorithm to Alleviate Local Congestion for Generalized Channels. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Zezhong Wang, Hiroto Nakayama, Masayuki Shimoda, Atsushi Takahashi, Kosuke Yanagidaira, Chikaaki Kodama
2024	—	`conf`	A Table Look-Up Based Quantum Simulation Accelerator on an FPGA. ICFPT Haruhiko Hasegawa, Masayuki Shimoda, Hiroki Nakahara, Takefumi Miyoshi
2024	C	`conf`	BCA Channel Routing to Minimize Wirelength for Generalized Channel Problem. ISCAS Zezhong Wang, Masayuki Shimoda, Atsushi Takahashi
2024	—	`conf`	Wirelength Minimization by Gap Swap-Flip in Gridless Gap Channel Routing. ISOCC Masayuki Shimoda, Atsushi Takahashi
2023	J	`jnl`	Pre- and post-processing techniques for reinforcement-learning-based routing and spectrum assignment in elastic optical networks. J. Opt. Commun. Netw. Takafumi Tanaka, Masayuki Shimoda
2021	J	`jnl`	FPGA-Based Inter-layer Pipelined Accelerators for Filter-Wise Weight-Balanced Sparse Fully Convolutional Networks with Overlapped Tiling. J. Signal Process. Syst. Masayuki Shimoda, Youki Sada, Hiroki Nakahara
2021	—	`conf`	Impact of Operational Mode Selection and Grooming Policies on Auxiliary Graph-Based Multi-layer Network Planning. ECOC Takafumi Tanaka, Masayuki Shimoda
2021	—	`conf`	Mask RSA: End-To-End Reinforcement Learning-based Routing and Spectrum Assignment in Elastic Optical Networks. ECOC Masayuki Shimoda, Takafumi Tanaka
2020	—	`conf`	Fast Monocular Depth Estimation on an FPGA. IPDPS Workshops Youki Sada, Naoto Soga, Masayuki Shimoda, Akira Jinguji, Shimpei Sato, Hiroki Nakahara
2020	J	`jnl`	SENTEI: Filter-Wise Pruning with Distillation towards Efficient Sparse Convolutional Neural Network Accelerators. IEICE Trans. Inf. Syst. Masayuki Shimoda, Youki Sada, Ryosuke Kuramochi, Shimpei Sato, Hiroki Nakahara
2019	—	`conf`	A Dataflow Pipelining Architecture for Tile Segmentation with a Sparse MobileNet on an FPGA. FPT Youki Sada, Masayuki Shimoda, Akira Jinguji, Hiroki Nakahara
2019	B	`conf`	An FPGA Implementation of Real-Time Object Detection with a Thermal Camera. FPL Masayuki Shimoda, Youki Sada, Ryosuke Kuramochi, Hiroki Nakahara
2019	A	`conf`	An FPGA-based Fine Tuning Accelerator for a Sparse CNN. FPGA Hiroki Nakahara, Akira Jinguji, Masayuki Shimoda, Shimpei Sato
2019	B	`conf`	FPGA-Based Training Accelerator Utilizing Sparseness of Convolutional Neural Network. FPL Hiroki Nakahara, Youki Sada, Masayuki Shimoda, Kouki Sayama, Akira Jinguji, Shimpei Sato
2019	—	`conf`	FPGA-based Accurate Pedestrian Detection with Thermal Camera for Surveillance System. ReConFig Ryosuke Kuramochi, Masayuki Shimoda, Youki Sada, Shimpei Sato, Hiroki Nakahara
2019	—	`conf`	Filter-Wise Pruning Approach to FPGA Implementation of Fully Convolutional Network for Semantic Segmentation. ARC Masayuki Shimoda, Youki Sada, Hiroki Nakahara
2019	J	`jnl`	GUINNESS: A GUI Based Binarized Deep Neural Network Framework for Software Programmers. IEICE Trans. Inf. Syst. Hiroki Nakahara, Haruyoshi Yonekawa, Tomoya Fujii, Masayuki Shimoda, Shimpei Sato
2019	—	`conf`	Many Universal Convolution Cores for Ensemble Sparse Convolutional Neural Networks. MCSoC Ryosuke Kuramochi, Youki Sada, Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara
2019	J	`jnl`	Power Efficient Object Detector with an Event-Driven Camera for Moving Object Surveillance on an FPGA. IEICE Trans. Inf. Syst. Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara
2018	B	`conf`	A Demonstration of FPGA-Based You Only Look Once Version2 (YOLOv2). FPL Hiroki Nakahara, Masayuki Shimoda, Shimpei Sato
2018	—	`conf`	A Tri-State Weight Convolutional Neural Network for an FPGA: Applied to YOLOv2 Object Detector. FPT Hiroki Nakahara, Masayuki Shimoda, Shimpei Sato
2018	B	`conf`	Demonstration of Object Detection for Event-Driven Cameras on FPGAs and GPUs. FPL Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara
2018	—	`conf`	Power Efficient Object Detector with an Event-Driven Camera on an FPGA. HEART Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara
2017	B	`conf`	A demonstration of the GUINNESS: A GUI based neural NEtwork SyntheSizer for an FPGA. FPL Hiroyuki Nakahara, Haruyoshi Yonekawa, Tomoya Fujii, Masayuki Shimoda, Simpei Sato
2017	—	`conf`	All binarized convolutional neural network and its implementation on an FPGA. FPT Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara