Masayuki Nakamura

24 papers A* 1A 1B 2Journal 13Unranked 7
YearRankTypeTitle / Venue / Authors
2025 — conf
A mm-Wave Frontend Circuit with High Accuracy Power Levels for ATE to Test 76- to 81- GHz Radar IC.
ITC-Asia
Norio Kobayashi, Minoru Iida, Masayuki Nakamura, Hideki Shirasu
2025 A conf
Push-on mating 57- to 81- GHz mm-Wave interface with high repeatability for ATE application.
ITC
Minoru Iida, Norio Kobayashi, Hideki Shirasu, Masayuki Nakamura
2016 J jnl
Needle Tip Position Accuracy Evaluation Experiment for Puncture Robot in Remote Center Control.
J. Robotics Mechatronics
Kohei Sugiyama, Takayuki Matsuno, Tetsushi Kamegawa, Takao Hiraki, Hirotaka Nakaya, Masayuki Nakamura, Akira Yanou, Mamoru Minami
2015 — conf
The Digital Reminiscence Method: Effect on Dementia in Japanese Day Care Centers.
HCI (17)
Masayuki Nakamura, Takashi Yoshikawa, Kayo Tanaka, Mengyuan Liao, Noriaki Kuwahara
2014 — conf
Energy-aware resource management of virtual machines under thermal and placement constraints.
IGCC
Hideaki Hashimoto, Keigo Matsuo, Kazuaki Chikira, Masayuki Nakamura, Joji Urata
2012 — conf
Proposal of Web Framework for Ubiquitous Sensor Network and Its Trial Application Using NO2 Sensor Mounted on Bicycle.
SAINT
Takayuki Nakamura, Yukio Kikuya, Yutaka Arakawa, Motonori Nakamura, Yuka Higashijima, Yasuko Yamada Maruo, Masayuki Nakamura
2011 J jnl
Collaborative Processing of Wearable and Ambient Sensor System for Blood Pressure Monitoring.
Sensors
Masayuki Nakamura, Jiro Nakamura, Guillaume Lopez, Masaki Shuzo, Ichiro Yamada
2009 J jnl
Distributed Environment Control Using Wireless Sensor/Actuator Networks for Lighting Applications.
Sensors
Masayuki Nakamura, Atsushi Sakurai, Jiro Nakamura
2008 — conf
Adaptive sensor/actuator networks for tracking environment control behaviors.
CSTST
Masayuki Nakamura, Atsushi Sakurai, Takumi Yamada, Jiro Nakamura
2008 J jnl
Collaborative processing in Mote-based sensor/actuator networks for environment control application.
Signal Process.
Masayuki Nakamura, Atsushi Sakurai, Shizuo Furubo, Hiroshi Ban
2008 J jnl
Development of Long-Range and High-Speed Wireless LAN for the Transmission of Telemedicine from Disaster Areas.
EURASIP J. Wirel. Commun. Netw.
Masayuki Nakamura, Shoshin Kubota, Hideaki Takagi, Kiyoshi Einaga, Masashi Yokoyama, Katsuto Mochizuki, Masaomi Takizawa, Sumio Murase
2007 J jnl
An 8.1-ns Column-Access 1.6-Gb/s/pin DDR3 SDRAM With an 8: 4 Multiplexed Data-Transfer Scheme.
IEEE J. Solid State Circuits
Hiroki Fujisawa, Shuichi Kubouchi, Koji Kuroki, Naohisa Nishioka, Yoshiro Riho, Hiromasa Noda, Isamu Fujii, Hideyuki Yoko, Ryuuji Takishita, Takahiro Ito, Hitoshi Tanaka, Masayuki Nakamura
2006 — conf
An 8.4ns Column-Access 1.3Gb/s/pin DDR3 SDRAM with an 8: 4 Multiplexed Data-Transfer Scheme.
ISSCC
Hiroki Fujisawa, Shuichi Kubouchi, Koji Kuroki, Naohisa Nishioka, Yoshiro Riho, Hiromasa Noda, Isamu Fujii, Hideyuki Yoko, Ryuuji Takishita, Takahiro Ito, Hitoshi Tanaka, Masayuki Nakamura
2006 B conf
Improved Collaborative Environment Control Using Mote-based Sensor/Actuator Networks.
LCN
Masayuki Nakamura, Atsushi Sakurai, Toshio Watanabe, Jiro Nakamura, Hiroshi Ban
2005 J jnl
1.8-V 800-Mb/s/pin DDR2 and 2.5-V 400-Mb/s/pin DDR1 compatibly designed 1Gb SDRAM with dual-clock input-latch scheme and hybrid multi-oxide output buffer.
IEEE J. Solid State Circuits
Hiroki Fujisawa, Masayuki Nakamura, Yasuhiro Takai, Yasuji Koshikawa, Tatsuya Matano, Seiji Narui, Narikazu Usuki, Chiaki Dono, Shinichi Miyatake, Makoto Morino, Koji Arai, Shuichi Kubouchi, Isamu Fujii, Hideyuki Yoko, Takao Adachi
2005 A* conf
Is methodology the highway out of verification hell?
DAC
Francine Bacchini, Gabe Moretti, Harry Foster, Janick Bergeron, Masayuki Nakamura, Shrenik Mehta, Laurent Ducousso
2004 J jnl
Improvement of Boosting Algorithm by Modifying the Weighting Rule.
Ann. Math. Artif. Intell.
Masayuki Nakamura, Hiroki Nomiya, Kuniaki Uehara
2003 J jnl
A 1-Gb/s/pin 512-Mb DDRII SDRAM using a digital DLL and a slew-rate-controlled output buffer.
IEEE J. Solid State Circuits
Tatsuya Matano, Yasuhiro Takai, Tsugio Takahashi, Yuusuke Sakito, Isamu Fujii, Yoshihiro Takaishi, Hiroki Fujisawa, Shuichi Kubouchi, Seiji Narui, Koji Arai, Makoto Morino, Masayuki Nakamura, Shinichi Miyatake, Toshihiro Sekiguchi, Kuniaki Koyama
2003 B conf
Study on a noise reduction system of CATV network upstream for data communication.
ICCCN
Masayuki Nakamura, Yuying Yang, Katsumi Wasaki, Yasunari Shidama
2002 J jnl
A low-impedance open-bitline array for multigigabit DRAM.
IEEE J. Solid State Circuits
Tomonori Sekiguchi, Kiyoo Itoh, Tsugio Takahashi, Masahiro Sugaya, Hiroki Fujisawa, Masayuki Nakamura, Kazuhiko Kajigaya, Katsutaka Kimura
2002 — conf
Improvement of Boosting Algorithm by Modifying the Weighting Rule.
AI&M
Masayuki Nakamura, Kuniaki Uehara
2001 J jnl
A dual-phase-controlled dynamic latched amplifier for high-speed and low-power DRAMs.
IEEE J. Solid State Circuits
Hiroki Fujisawa, Tsugio Takahashi, Masayuki Nakamura, Kazuhiko Kajigaya
2001 J jnl
A multigigabit DRAM technology with 6F
IEEE J. Solid State Circuits
Tsugio Takahashi, Tomonori Sekiguchi, Riichiro Takemura, Seiji Narui, Hiroki Fujisawa, Shinichi Miyatake, Makoto Morino, Koji Arai, Satoru Yamada, Shoji Shukuri, Masayuki Nakamura, Yoshitaka Tadaki, Kazuhiko Kajigaya, Katsutaka Kimura, Kiyoo Itoh
1996 J jnl
A 29-ns 64-Mb DRAM with hierarchical array architecture.
IEEE J. Solid State Circuits
Masayuki Nakamura, Tugio Takahashi, Takesada Akiba, Goro Kitsukawa, Makoto Morino, Toshihiro Sekiguchi, Isamu Asano, Katsuo Komatsuzaki, Yoshitaka Tadaki, Songsu Cho, Kazuhiko Kajigaya, Tadashi Tachibana, Katsuyuki Sato