Masayuki Mizuno

44 papers A 1B 1Misc 3Journal 24Unranked 15

Year	Rank	Type	Title / Venue / Authors
2019	B	`conf`	Formal Verifications of Call-by-Need and Call-by-Name Evaluations with Mutual Recursion. APLAS Masayuki Mizuno, Eijiro Sumii
2019	J	`jnl`	The numerical analysis of mass evacuation in Taipei 101 with control volume model. Simul. Model. Pract. Theory Guan-Yuan Wu, Masayuki Mizuno
2018	Misc	`conf`	Formal Verification of the Correspondence Between Call-by-Need and Call-by-Name. FLOPS Masayuki Mizuno, Eijiro Sumii
2013	—	`conf`	A 5.5Gb/s 5mm contactless interface containing a 50Mb/s bidirectional sub-channel employing common-mode OOK signaling. ISSCC Ken'ichiro Hijioka, Masaharu Matsudaira, Koichi Yamaguchi, Masayuki Mizuno
2012	J	`jnl`	A 2.5 kV Isolation 35 kV/us CMR 250 Mbps Digital Isolator in Standard CMOS With a Small Transformer Driving Technique. IEEE J. Solid State Circuits Shunichi Kaeriyama, Shinichi Uchida, Masayuki Furumiya, Mitsuji Okada, Tadashi Maeda, Masayuki Mizuno
2012	J	`jnl`	A 27% Active-Power-Reduced 40-nm CMOS Multimedia SoC With Adaptive Voltage Scaling Using Distributed Universal Delay Lines. IEEE J. Solid State Circuits Yoshifumi Ikenaga, Masahiro Nomura, Shuji Suenaga, Hideo Sonohara, Yoshitaka Horikoshi, Toshiyuki Saito, Yukio Ohdaira, Yoichiro Nishio, Tomohiro Iwashita, Miyuki Satou, Koji Nishida, Koichi Nose, Koichiro Noguchi, Yoshihiro Hayashi, Masayuki Mizuno
2012	—	`conf`	A 280nW, 100kHz, 1-cycle start-up time, on-chip CMOS relaxation oscillator employing a feedforward period control scheme. VLSIC Takashi Tokairin, Koichi Nose, Koichi Takeda, Koichiro Noguchi, Tadashi Maeda, Kazuyoshi Kawai, Masayuki Mizuno
2011	J	`jnl`	A Clock Generator with Clock Period, Duty-Ratio and I/Q-Balance Adjustment Capabilities for On-Chip Timing-Margin Tests. IEICE Trans. Electron. Shunichi Kaeriyama, Mikihiro Kajita, Masayuki Mizuno
2011	J	`jnl`	A Duobinary Signaling for Asymmetric Multi-Chip Communication. IEICE Trans. Electron. Koichi Yamaguchi, Masayuki Mizuno
2011	J	`jnl`	Dicode Partial Response Signaling over Inductively-Coupled Channel. IEICE Trans. Electron. Koichi Yamaguchi, Masayuki Mizuno
2010	J	`jnl`	A 0.2 mm IEEE J. Solid State Circuits Haruya Ishizaki, Masayuki Mizuno
2010	—	`conf`	A 16Gb/s 1 ISSCC Hideyuki Sugita, Kazuhisa Sunaga, Koichi Yamaguchi, Masayuki Mizuno
2010	—	`conf`	A 6Gb/s receiver with discrete-time based channel filtering for wireline FDM communications. CICC Tsutomu Takeya, Kazuhisa Sunaga, Koichi Yamaguchi, Hideyuki Sugita, Yoichi Yoshida, Masayuki Mizuno, Tadahiro Kuroda
2010	J	`jnl`	A Chip-Stacked Memory for On-Chip SRAM-Rich SoCs and Processors. IEEE J. Solid State Circuits Hideaki Saito, Masayuki Nakajima, Takumi Okamoto, Yusuke Yamada, Akira Ohuchi, Noriyuki Iguchi, Toshitsugu Sakamoto, Koichi Yamaguchi, Masayuki Mizuno
2010	—	`conf`	A precise-tracking NBTI-degradation monitor independent of NBTI recovery effect. ISSCC Eisuke Saneyoshi, Koichi Nose, Masayuki Mizuno
2010	J	`jnl`	An Inductive-Coupling DC Voltage Transceiver for Highly Parallel Wafer-Level Testing. IEEE J. Solid State Circuits Yoichi Yoshida, Koichi Nose, Yoshihiro Nakagawa, Koichiro Noguchi, Yasuhiro Morita, Masamoto Tago, Masayuki Mizuno, Tadahiro Kuroda
2010	Misc	`conf`	Gate-oxide early-life failure identification using delay shifts. VTS Young Moon Kim, Tze Wee Chen, Yoshio Kameda, Masayuki Mizuno, Subhasish Mitra
2009	J	`jnl`	A 2.0 Gb/s Clock-Embedded Interface for Full-HD 10-Bit 120 Hz LCD Drivers With 1/5-Rate Noise-Tolerant Phase and Frequency Recovery. IEEE J. Solid State Circuits Koichi Yamaguchi, Yoshihiko Hori, Keiichi Nakajima, Kazumasa Suzuki, Masayuki Mizuno, Hiroshi Hayama
2009	—	`conf`	A 2.0Gb/s clock-embedded interface for full-HD 10b 120Hz LCD drivers with 1/5-rate noise-tolerant phase and frequency recovery. ISSCC Koichi Yamaguchi, Yoshihiko Hori, Keiichi Nakajima, Kazumasa Suzuki, Masayuki Mizuno, Hiroshi Hayama
2009	—	`conf`	A chip-stacked memory for on-chip SRAM-rich SoCs and processors. ISSCC Hideaki Saito, Masayuki Nakajima, Takumi Okamoto, Yusuke Yamada, Akira Ohuchi, Noriyuki Iguchi, Toshitsugu Sakamoto, Koichi Yamaguchi, Masayuki Mizuno
2009	A	`conf`	Basis-motion torque composition approach: generation of feedforward inputs for control of multi-joint robots. IROS Masahiro Sekimoto, Sadao Kawamura, Tomoya Ishitsubo, Shinsuke Akizuki, Masayuki Mizuno
2009	J	`jnl`	Introduction to the Special Issue on the 2008 Symposium on VLSI Circuits. IEEE J. Solid State Circuits Katsu Nakamura, Masayuki Mizuno
2009	J	`jnl`	On-Chip Optical Interconnect. Proc. IEEE Keishi Ohashi, Kenichi Nishi, Takanori Shimizu, Masafumi Nakada, Junichi Fujikata, Jun Ushida, Sunao Torii, Koichi Nose, Masayuki Mizuno, Hiroaki Yukawa, Masao Kinoshita, Nobuo Suzuki, Akiko Gomyo, Tsutomu Ishi, Daisuke Okamoto, Katsuya Furue, Toshihide Ueno, Tai Tsuchizawa, Toshifumi Watanabe, Koji Yamada, Seiichi Itabashi, Jun Akedo
2009	—	`conf`	Wireless DC voltage transmission using inductive-coupling channelfor highly-parallel wafer-level testing. ISSCC Yoichi Yoshida, Koichi Nose, Yoshihiro Nakagawa, Koichiro Noguchi, Yasuhiro Morita, Masamoto Tago, Tadahiro Kuroda, Masayuki Mizuno
2008	J	`jnl`	A 0.016 mm IEEE J. Solid State Circuits Koichi Nose, Masayuki Mizuno
2008	J	`jnl`	LSI On-Chip Optical Interconnection with Si Nano-Photonics. IEICE Trans. Electron. Junichi Fujikata, Kenichi Nishi, Akiko Gomyo, Jun Ushida, Tsutomu Ishi, Hiroaki Yukawa, Daisuke Okamoto, Masafumi Nakada, Takanori Shimizu, Masao Kinoshita, Koichi Nose, Masayuki Mizuno, Tai Tsuchizawa, Toshifumi Watanabe, Koji Yamada, Seiichi Itabashi, Keishi Ohashi
2007	—	`conf`	A 1-to-2GHz 4-Phase On-Chip Clock Generator with Timing-Margin Test Capability. ISSCC Shunichi Kaeriyama, Mikihiro Kajita, Masayuki Mizuno
2007	J	`jnl`	Daisy Chain Transmitter for Power Reduction in Inductive-Coupling CMOS Link. IEICE Trans. Electron. Kiichi Niitsu, Noriyuki Miura, Mari Inoue, Yoshihiro Nakagawa, Masamoto Tago, Masayuki Mizuno, Takayasu Sakurai, Tadahiro Kuroda
2007	—	`conf`	Fine-Grain Redundant Logic Using Defect-Prediction Flip-Flops. ISSCC Toru Nakura, Koichi Nose, Masayuki Mizuno
2007	—	`conf`	LAGS System Using Data/Instruction Grain Power Control. ISSCC Makoto Ikeda, Taku Sogabe, Ken Ishii, Masayuki Mizuno, Toru Nakura, Koichi Nose, Kunihiro Asada
2006	J	`jnl`	A 1-ps Resolution Jitter-Measurement Macro Using Interpolated Jitter Oversampling. IEEE J. Solid State Circuits Koichi Nose, Mikihiro Kajita, Masayuki Mizuno
2006	—	`conf`	A 1ps-Resolution Jitter-Measurement Macro Using Interpolated Jitter Oversampling. ISSCC Koichi Nose, Mikihiro Kajita, Masayuki Mizuno
2006	—	`conf`	Optical interconnect technologies for high-speed VLSI chips using silicon nano-photonics. ISSCC Keishi Ohashi, Junichi Fujikata, Masafumi Nakada, Tsutomu Ishi, Kenichi Nishi, Hirohito Yamada, Muneo Fukaishi, Masayuki Mizuno, Koichi Nose, Ichiro Ogura, Yutaka Urino, Toshio Baba
2006	J	`jnl`	Solid-Electrolyte Nanometer Switch. IEICE Trans. Electron. Naoki Banno, Toshitsugu Sakamoto, Noriyuki Iguchi, Hisao Kawaura, Shunichi Kaeriyama, Masayuki Mizuno, Kazuya Terabe, Tsuyoshi Hasegawa, Masakazu Aono
2005	J	`jnl`	A 6.7-fF/μm IEEE J. Solid State Circuits Makoto Takamiya, Masayuki Mizuno
2005	J	`jnl`	A nonvolatile programmable solid-electrolyte nanometer switch. IEEE J. Solid State Circuits Shunichi Kaeriyama, Toshitsugu Sakamoto, Hiroshi Sunamura, Masayuki Mizuno, Hisao Kawaura, Tsuyoshi Hasegawa, Kazuya Terabe, Tomonobu Nakayama, Masakazu Aono
2004	—	`conf`	Frequency-hopping vernier clock generators for multiple clock domain SoCs. CICC Hiroshi Kodama, Masayuki Mizuno, Koichi Nose, Akio Tanaka
2003	J	`jnl`	A 0.13-μm CMOS 5-Gb/s 10-m 28AWG cable transceiver with no-feedback-loop continuous-time post-equalizer. IEEE J. Solid State Circuits Yoshiharu Kudoh, Muneo Fukaishi, Masayuki Mizuno
2001	—	`conf`	A 0.10 μm CMOS, 1.2 V, 2 GHz phase-locked loop with gain compensation VCO. CICC Koichiro Minami, Muneo Fukaishi, Masayuki Mizuno, Hideaki Onishi, Kenji Noda, Kiyotaka Imai, Tadahiko Horiuchi, Hiroshi Yamaguchi, Takanori Sato, Kazuyuki Nakamura, Masakazu Yaniashina
1999	J	`jnl`	A 2000-MOPS embedded RISC processor with a Rambus DRAM controller. IEEE J. Solid State Circuits Kazumasa Suzuki, Masayuki Daito, Tomoo Inoue, Kouhei Nadehara, Masahiro Nomura, Masayuki Mizuno, Tomofumi Iima, Shoichiro Sato, Terumi Fukuda, Tomohisa Arai, Ichiro Kuroda, Masakazu Yamashina
1997	J	`jnl`	A 1.5-W single-chip MPEG-2 MP@ML video encoder with low power motion estimation and clocking. IEEE J. Solid State Circuits Masayuki Mizuno, Yasushi Ooi, Naoya Hayashi, Junichi Goto, Masatoshi Hozumi, Koichiro Furuta, Atsufumi Shibayama, Yoetsu Nakazawa, Osamu Ohnishi, Shu-Yu Zhu, Yutaka Yokoyama, Yoichi Katayama, Hideto Takano, Noriyuki Miki, Yuzo Senda, Ichiro Tamitani, Masakazu Yamashina
1997	Misc	`conf`	An MPEG-2 encoder architecture based on a single-chip dedicated LSI with a control MPU. ICASSP Yasushi Ooi, Osamu Ohnishi, Yutaka Yokoyama, Yoichi Katayama, Masayuki Mizuno, Masakazu Yamashina, Hideo Takano, Naoya Hayashi, Ichiro Tamitani
1996	J	`jnl`	A GHz MOS adaptive pipeline technique using MOS current-mode logic. IEEE J. Solid State Circuits Masayuki Mizuno, Masakazu Yamashina, Koichiro Furuta, Hiroyuki Igura, Hitoshi Abiko, Kazuhiro Okabe, Atsuki Ono, Hachiro Yamada
1996	J	`jnl`	Capacitance coupling immune, transient sensitive accelerator for resistive interconnect signals of subquarter micron ULSI. IEEE J. Solid State Circuits Tomofumi lima, Masayuki Mizuno, Tadahiko Horiuchi, Masakazu Yamashina